setup.c (8cf72172d739639f2699131821a3ebc291287cf2) setup.c (18d7f152df31e5a326301fdaad385e40874dff80)
1/*
2 * linux/arch/arm/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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32#include <linux/sort.h>
33
34#include <asm/unified.h>
35#include <asm/cp15.h>
36#include <asm/cpu.h>
37#include <asm/cputype.h>
38#include <asm/elf.h>
39#include <asm/procinfo.h>
1/*
2 * linux/arch/arm/kernel/setup.c
3 *
4 * Copyright (C) 1995-2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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32#include <linux/sort.h>
33
34#include <asm/unified.h>
35#include <asm/cp15.h>
36#include <asm/cpu.h>
37#include <asm/cputype.h>
38#include <asm/elf.h>
39#include <asm/procinfo.h>
40#include <asm/psci.h>
41#include <asm/sections.h>
42#include <asm/setup.h>
43#include <asm/smp_plat.h>
44#include <asm/mach-types.h>
45#include <asm/cacheflush.h>
46#include <asm/cachetype.h>
47#include <asm/tlbflush.h>
48

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124int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
125
126struct stack {
127 u32 irq[3];
128 u32 abt[3];
129 u32 und[3];
130} ____cacheline_aligned;
131
40#include <asm/sections.h>
41#include <asm/setup.h>
42#include <asm/smp_plat.h>
43#include <asm/mach-types.h>
44#include <asm/cacheflush.h>
45#include <asm/cachetype.h>
46#include <asm/tlbflush.h>
47

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123int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
124
125struct stack {
126 u32 irq[3];
127 u32 abt[3];
128 u32 und[3];
129} ____cacheline_aligned;
130
132#ifndef CONFIG_CPU_V7M
133static struct stack stacks[NR_CPUS];
131static struct stack stacks[NR_CPUS];
134#endif
135
136char elf_platform[ELF_PLATFORM_SIZE];
137EXPORT_SYMBOL(elf_platform);
138
139static const char *cpu_name;
140static const char *machine_name;
141static char __initdata cmd_line[COMMAND_LINE_SIZE];
142struct machine_desc *machine_desc __initdata;

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205 "4",
206 "4T",
207 "5",
208 "5T",
209 "5TE",
210 "5TEJ",
211 "6TEJ",
212 "7",
132
133char elf_platform[ELF_PLATFORM_SIZE];
134EXPORT_SYMBOL(elf_platform);
135
136static const char *cpu_name;
137static const char *machine_name;
138static char __initdata cmd_line[COMMAND_LINE_SIZE];
139struct machine_desc *machine_desc __initdata;

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202 "4",
203 "4T",
204 "5",
205 "5T",
206 "5TE",
207 "5TEJ",
208 "6TEJ",
209 "7",
213 "7M",
210 "?(11)",
214 "?(12)",
215 "?(13)",
216 "?(14)",
217 "?(15)",
218 "?(16)",
219 "?(17)",
220};
221
211 "?(12)",
212 "?(13)",
213 "?(14)",
214 "?(15)",
215 "?(16)",
216 "?(17)",
217};
218
222#ifdef CONFIG_CPU_V7M
223static int __get_cpu_architecture(void)
224{
219static int __get_cpu_architecture(void)
220{
225 return CPU_ARCH_ARMv7M;
226}
227#else
228static int __get_cpu_architecture(void)
229{
230 int cpu_arch;
231
232 if ((read_cpuid_id() & 0x0008f000) == 0) {
233 cpu_arch = CPU_ARCH_UNKNOWN;
234 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
235 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
236 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
237 cpu_arch = (read_cpuid_id() >> 16) & 7;

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252 cpu_arch = CPU_ARCH_ARMv6;
253 else
254 cpu_arch = CPU_ARCH_UNKNOWN;
255 } else
256 cpu_arch = CPU_ARCH_UNKNOWN;
257
258 return cpu_arch;
259}
221 int cpu_arch;
222
223 if ((read_cpuid_id() & 0x0008f000) == 0) {
224 cpu_arch = CPU_ARCH_UNKNOWN;
225 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
226 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
227 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
228 cpu_arch = (read_cpuid_id() >> 16) & 7;

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243 cpu_arch = CPU_ARCH_ARMv6;
244 else
245 cpu_arch = CPU_ARCH_UNKNOWN;
246 } else
247 cpu_arch = CPU_ARCH_UNKNOWN;
248
249 return cpu_arch;
250}
260#endif
261
262int __pure cpu_architecture(void)
263{
264 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
265
266 return __cpu_architecture;
267}
268

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298
299 return aliasing_icache;
300}
301
302static void __init cacheid_init(void)
303{
304 unsigned int arch = cpu_architecture();
305
251
252int __pure cpu_architecture(void)
253{
254 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
255
256 return __cpu_architecture;
257}
258

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288
289 return aliasing_icache;
290}
291
292static void __init cacheid_init(void)
293{
294 unsigned int arch = cpu_architecture();
295
306 if (arch == CPU_ARCH_ARMv7M) {
307 cacheid = 0;
308 } else if (arch >= CPU_ARCH_ARMv6) {
296 if (arch >= CPU_ARCH_ARMv6) {
309 unsigned int cachetype = read_cpuid_cachetype();
310 if ((cachetype & (7 << 29)) == 4 << 29) {
311 /* ARMv7 register format */
312 arch = CPU_ARCH_ARMv7;
313 cacheid = CACHEID_VIPT_NONALIASING;
314 switch (cachetype & (3 << 14)) {
315 case (1 << 14):
316 cacheid |= CACHEID_ASID_TAGGED;

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362#ifdef CONFIG_DEBUG_LL
363 printascii(buf);
364#endif
365 printk("%s", buf);
366}
367
368static void __init cpuid_init_hwcaps(void)
369{
297 unsigned int cachetype = read_cpuid_cachetype();
298 if ((cachetype & (7 << 29)) == 4 << 29) {
299 /* ARMv7 register format */
300 arch = CPU_ARCH_ARMv7;
301 cacheid = CACHEID_VIPT_NONALIASING;
302 switch (cachetype & (3 << 14)) {
303 case (1 << 14):
304 cacheid |= CACHEID_ASID_TAGGED;

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350#ifdef CONFIG_DEBUG_LL
351 printascii(buf);
352#endif
353 printk("%s", buf);
354}
355
356static void __init cpuid_init_hwcaps(void)
357{
370 unsigned int divide_instrs, vmsa;
358 unsigned int divide_instrs;
371
372 if (cpu_architecture() < CPU_ARCH_ARMv7)
373 return;
374
375 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
376
377 switch (divide_instrs) {
378 case 2:
379 elf_hwcap |= HWCAP_IDIVA;
380 case 1:
381 elf_hwcap |= HWCAP_IDIVT;
382 }
359
360 if (cpu_architecture() < CPU_ARCH_ARMv7)
361 return;
362
363 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
364
365 switch (divide_instrs) {
366 case 2:
367 elf_hwcap |= HWCAP_IDIVA;
368 case 1:
369 elf_hwcap |= HWCAP_IDIVT;
370 }
383
384 /* LPAE implies atomic ldrd/strd instructions */
385 vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
386 if (vmsa >= 5)
387 elf_hwcap |= HWCAP_LPAE;
388}
389
390static void __init feat_v6_fixup(void)
391{
392 int id = read_cpuid_id();
393
394 if ((id & 0xff0f0000) != 0x41070000)
395 return;

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404
405/*
406 * cpu_init - initialise one CPU.
407 *
408 * cpu_init sets up the per-CPU stacks.
409 */
410void notrace cpu_init(void)
411{
371}
372
373static void __init feat_v6_fixup(void)
374{
375 int id = read_cpuid_id();
376
377 if ((id & 0xff0f0000) != 0x41070000)
378 return;

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387
388/*
389 * cpu_init - initialise one CPU.
390 *
391 * cpu_init sets up the per-CPU stacks.
392 */
393void notrace cpu_init(void)
394{
412#ifndef CONFIG_CPU_V7M
413 unsigned int cpu = smp_processor_id();
414 struct stack *stk = &stacks[cpu];
415
416 if (cpu >= NR_CPUS) {
417 printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
418 BUG();
419 }
420

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455 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
456 "I" (offsetof(struct stack, irq[0])),
457 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
458 "I" (offsetof(struct stack, abt[0])),
459 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
460 "I" (offsetof(struct stack, und[0])),
461 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
462 : "r14");
395 unsigned int cpu = smp_processor_id();
396 struct stack *stk = &stacks[cpu];
397
398 if (cpu >= NR_CPUS) {
399 printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
400 BUG();
401 }
402

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437 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
438 "I" (offsetof(struct stack, irq[0])),
439 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
440 "I" (offsetof(struct stack, abt[0])),
441 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
442 "I" (offsetof(struct stack, und[0])),
443 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
444 : "r14");
463#endif
464}
465
445}
446
466int __cpu_logical_map[NR_CPUS];
447u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
467
468void __init smp_setup_processor_id(void)
469{
470 int i;
471 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
472 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
473
474 cpu_logical_map(0) = cpu;
475 for (i = 1; i < nr_cpu_ids; ++i)
476 cpu_logical_map(i) = i == cpu ? 0 : i;
477
478 printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
479}
480
448
449void __init smp_setup_processor_id(void)
450{
451 int i;
452 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
453 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
454
455 cpu_logical_map(0) = cpu;
456 for (i = 1; i < nr_cpu_ids; ++i)
457 cpu_logical_map(i) = i == cpu ? 0 : i;
458
459 printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
460}
461
481struct mpidr_hash mpidr_hash;
482#ifdef CONFIG_SMP
483/**
484 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
485 * level in order to build a linear index from an
486 * MPIDR value. Resulting algorithm is a collision
487 * free hash carried out through shifting and ORing
488 */
489static void __init smp_build_mpidr_hash(void)
490{
491 u32 i, affinity;
492 u32 fs[3], bits[3], ls, mask = 0;
493 /*
494 * Pre-scan the list of MPIDRS and filter out bits that do
495 * not contribute to affinity levels, ie they never toggle.
496 */
497 for_each_possible_cpu(i)
498 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
499 pr_debug("mask of set bits 0x%x\n", mask);
500 /*
501 * Find and stash the last and first bit set at all affinity levels to
502 * check how many bits are required to represent them.
503 */
504 for (i = 0; i < 3; i++) {
505 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
506 /*
507 * Find the MSB bit and LSB bits position
508 * to determine how many bits are required
509 * to express the affinity level.
510 */
511 ls = fls(affinity);
512 fs[i] = affinity ? ffs(affinity) - 1 : 0;
513 bits[i] = ls - fs[i];
514 }
515 /*
516 * An index can be created from the MPIDR by isolating the
517 * significant bits at each affinity level and by shifting
518 * them in order to compress the 24 bits values space to a
519 * compressed set of values. This is equivalent to hashing
520 * the MPIDR through shifting and ORing. It is a collision free
521 * hash though not minimal since some levels might contain a number
522 * of CPUs that is not an exact power of 2 and their bit
523 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
524 */
525 mpidr_hash.shift_aff[0] = fs[0];
526 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
527 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
528 (bits[1] + bits[0]);
529 mpidr_hash.mask = mask;
530 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
531 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
532 mpidr_hash.shift_aff[0],
533 mpidr_hash.shift_aff[1],
534 mpidr_hash.shift_aff[2],
535 mpidr_hash.mask,
536 mpidr_hash.bits);
537 /*
538 * 4x is an arbitrary value used to warn on a hash table much bigger
539 * than expected on most systems.
540 */
541 if (mpidr_hash_size() > 4 * num_possible_cpus())
542 pr_warn("Large number of MPIDR hash buckets detected\n");
543 sync_cache_w(&mpidr_hash);
544}
545#endif
546
547static void __init setup_processor(void)
548{
549 struct proc_info_list *list;
550
551 /*
552 * locate processor in the list of supported processor
553 * types. The linker builds this table for us from the
554 * entries in arch/arm/mm/proc-*.S

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876 request_standard_resources(mdesc);
877
878 if (mdesc->restart)
879 arm_pm_restart = mdesc->restart;
880
881 unflatten_device_tree();
882
883 arm_dt_init_cpu_maps();
462static void __init setup_processor(void)
463{
464 struct proc_info_list *list;
465
466 /*
467 * locate processor in the list of supported processor
468 * types. The linker builds this table for us from the
469 * entries in arch/arm/mm/proc-*.S

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791 request_standard_resources(mdesc);
792
793 if (mdesc->restart)
794 arm_pm_restart = mdesc->restart;
795
796 unflatten_device_tree();
797
798 arm_dt_init_cpu_maps();
884 psci_init();
885#ifdef CONFIG_SMP
886 if (is_smp()) {
799#ifdef CONFIG_SMP
800 if (is_smp()) {
887 if (!mdesc->smp_init || !mdesc->smp_init()) {
888 if (psci_smp_available())
889 smp_set_ops(&psci_smp_ops);
890 else if (mdesc->smp)
891 smp_set_ops(mdesc->smp);
892 }
801 smp_set_ops(mdesc->smp);
893 smp_init_cpus();
802 smp_init_cpus();
894 smp_build_mpidr_hash();
895 }
896#endif
897
898 if (!is_smp())
899 hyp_mode_check();
900
901 reserve_crashkernel();
902

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959 "thumbee",
960 "neon",
961 "vfpv3",
962 "vfpv3d16",
963 "tls",
964 "vfpv4",
965 "idiva",
966 "idivt",
803 }
804#endif
805
806 if (!is_smp())
807 hyp_mode_check();
808
809 reserve_crashkernel();
810

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867 "thumbee",
868 "neon",
869 "vfpv3",
870 "vfpv3d16",
871 "tls",
872 "vfpv4",
873 "idiva",
874 "idivt",
967 "lpae",
968 NULL
969};
970
971static int c_show(struct seq_file *m, void *v)
972{
973 int i, j;
974 u32 cpuid;
975

--- 79 unchanged lines hidden --- 		875 NULL
876};
877
878static int c_show(struct seq_file *m, void *v)
879{
880 int i, j;
881 u32 cpuid;
882

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