iwmmxt.S (a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0) iwmmxt.S (b9920fdd5a751df129808e7fa512e9928223ee05)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/kernel/iwmmxt.S
4 *
5 * XScale iWMMXt (Concan) context switching and handling
6 *
7 * Initial code:
8 * Copyright (c) 2003, Intel Corporation

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13
14#include <linux/linkage.h>
15#include <asm/ptrace.h>
16#include <asm/thread_info.h>
17#include <asm/asm-offsets.h>
18#include <asm/assembler.h>
19#include "iwmmxt.h"
20
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/kernel/iwmmxt.S
4 *
5 * XScale iWMMXt (Concan) context switching and handling
6 *
7 * Initial code:
8 * Copyright (c) 2003, Intel Corporation

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13
14#include <linux/linkage.h>
15#include <asm/ptrace.h>
16#include <asm/thread_info.h>
17#include <asm/asm-offsets.h>
18#include <asm/assembler.h>
19#include "iwmmxt.h"
20
21#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
22#define PJ4(code...) code
23#define XSC(code...)
24#elif defined(CONFIG_CPU_MOHAWK) || \
25 defined(CONFIG_CPU_XSC3) || \
26 defined(CONFIG_CPU_XSCALE)
27#define PJ4(code...)
28#define XSC(code...) code
29#else
30#error "Unsupported iWMMXt architecture"
31#endif
32
33#define MMX_WR0 (0x00)
34#define MMX_WR1 (0x08)
35#define MMX_WR2 (0x10)
36#define MMX_WR3 (0x18)
37#define MMX_WR4 (0x20)
38#define MMX_WR5 (0x28)
39#define MMX_WR6 (0x30)
40#define MMX_WR7 (0x38)

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76 * lr = undefined instr exit
77 *
78 * called from prefetch exception handler with interrupts enabled
79 */
80
81ENTRY(iwmmxt_task_enable)
82 inc_preempt_count r10, r3
83
21#define MMX_WR0 (0x00)
22#define MMX_WR1 (0x08)
23#define MMX_WR2 (0x10)
24#define MMX_WR3 (0x18)
25#define MMX_WR4 (0x20)
26#define MMX_WR5 (0x28)
27#define MMX_WR6 (0x30)
28#define MMX_WR7 (0x38)

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64 * lr = undefined instr exit
65 *
66 * called from prefetch exception handler with interrupts enabled
67 */
68
69ENTRY(iwmmxt_task_enable)
70 inc_preempt_count r10, r3
71
84 XSC(mrc p15, 0, r2, c15, c1, 0)
85 PJ4(mrc p15, 0, r2, c1, c0, 2)
72 mrc p15, 0, r2, c15, c1, 0
86 @ CP0 and CP1 accessible?
73 @ CP0 and CP1 accessible?
87 XSC(tst r2, #0x3)
88 PJ4(tst r2, #0xf)
74 tst r2, #0x3
89 bne 4f @ if so no business here
90 @ enable access to CP0 and CP1
75 bne 4f @ if so no business here
76 @ enable access to CP0 and CP1
91 XSC(orr r2, r2, #0x3)
92 XSC(mcr p15, 0, r2, c15, c1, 0)
93 PJ4(orr r2, r2, #0xf)
94 PJ4(mcr p15, 0, r2, c1, c0, 2)
77 orr r2, r2, #0x3
78 mcr p15, 0, r2, c15, c1, 0
95
96 ldr r3, =concan_owner
97 ldr r2, [r0, #S_PC] @ current task pc value
98 ldr r1, [r3] @ get current Concan owner
99 sub r2, r2, #4 @ adjust pc back
100 str r2, [r0, #S_PC]
101 add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
102 str r0, [r3] @ this task now owns Concan regs

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213 ldr r1, [r3] @ get current Concan owner
214 teq r1, #0 @ any current owner?
215 beq 1f @ no: quit
216 teq r0, #0 @ any owner?
217 teqne r1, r2 @ or specified one?
218 bne 1f @ no: quit
219
220 @ enable access to CP0 and CP1
79
80 ldr r3, =concan_owner
81 ldr r2, [r0, #S_PC] @ current task pc value
82 ldr r1, [r3] @ get current Concan owner
83 sub r2, r2, #4 @ adjust pc back
84 str r2, [r0, #S_PC]
85 add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
86 str r0, [r3] @ this task now owns Concan regs

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197 ldr r1, [r3] @ get current Concan owner
198 teq r1, #0 @ any current owner?
199 beq 1f @ no: quit
200 teq r0, #0 @ any owner?
201 teqne r1, r2 @ or specified one?
202 bne 1f @ no: quit
203
204 @ enable access to CP0 and CP1
221 XSC(mrc p15, 0, r4, c15, c1, 0)
222 XSC(orr r4, r4, #0x3)
223 XSC(mcr p15, 0, r4, c15, c1, 0)
224 PJ4(mrc p15, 0, r4, c1, c0, 2)
225 PJ4(orr r4, r4, #0xf)
226 PJ4(mcr p15, 0, r4, c1, c0, 2)
205 mrc p15, 0, r4, c15, c1, 0
206 orr r4, r4, #0x3
207 mcr p15, 0, r4, c15, c1, 0
227
228 mov r0, #0 @ nothing to load
229 str r0, [r3] @ no more current owner
230 mrc p15, 0, r2, c2, c0, 0
231 mov r2, r2 @ cpwait
232 bl concan_save
233
234 @ disable access to CP0 and CP1
208
209 mov r0, #0 @ nothing to load
210 str r0, [r3] @ no more current owner
211 mrc p15, 0, r2, c2, c0, 0
212 mov r2, r2 @ cpwait
213 bl concan_save
214
215 @ disable access to CP0 and CP1
235 XSC(bic r4, r4, #0x3)
236 XSC(mcr p15, 0, r4, c15, c1, 0)
237 PJ4(bic r4, r4, #0xf)
238 PJ4(mcr p15, 0, r4, c1, c0, 2)
216 bic r4, r4, #0x3
217 mcr p15, 0, r4, c15, c1, 0
239
240 mrc p15, 0, r2, c2, c0, 0
241 mov r2, r2 @ cpwait
242
2431: msr cpsr_c, ip @ restore interrupt mode
244 ldmfd sp!, {r4, pc}
245
246ENDPROC(iwmmxt_task_disable)

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325 * Concan handling on task switch
326 *
327 * r0 = next thread_info pointer
328 *
329 * Called only from the iwmmxt notifier with task preemption disabled.
330 */
331ENTRY(iwmmxt_task_switch)
332
218
219 mrc p15, 0, r2, c2, c0, 0
220 mov r2, r2 @ cpwait
221
2221: msr cpsr_c, ip @ restore interrupt mode
223 ldmfd sp!, {r4, pc}
224
225ENDPROC(iwmmxt_task_disable)

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304 * Concan handling on task switch
305 *
306 * r0 = next thread_info pointer
307 *
308 * Called only from the iwmmxt notifier with task preemption disabled.
309 */
310ENTRY(iwmmxt_task_switch)
311
333 XSC(mrc p15, 0, r1, c15, c1, 0)
334 PJ4(mrc p15, 0, r1, c1, c0, 2)
312 mrc p15, 0, r1, c15, c1, 0
335 @ CP0 and CP1 accessible?
313 @ CP0 and CP1 accessible?
336 XSC(tst r1, #0x3)
337 PJ4(tst r1, #0xf)
314 tst r1, #0x3
338 bne 1f @ yes: block them for next task
339
340 ldr r2, =concan_owner
341 add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
342 ldr r2, [r2] @ get current Concan owner
343 teq r2, r3 @ next task owns it?
344 retne lr @ no: leave Concan disabled
345
3461: @ flip Concan access
315 bne 1f @ yes: block them for next task
316
317 ldr r2, =concan_owner
318 add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
319 ldr r2, [r2] @ get current Concan owner
320 teq r2, r3 @ next task owns it?
321 retne lr @ no: leave Concan disabled
322
3231: @ flip Concan access
347 XSC(eor r1, r1, #0x3)
348 XSC(mcr p15, 0, r1, c15, c1, 0)
349 PJ4(eor r1, r1, #0xf)
350 PJ4(mcr p15, 0, r1, c1, c0, 2)
324 eor r1, r1, #0x3
325 mcr p15, 0, r1, c15, c1, 0
351
352 mrc p15, 0, r1, c2, c0, 0
353 sub pc, lr, r1, lsr #32 @ cpwait and return
354
355ENDPROC(iwmmxt_task_switch)
356
357/*
358 * Remove Concan ownership of given task

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327 mrc p15, 0, r1, c2, c0, 0
328 sub pc, lr, r1, lsr #32 @ cpwait and return
329
330ENDPROC(iwmmxt_task_switch)
331
332/*
333 * Remove Concan ownership of given task

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