iwmmxt.S (05668381140309088443bf5dc53add4104610fbb) iwmmxt.S (ef6c84454f8567d4968c210d7d194fb711ed3739)
1/*
2 * linux/arch/arm/kernel/iwmmxt.S
3 *
4 * XScale iWMMXt (Concan) context switching and handling
5 *
6 * Initial code:
7 * Copyright (c) 2003, Intel Corporation
8 *

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14 * published by the Free Software Foundation.
15 */
16
17#include <linux/linkage.h>
18#include <asm/ptrace.h>
19#include <asm/thread_info.h>
20#include <asm/asm-offsets.h>
21
1/*
2 * linux/arch/arm/kernel/iwmmxt.S
3 *
4 * XScale iWMMXt (Concan) context switching and handling
5 *
6 * Initial code:
7 * Copyright (c) 2003, Intel Corporation
8 *

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14 * published by the Free Software Foundation.
15 */
16
17#include <linux/linkage.h>
18#include <asm/ptrace.h>
19#include <asm/thread_info.h>
20#include <asm/asm-offsets.h>
21
22#if defined(CONFIG_CPU_PJ4)
23#define PJ4(code...) code
24#define XSC(code...)
25#else
26#define PJ4(code...)
27#define XSC(code...) code
28#endif
29
22#define MMX_WR0 (0x00)
23#define MMX_WR1 (0x08)
24#define MMX_WR2 (0x10)
25#define MMX_WR3 (0x18)
26#define MMX_WR4 (0x20)
27#define MMX_WR5 (0x28)
28#define MMX_WR6 (0x30)
29#define MMX_WR7 (0x38)

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53 * r9 = ret_from_exception
54 * lr = undefined instr exit
55 *
56 * called from prefetch exception handler with interrupts disabled
57 */
58
59ENTRY(iwmmxt_task_enable)
60
30#define MMX_WR0 (0x00)
31#define MMX_WR1 (0x08)
32#define MMX_WR2 (0x10)
33#define MMX_WR3 (0x18)
34#define MMX_WR4 (0x20)
35#define MMX_WR5 (0x28)
36#define MMX_WR6 (0x30)
37#define MMX_WR7 (0x38)

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61 * r9 = ret_from_exception
62 * lr = undefined instr exit
63 *
64 * called from prefetch exception handler with interrupts disabled
65 */
66
67ENTRY(iwmmxt_task_enable)
68
61 mrc p15, 0, r2, c15, c1, 0
62 tst r2, #0x3 @ CP0 and CP1 accessible?
69 XSC(mrc p15, 0, r2, c15, c1, 0)
70 PJ4(mrc p15, 0, r2, c1, c0, 2)
71 @ CP0 and CP1 accessible?
72 XSC(tst r2, #0x3)
73 PJ4(tst r2, #0xf)
63 movne pc, lr @ if so no business here
74 movne pc, lr @ if so no business here
64 orr r2, r2, #0x3 @ enable access to CP0 and CP1
65 mcr p15, 0, r2, c15, c1, 0
75 @ enable access to CP0 and CP1
76 XSC(orr r2, r2, #0x3)
77 XSC(mcr p15, 0, r2, c15, c1, 0)
78 PJ4(orr r2, r2, #0xf)
79 PJ4(mcr p15, 0, r2, c1, c0, 2)
66
67 ldr r3, =concan_owner
68 add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
69 ldr r2, [sp, #60] @ current task pc value
70 ldr r1, [r3] @ get current Concan owner
71 str r0, [r3] @ this task now owns Concan regs
72 sub r2, r2, #4 @ adjust pc back
73 str r2, [sp, #60]

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174 add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
175 ldr r1, [r3] @ get current Concan owner
176 teq r1, #0 @ any current owner?
177 beq 1f @ no: quit
178 teq r0, #0 @ any owner?
179 teqne r1, r2 @ or specified one?
180 bne 1f @ no: quit
181
80
81 ldr r3, =concan_owner
82 add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
83 ldr r2, [sp, #60] @ current task pc value
84 ldr r1, [r3] @ get current Concan owner
85 str r0, [r3] @ this task now owns Concan regs
86 sub r2, r2, #4 @ adjust pc back
87 str r2, [sp, #60]

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188 add r2, r0, #TI_IWMMXT_STATE @ get task Concan save area
189 ldr r1, [r3] @ get current Concan owner
190 teq r1, #0 @ any current owner?
191 beq 1f @ no: quit
192 teq r0, #0 @ any owner?
193 teqne r1, r2 @ or specified one?
194 bne 1f @ no: quit
195
182 mrc p15, 0, r4, c15, c1, 0
183 orr r4, r4, #0x3 @ enable access to CP0 and CP1
184 mcr p15, 0, r4, c15, c1, 0
196 @ enable access to CP0 and CP1
197 XSC(mrc p15, 0, r4, c15, c1, 0)
198 XSC(orr r4, r4, #0xf)
199 XSC(mcr p15, 0, r4, c15, c1, 0)
200 PJ4(mrc p15, 0, r4, c1, c0, 2)
201 PJ4(orr r4, r4, #0x3)
202 PJ4(mcr p15, 0, r4, c1, c0, 2)
203
185 mov r0, #0 @ nothing to load
186 str r0, [r3] @ no more current owner
187 mrc p15, 0, r2, c2, c0, 0
188 mov r2, r2 @ cpwait
189 bl concan_save
190
204 mov r0, #0 @ nothing to load
205 str r0, [r3] @ no more current owner
206 mrc p15, 0, r2, c2, c0, 0
207 mov r2, r2 @ cpwait
208 bl concan_save
209
191 bic r4, r4, #0x3 @ disable access to CP0 and CP1
192 mcr p15, 0, r4, c15, c1, 0
210 @ disable access to CP0 and CP1
211 XSC(bic r4, r4, #0x3)
212 XSC(mcr p15, 0, r4, c15, c1, 0)
213 PJ4(bic r4, r4, #0xf)
214 PJ4(mcr p15, 0, r4, c1, c0, 2)
215
193 mrc p15, 0, r2, c2, c0, 0
194 mov r2, r2 @ cpwait
195
1961: msr cpsr_c, ip @ restore interrupt mode
197 ldmfd sp!, {r4, pc}
198
199/*
200 * Copy Concan state to given memory address

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272 * Concan handling on task switch
273 *
274 * r0 = next thread_info pointer
275 *
276 * Called only from the iwmmxt notifier with task preemption disabled.
277 */
278ENTRY(iwmmxt_task_switch)
279
216 mrc p15, 0, r2, c2, c0, 0
217 mov r2, r2 @ cpwait
218
2191: msr cpsr_c, ip @ restore interrupt mode
220 ldmfd sp!, {r4, pc}
221
222/*
223 * Copy Concan state to given memory address

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295 * Concan handling on task switch
296 *
297 * r0 = next thread_info pointer
298 *
299 * Called only from the iwmmxt notifier with task preemption disabled.
300 */
301ENTRY(iwmmxt_task_switch)
302
280 mrc p15, 0, r1, c15, c1, 0
281 tst r1, #0x3 @ CP0 and CP1 accessible?
303 XSC(mrc p15, 0, r1, c15, c1, 0)
304 PJ4(mrc p15, 0, r1, c1, c0, 2)
305 @ CP0 and CP1 accessible?
306 XSC(tst r1, #0x3)
307 PJ4(tst r1, #0xf)
282 bne 1f @ yes: block them for next task
283
284 ldr r2, =concan_owner
285 add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
286 ldr r2, [r2] @ get current Concan owner
287 teq r2, r3 @ next task owns it?
288 movne pc, lr @ no: leave Concan disabled
289
308 bne 1f @ yes: block them for next task
309
310 ldr r2, =concan_owner
311 add r3, r0, #TI_IWMMXT_STATE @ get next task Concan save area
312 ldr r2, [r2] @ get current Concan owner
313 teq r2, r3 @ next task owns it?
314 movne pc, lr @ no: leave Concan disabled
315
2901: eor r1, r1, #3 @ flip Concan access
291 mcr p15, 0, r1, c15, c1, 0
3161: @ flip Conan access
317 XSC(eor r1, r1, #0x3)
318 XSC(mcr p15, 0, r1, c15, c1, 0)
319 PJ4(eor r1, r1, #0xf)
320 PJ4(mcr p15, 0, r1, c1, c0, 2)
292
293 mrc p15, 0, r1, c2, c0, 0
294 sub pc, lr, r1, lsr #32 @ cpwait and return
295
296/*
297 * Remove Concan ownership of given task
298 *
299 * r0 = struct thread_info pointer

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322 mrc p15, 0, r1, c2, c0, 0
323 sub pc, lr, r1, lsr #32 @ cpwait and return
324
325/*
326 * Remove Concan ownership of given task
327 *
328 * r0 = struct thread_info pointer

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