head-nommu.S (05668381140309088443bf5dc53add4104610fbb) head-nommu.S (f12d0d7c7786af39435ef6ae9defe47fb58f6091)
1/*
2 * linux/arch/arm/kernel/head-nommu.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (C) 2003-2006 Hyok S. Choi
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Common kernel startup code (non-paged MM)
1/*
2 * linux/arch/arm/kernel/head-nommu.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (C) 2003-2006 Hyok S. Choi
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Common kernel startup code (non-paged MM)
12 * for 32-bit CPUs which has a process ID register(CP15).
13 *
14 */
15#include <linux/linkage.h>
16#include <linux/init.h>
17
18#include <asm/assembler.h>
19#include <asm/mach-types.h>
20#include <asm/procinfo.h>

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35 * numbers for r1.
36 *
37 */
38 __INIT
39 .type stext, %function
40ENTRY(stext)
41 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
42 @ and irqs disabled
12 *
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16
17#include <asm/assembler.h>
18#include <asm/mach-types.h>
19#include <asm/procinfo.h>

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34 * numbers for r1.
35 *
36 */
37 __INIT
38 .type stext, %function
39ENTRY(stext)
40 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
41 @ and irqs disabled
42#ifndef CONFIG_CPU_CP15
43 ldr r9, =CONFIG_PROCESSOR_ID
44#else
43 mrc p15, 0, r9, c0, c0 @ get processor id
45 mrc p15, 0, r9, c0, c0 @ get processor id
46#endif
44 bl __lookup_processor_type @ r5=procinfo r9=cpuid
45 movs r10, r5 @ invalid processor (r5=0)?
46 beq __error_p @ yes, error 'p'
47 bl __lookup_machine_type @ r5=machinfo
48 movs r8, r5 @ invalid machine (r5=0)?
49 beq __error_a @ yes, error 'a'
50
51 ldr r13, __switch_data @ address to jump to after
52 @ the initialization is done
53 adr lr, __after_proc_init @ return (PIC) address
54 add pc, r10, #PROCINFO_INITFUNC
55
56/*
57 * Set the Control Register and Read the process ID.
58 */
59 .type __after_proc_init, %function
60__after_proc_init:
47 bl __lookup_processor_type @ r5=procinfo r9=cpuid
48 movs r10, r5 @ invalid processor (r5=0)?
49 beq __error_p @ yes, error 'p'
50 bl __lookup_machine_type @ r5=machinfo
51 movs r8, r5 @ invalid machine (r5=0)?
52 beq __error_a @ yes, error 'a'
53
54 ldr r13, __switch_data @ address to jump to after
55 @ the initialization is done
56 adr lr, __after_proc_init @ return (PIC) address
57 add pc, r10, #PROCINFO_INITFUNC
58
59/*
60 * Set the Control Register and Read the process ID.
61 */
62 .type __after_proc_init, %function
63__after_proc_init:
64#ifdef CONFIG_CPU_CP15
61 mrc p15, 0, r0, c1, c0, 0 @ read control reg
62#ifdef CONFIG_ALIGNMENT_TRAP
63 orr r0, r0, #CR_A
64#else
65 bic r0, r0, #CR_A
66#endif
67#ifdef CONFIG_CPU_DCACHE_DISABLE
68 bic r0, r0, #CR_C
69#endif
70#ifdef CONFIG_CPU_BPREDICT_DISABLE
71 bic r0, r0, #CR_Z
72#endif
73#ifdef CONFIG_CPU_ICACHE_DISABLE
74 bic r0, r0, #CR_I
75#endif
76 mcr p15, 0, r0, c1, c0, 0 @ write control reg
65 mrc p15, 0, r0, c1, c0, 0 @ read control reg
66#ifdef CONFIG_ALIGNMENT_TRAP
67 orr r0, r0, #CR_A
68#else
69 bic r0, r0, #CR_A
70#endif
71#ifdef CONFIG_CPU_DCACHE_DISABLE
72 bic r0, r0, #CR_C
73#endif
74#ifdef CONFIG_CPU_BPREDICT_DISABLE
75 bic r0, r0, #CR_Z
76#endif
77#ifdef CONFIG_CPU_ICACHE_DISABLE
78 bic r0, r0, #CR_I
79#endif
80 mcr p15, 0, r0, c1, c0, 0 @ write control reg
81#endif /* CONFIG_CPU_CP15 */
77
78 mov pc, r13 @ clear the BSS and jump
79 @ to start_kernel
80 .ltorg
81
82#include "head-common.S"
82
83 mov pc, r13 @ clear the BSS and jump
84 @ to start_kernel
85 .ltorg
86
87#include "head-common.S"