| head-nommu.S (0337966d121ebebf73a1c346123e8112796e684e) | head-nommu.S (a0995c0805b63c930b99970f2c9d5e4f167ca65b) |
|---|---|
| 1/* 2 * linux/arch/arm/kernel/head-nommu.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (C) 2003-2006 Hyok S. Choi 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Common kernel startup code (non-paged MM) 12 * 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> | 1/* 2 * linux/arch/arm/kernel/head-nommu.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (C) 2003-2006 Hyok S. Choi 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Common kernel startup code (non-paged MM) 12 * 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> |
| 16#include <linux/errno.h> |
|
| 16 17#include <asm/assembler.h> 18#include <asm/ptrace.h> 19#include <asm/asm-offsets.h> 20#include <asm/memory.h> 21#include <asm/cp15.h> 22#include <asm/thread_info.h> 23#include <asm/v7m.h> --- 81 unchanged lines hidden (view full) --- 105 bl __lookup_processor_type @ r5=procinfo r9=cpuid 106 movs r10, r5 @ invalid processor? 107 beq __error_p @ yes, error 'p' 108 109 ldr r7, __secondary_data 110 111#ifdef CONFIG_ARM_MPU 112 /* Use MPU region info supplied by __cpu_up */ | 17 18#include <asm/assembler.h> 19#include <asm/ptrace.h> 20#include <asm/asm-offsets.h> 21#include <asm/memory.h> 22#include <asm/cp15.h> 23#include <asm/thread_info.h> 24#include <asm/v7m.h> --- 81 unchanged lines hidden (view full) --- 106 bl __lookup_processor_type @ r5=procinfo r9=cpuid 107 movs r10, r5 @ invalid processor? 108 beq __error_p @ yes, error 'p' 109 110 ldr r7, __secondary_data 111 112#ifdef CONFIG_ARM_MPU 113 /* Use MPU region info supplied by __cpu_up */ |
| 113 ldr r6, [r7] @ get secondary_data.mpu_szr 114 bl __setup_mpu @ Initialize the MPU | 114 ldr r6, [r7] @ get secondary_data.mpu_rgn_info 115 bl __secondary_setup_mpu @ Initialize the MPU |
| 115#endif 116 117 badr lr, 1f @ return (PIC) address 118 ldr r12, [r10, #PROCINFO_INITFUNC] 119 add r12, r12, r10 120 ret r12 1211: bl __after_proc_init 122 ldr sp, [r7, #12] @ set up the stack pointer --- 76 unchanged lines hidden (view full) --- 199*/ 200 201ENTRY(__setup_mpu) 202 203 /* Probe for v7 PMSA compliance */ 204 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 205 and r0, r0, #(MMFR0_PMSA) @ PMSA field 206 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 | 116#endif 117 118 badr lr, 1f @ return (PIC) address 119 ldr r12, [r10, #PROCINFO_INITFUNC] 120 add r12, r12, r10 121 ret r12 1221: bl __after_proc_init 123 ldr sp, [r7, #12] @ set up the stack pointer --- 76 unchanged lines hidden (view full) --- 200*/ 201 202ENTRY(__setup_mpu) 203 204 /* Probe for v7 PMSA compliance */ 205 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 206 and r0, r0, #(MMFR0_PMSA) @ PMSA field 207 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 |
| 207 bne __error_p @ Fail: ARM_MPU on NOT v7 PMSA | 208 bxne lr |
| 208 209 /* Determine whether the D/I-side memory map is unified. We set the 210 * flags here and continue to use them for the rest of this function */ 211 mrc p15, 0, r0, c0, c0, 4 @ MPUIR 212 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU | 209 210 /* Determine whether the D/I-side memory map is unified. We set the 211 * flags here and continue to use them for the rest of this function */ 212 mrc p15, 0, r0, c0, c0, 4 @ MPUIR 213 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU |
| 213 beq __error_p @ Fail: ARM_MPU and no MPU | 214 bxeq lr |
| 214 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 215 216 /* Setup second region first to free up r6 */ 217 set_region_nr r0, #MPU_RAM_REGION 218 isb 219 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */ 220 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET 221 ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL) --- 11 unchanged lines hidden (view full) --- 233 ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA) 234 mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled 235 236 setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled 237 beq 2f @ Memory-map not unified 238 setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled 2392: isb 240 | 215 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 216 217 /* Setup second region first to free up r6 */ 218 set_region_nr r0, #MPU_RAM_REGION 219 isb 220 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */ 221 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET 222 ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL) --- 11 unchanged lines hidden (view full) --- 234 ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA) 235 mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled 236 237 setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled 238 beq 2f @ Memory-map not unified 239 setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled 2402: isb 241 |
| 241 /* Vectors region */ 242 set_region_nr r0, #MPU_VECTORS_REGION | 242 /* Enable the MPU */ 243 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR 244 bic r0, r0, #CR_BR @ Disable the 'default mem-map' 245 orr r0, r0, #CR_M @ Set SCTRL.M (MPU on) 246 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU |
| 243 isb | 247 isb |
| 244 /* Shared, inaccessible to PL0, rw PL1 */ 245 mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE 246 ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL) 247 /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */ 248 mov r6, #(((2 * PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN) | |
| 249 | 248 |
| 250 setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled 251 beq 3f @ Memory-map not unified 252 setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled 2533: isb | 249 ret lr 250ENDPROC(__setup_mpu) |
| 254 | 251 |
| 252#ifdef CONFIG_SMP 253/* 254 * r6: pointer at mpu_rgn_info 255 */ 256 257ENTRY(__secondary_setup_mpu) 258 /* Probe for v7 PMSA compliance */ 259 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 260 and r0, r0, #(MMFR0_PMSA) @ PMSA field 261 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 262 bne __error_p 263 264 /* Determine whether the D/I-side memory map is unified. We set the 265 * flags here and continue to use them for the rest of this function */ 266 mrc p15, 0, r0, c0, c0, 4 @ MPUIR 267 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU 268 beq __error_p 269 270 ldr r4, [r6, #MPU_RNG_INFO_USED] 271 mov r5, #MPU_RNG_SIZE 272 add r3, r6, #MPU_RNG_INFO_RNGS 273 mla r3, r4, r5, r3 274 2751: 276 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 277 sub r3, r3, #MPU_RNG_SIZE 278 sub r4, r4, #1 279 280 set_region_nr r0, r4 281 isb 282 283 ldr r0, [r3, #MPU_RGN_DRBAR] 284 ldr r6, [r3, #MPU_RGN_DRSR] 285 ldr r5, [r3, #MPU_RGN_DRACR] 286 287 setup_region r0, r5, r6, MPU_DATA_SIDE 288 beq 2f 289 setup_region r0, r5, r6, MPU_INSTR_SIDE 2902: isb 291 292 mrc p15, 0, r0, c0, c0, 4 @ Reevaluate the MPUIR 293 cmp r4, #0 294 bgt 1b 295 |
|
| 255 /* Enable the MPU */ 256 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR | 296 /* Enable the MPU */ 297 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR |
| 257 bic r0, r0, #CR_BR @ Disable the 'default mem-map' | 298 bic r0, r0, #CR_BR @ Disable the 'default mem-map' |
| 258 orr r0, r0, #CR_M @ Set SCTRL.M (MPU on) 259 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU 260 isb | 299 orr r0, r0, #CR_M @ Set SCTRL.M (MPU on) 300 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU 301 isb |
| 302 |
|
| 261 ret lr | 303 ret lr |
| 262ENDPROC(__setup_mpu) 263#endif | 304ENDPROC(__secondary_setup_mpu) 305 306#endif /* CONFIG_SMP */ 307#endif /* CONFIG_ARM_MPU */ |
| 264#include "head-common.S" | 308#include "head-common.S" |