pgtable.h (c825dda905bac330c2da7fabdf5c0ac28758b3cd) pgtable.h (17f57211969bddca2e922299a2530b1c65ccabfa)
1/*
2 * arch/arm/include/asm/pgtable.h
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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19#include "pgtable-nommu.h"
20
21#else
22
23#include <asm/memory.h>
24#include <mach/vmalloc.h>
25#include <asm/pgtable-hwdef.h>
26
1/*
2 * arch/arm/include/asm/pgtable.h
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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19#include "pgtable-nommu.h"
20
21#else
22
23#include <asm/memory.h>
24#include <mach/vmalloc.h>
25#include <asm/pgtable-hwdef.h>
26
27#include <asm/pgtable-2level.h>
28
27/*
28 * Just any arbitrary offset to the start of the vmalloc VM area: the
29 * current 8MB value just means that there will be a 8MB "hole" after the
30 * physical memory until the kernel virtual memory starts. That means that
31 * any out-of-bounds memory accesses will hopefully be caught.
32 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
33 * area for the same reason. ;)
34 *
35 * Note that platforms may override VMALLOC_START, but they must provide
36 * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
37 * which may not overlap IO space.
38 */
39#ifndef VMALLOC_START
40#define VMALLOC_OFFSET (8*1024*1024)
41#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
42#endif
43
29/*
30 * Just any arbitrary offset to the start of the vmalloc VM area: the
31 * current 8MB value just means that there will be a 8MB "hole" after the
32 * physical memory until the kernel virtual memory starts. That means that
33 * any out-of-bounds memory accesses will hopefully be caught.
34 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
35 * area for the same reason. ;)
36 *
37 * Note that platforms may override VMALLOC_START, but they must provide
38 * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
39 * which may not overlap IO space.
40 */
41#ifndef VMALLOC_START
42#define VMALLOC_OFFSET (8*1024*1024)
43#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
44#endif
45
44/*
45 * Hardware-wise, we have a two level page table structure, where the first
46 * level has 4096 entries, and the second level has 256 entries. Each entry
47 * is one 32-bit word. Most of the bits in the second level entry are used
48 * by hardware, and there aren't any "accessed" and "dirty" bits.
49 *
50 * Linux on the other hand has a three level page table structure, which can
51 * be wrapped to fit a two level page table structure easily - using the PGD
52 * and PTE only. However, Linux also expects one "PTE" table per page, and
53 * at least a "dirty" bit.
54 *
55 * Therefore, we tweak the implementation slightly - we tell Linux that we
56 * have 2048 entries in the first level, each of which is 8 bytes (iow, two
57 * hardware pointers to the second level.) The second level contains two
58 * hardware PTE tables arranged contiguously, preceded by Linux versions
59 * which contain the state information Linux needs. We, therefore, end up
60 * with 512 entries in the "PTE" level.
61 *
62 * This leads to the page tables having the following layout:
63 *
64 * pgd pte
65 * | |
66 * +--------+
67 * | | +------------+ +0
68 * +- - - - + | Linux pt 0 |
69 * | | +------------+ +1024
70 * +--------+ +0 | Linux pt 1 |
71 * | |-----> +------------+ +2048
72 * +- - - - + +4 | h/w pt 0 |
73 * | |-----> +------------+ +3072
74 * +--------+ +8 | h/w pt 1 |
75 * | | +------------+ +4096
76 *
77 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
78 * PTE_xxx for definitions of bits appearing in the "h/w pt".
79 *
80 * PMD_xxx definitions refer to bits in the first level page table.
81 *
82 * The "dirty" bit is emulated by only granting hardware write permission
83 * iff the page is marked "writable" and "dirty" in the Linux PTE. This
84 * means that a write to a clean page will cause a permission fault, and
85 * the Linux MM layer will mark the page dirty via handle_pte_fault().
86 * For the hardware to notice the permission change, the TLB entry must
87 * be flushed, and ptep_set_access_flags() does that for us.
88 *
89 * The "accessed" or "young" bit is emulated by a similar method; we only
90 * allow accesses to the page if the "young" bit is set. Accesses to the
91 * page will cause a fault, and handle_pte_fault() will set the young bit
92 * for us as long as the page is marked present in the corresponding Linux
93 * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is
94 * up to date.
95 *
96 * However, when the "young" bit is cleared, we deny access to the page
97 * by clearing the hardware PTE. Currently Linux does not flush the TLB
98 * for us in this case, which means the TLB will retain the transation
99 * until either the TLB entry is evicted under pressure, or a context
100 * switch which changes the user space mapping occurs.
101 */
102#define PTRS_PER_PTE 512
103#define PTRS_PER_PMD 1
104#define PTRS_PER_PGD 2048
105
106#define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
107#define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t))
108#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32))
109
110/*
111 * PMD_SHIFT determines the size of the area a second-level page table can map
112 * PGDIR_SHIFT determines what a third-level page table entry can map
113 */
114#define PMD_SHIFT 21
115#define PGDIR_SHIFT 21
116
117#define LIBRARY_TEXT_START 0x0c000000
118
119#ifndef __ASSEMBLY__
120extern void __pte_error(const char *file, int line, pte_t);
121extern void __pmd_error(const char *file, int line, pmd_t);
122extern void __pgd_error(const char *file, int line, pgd_t);
123
124#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte)
125#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd)
126#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd)
46#define LIBRARY_TEXT_START 0x0c000000
47
48#ifndef __ASSEMBLY__
49extern void __pte_error(const char *file, int line, pte_t);
50extern void __pmd_error(const char *file, int line, pmd_t);
51extern void __pgd_error(const char *file, int line, pgd_t);
52
53#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte)
54#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd)
55#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd)
127#endif /* !__ASSEMBLY__ */
128
56
129#define PMD_SIZE (1UL << PMD_SHIFT)
130#define PMD_MASK (~(PMD_SIZE-1))
131#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
132#define PGDIR_MASK (~(PGDIR_SIZE-1))
133
134/*
135 * This is the lowest virtual address we can permit any user space
136 * mapping to be mapped at. This is particularly important for
137 * non-high vector CPUs.
138 */
139#define FIRST_USER_ADDRESS PAGE_SIZE
140
57/*
58 * This is the lowest virtual address we can permit any user space
59 * mapping to be mapped at. This is particularly important for
60 * non-high vector CPUs.
61 */
62#define FIRST_USER_ADDRESS PAGE_SIZE
63
141#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
142
143/*
64/*
144 * section address mask and size definitions.
145 */
146#define SECTION_SHIFT 20
147#define SECTION_SIZE (1UL << SECTION_SHIFT)
148#define SECTION_MASK (~(SECTION_SIZE-1))
149
150/*
151 * ARMv6 supersection address mask and size definitions.
152 */
153#define SUPERSECTION_SHIFT 24
154#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
155#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
156
157/*
158 * "Linux" PTE definitions.
159 *
160 * We keep two sets of PTEs - the hardware and the linux version.
161 * This allows greater flexibility in the way we map the Linux bits
162 * onto the hardware tables, and allows us to have YOUNG and DIRTY
163 * bits.
164 *
165 * The PTE table pointer refers to the hardware entries; the "Linux"
166 * entries are stored 1024 bytes below.
167 */
168#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
169#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
170#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
171#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6)
172#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7)
173#define L_PTE_USER (_AT(pteval_t, 1) << 8)
174#define L_PTE_XN (_AT(pteval_t, 1) << 9)
175#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */
176
177/*
178 * These are the memory types, defined to be compatible with
179 * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
180 */
181#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */
182#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
183#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
184#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
185#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
186#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
187#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
188#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
189#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
190#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
191#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
192
193#ifndef __ASSEMBLY__
194
195/*
196 * The pgprot_* and protection_map entries will be fixed up in runtime
197 * to include the cachable and bufferable bits based on memory policy,
198 * as well as any architecture dependent bits like global/ASID and SMP
199 * shared mapping bits.
200 */
201#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG
202
203extern pgprot_t pgprot_user;

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227 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
228
229#define pgprot_noncached(prot) \
230 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
231
232#define pgprot_writecombine(prot) \
233 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
234
65 * The pgprot_* and protection_map entries will be fixed up in runtime
66 * to include the cachable and bufferable bits based on memory policy,
67 * as well as any architecture dependent bits like global/ASID and SMP
68 * shared mapping bits.
69 */
70#define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG
71
72extern pgprot_t pgprot_user;

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96 __pgprot((pgprot_val(prot) & ~(mask)) | (bits))
97
98#define pgprot_noncached(prot) \
99 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
100
101#define pgprot_writecombine(prot) \
102 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
103
235#define pgprot_stronglyordered(prot) \
236 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
237
238#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
239#define pgprot_dmacoherent(prot) \
240 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
241#define __HAVE_PHYS_MEM_ACCESS_PROT
242struct file;
243extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
244 unsigned long size, pgprot_t vma_prot);
245#else

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105#define pgprot_dmacoherent(prot) \
106 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
107#define __HAVE_PHYS_MEM_ACCESS_PROT
108struct file;
109extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
110 unsigned long size, pgprot_t vma_prot);
111#else

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