exynos4210.dtsi (34069d12e239ae8f36dd96c378e4622fb1c42a76) exynos4210.dtsi (ef399736c3ba77fb82d778b1b7285baa65a7e079)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org

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386 temperature = <100000>; /* millicelsius */
387};
388
389&cpu_alert2 {
390 temperature = <110000>; /* millicelsius */
391};
392
393&cpu_thermal {
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Samsung's Exynos4210 SoC device tree source
4 *
5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2010-2011 Linaro Ltd.
8 * www.linaro.org

--- 377 unchanged lines hidden (view full) ---

386 temperature = <100000>; /* millicelsius */
387};
388
389&cpu_alert2 {
390 temperature = <110000>; /* millicelsius */
391};
392
393&cpu_thermal {
394 polling-delay-passive = <0>;
395 polling-delay = <0>;
394 /*
395 * Exynos 4210 supports thermal interrupts, but only for the rising
396 * threshold. This means that polling is not needed for preventing
397 * overheating, but only for decreasing cooling when possible. Hence we
398 * poll with a high delay. Ideally, we would disable polling for the
399 * first trip point, but this isn't really possible without outrageous
400 * hacks.
401 */
402 polling-delay-passive = <5000>;
403 polling-delay = <5000>;
396};
397
398&gic {
399 cpu-offset = <0x8000>;
400};
401
402&camera {
403 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,

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405
406&gic {
407 cpu-offset = <0x8000>;
408};
409
410&camera {
411 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,

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