rv1126.dtsi (de80193308f43d3ae52cd3561e8ba77cd1437311) rv1126.dtsi (28b2ae4ab0d139b5e1d64e4cbb245f2661a83036)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rv1126-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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242 dma-names = "tx", "rx";
243 pinctrl-names = "default";
244 pinctrl-0 = <&uart1m0_xfer>;
245 reg-shift = <2>;
246 reg-io-width = <4>;
247 status = "disabled";
248 };
249
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rv1126-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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242 dma-names = "tx", "rx";
243 pinctrl-names = "default";
244 pinctrl-0 = <&uart1m0_xfer>;
245 reg-shift = <2>;
246 reg-io-width = <4>;
247 status = "disabled";
248 };
249
250 pwm2: pwm@ff430020 {
251 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
252 reg = <0xff430020 0x10>;
253 clock-names = "pwm", "pclk";
254 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pwm2m0_pins>;
257 #pwm-cells = <3>;
258 status = "disabled";
259 };
260
250 pmucru: clock-controller@ff480000 {
251 compatible = "rockchip,rv1126-pmucru";
252 reg = <0xff480000 0x1000>;
253 rockchip,grf = <&grf>;
254 #clock-cells = <1>;
255 #reset-cells = <1>;
256 };
257

--- 323 unchanged lines hidden --- 		261 pmucru: clock-controller@ff480000 {
262 compatible = "rockchip,rv1126-pmucru";
263 reg = <0xff480000 0x1000>;
264 rockchip,grf = <&grf>;
265 #clock-cells = <1>;
266 #reset-cells = <1>;
267 };
268

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