rv1126.dtsi (c3ae1484e112343dc5d9fc33ca0cc83c994939c1) rv1126.dtsi (4fafaed5afcc3a58e982629dbc0471ba9ba8678f)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rv1126-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 111 unchanged lines hidden (view full) ---

120 reg = <0xfe860200 0x20>;
121 };
122
123 qos_sdio: qos@fe86c000 {
124 compatible = "rockchip,rv1126-qos", "syscon";
125 reg = <0xfe86c000 0x20>;
126 };
127
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rv1126-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 111 unchanged lines hidden (view full) ---

120 reg = <0xfe860200 0x20>;
121 };
122
123 qos_sdio: qos@fe86c000 {
124 compatible = "rockchip,rv1126-qos", "syscon";
125 reg = <0xfe86c000 0x20>;
126 };
127
128 qos_iep: qos@fe8a0000 {
129 compatible = "rockchip,rv1126-qos", "syscon";
130 reg = <0xfe8a0000 0x20>;
131 };
132
133 qos_rga_rd: qos@fe8a0080 {
134 compatible = "rockchip,rv1126-qos", "syscon";
135 reg = <0xfe8a0080 0x20>;
136 };
137
138 qos_rga_wr: qos@fe8a0100 {
139 compatible = "rockchip,rv1126-qos", "syscon";
140 reg = <0xfe8a0100 0x20>;
141 };
142
143 qos_vop: qos@fe8a0180 {
144 compatible = "rockchip,rv1126-qos", "syscon";
145 reg = <0xfe8a0180 0x20>;
146 };
147
128 gic: interrupt-controller@feff0000 {
129 compatible = "arm,gic-400";
130 interrupt-controller;
131 #interrupt-cells = <3>;
132 #address-cells = <0>;
133
134 reg = <0xfeff1000 0x1000>,
135 <0xfeff2000 0x2000>,

--- 29 unchanged lines hidden (view full) ---

165
166 power-domain@RV1126_PD_SDIO {
167 reg = <RV1126_PD_SDIO>;
168 clocks = <&cru HCLK_SDIO>,
169 <&cru CLK_SDIO>;
170 pm_qos = <&qos_sdio>;
171 #power-domain-cells = <0>;
172 };
148 gic: interrupt-controller@feff0000 {
149 compatible = "arm,gic-400";
150 interrupt-controller;
151 #interrupt-cells = <3>;
152 #address-cells = <0>;
153
154 reg = <0xfeff1000 0x1000>,
155 <0xfeff2000 0x2000>,

--- 29 unchanged lines hidden (view full) ---

185
186 power-domain@RV1126_PD_SDIO {
187 reg = <RV1126_PD_SDIO>;
188 clocks = <&cru HCLK_SDIO>,
189 <&cru CLK_SDIO>;
190 pm_qos = <&qos_sdio>;
191 #power-domain-cells = <0>;
192 };
193
194 power-domain@RV1126_PD_VO {
195 reg = <RV1126_PD_VO>;
196 clocks = <&cru ACLK_RGA>,
197 <&cru HCLK_RGA>,
198 <&cru CLK_RGA_CORE>,
199 <&cru ACLK_VOP>,
200 <&cru HCLK_VOP>,
201 <&cru DCLK_VOP>,
202 <&cru PCLK_DSIHOST>,
203 <&cru ACLK_IEP>,
204 <&cru HCLK_IEP>,
205 <&cru CLK_IEP_CORE>;
206 pm_qos = <&qos_rga_rd>,
207 <&qos_rga_wr>,
208 <&qos_vop>,
209 <&qos_iep>;
210 #power-domain-cells = <0>;
211 };
173 };
174 };
175
176 i2c0: i2c@ff3f0000 {
177 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
178 reg = <0xff3f0000 0x1000>;
179 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
180 rockchip,grf = <&pmugrf>;

--- 319 unchanged lines hidden --- 		212 };
213 };
214
215 i2c0: i2c@ff3f0000 {
216 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
217 reg = <0xff3f0000 0x1000>;
218 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
219 rockchip,grf = <&pmugrf>;

--- 319 unchanged lines hidden ---