rv1126.dtsi (2612e3bbc0386368a850140a6c9b990cd496a5ec) rv1126.dtsi (c3ae1484e112343dc5d9fc33ca0cc83c994939c1)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rv1126-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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414 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
415 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
416 fifo-depth = <0x100>;
417 max-frequency = <200000000>;
418 power-domains = <&power RV1126_PD_SDIO>;
419 status = "disabled";
420 };
421
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rv1126-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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414 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
415 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
416 fifo-depth = <0x100>;
417 max-frequency = <200000000>;
418 power-domains = <&power RV1126_PD_SDIO>;
419 status = "disabled";
420 };
421
422 sfc: spi@ffc90000 {
423 compatible = "rockchip,sfc";
424 reg = <0xffc90000 0x4000>;
425 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
426 assigned-clocks = <&cru SCLK_SFC>;
427 assigned-clock-rates = <80000000>;
428 clock-names = "clk_sfc", "hclk_sfc";
429 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
430 power-domains = <&power RV1126_PD_NVM>;
431 status = "disabled";
432 };
433
422 pinctrl: pinctrl {
423 compatible = "rockchip,rv1126-pinctrl";
424 rockchip,grf = <&grf>;
425 rockchip,pmu = <&pmugrf>;
426 #address-cells = <1>;
427 #size-cells = <1>;
428 ranges;
429

--- 58 unchanged lines hidden --- 		434 pinctrl: pinctrl {
435 compatible = "rockchip,rv1126-pinctrl";
436 rockchip,grf = <&grf>;
437 rockchip,pmu = <&pmugrf>;
438 #address-cells = <1>;
439 #size-cells = <1>;
440 ranges;
441

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