rv1126.dtsi (212cda94739b1644e38ef4f588bb580c12feb9a7) rv1126.dtsi (898eb75f443eaf6cb46facf52fc337fbdbdca079)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rv1126-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 255 unchanged lines hidden (view full) ---

264 dma-names = "tx", "rx";
265 pinctrl-names = "default";
266 pinctrl-0 = <&uart1m0_xfer>;
267 reg-shift = <2>;
268 reg-io-width = <4>;
269 status = "disabled";
270 };
271
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rockchip,rv1126-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 255 unchanged lines hidden (view full) ---

264 dma-names = "tx", "rx";
265 pinctrl-names = "default";
266 pinctrl-0 = <&uart1m0_xfer>;
267 reg-shift = <2>;
268 reg-io-width = <4>;
269 status = "disabled";
270 };
271
272 pwm0: pwm@ff430000 {
273 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
274 reg = <0xff430000 0x10>;
275 clock-names = "pwm", "pclk";
276 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pwm0m0_pins>;
279 #pwm-cells = <3>;
280 status = "disabled";
281 };
282
283 pwm1: pwm@ff430010 {
284 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
285 reg = <0xff430010 0x10>;
286 clock-names = "pwm", "pclk";
287 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pwm1m0_pins>;
290 #pwm-cells = <3>;
291 status = "disabled";
292 };
293
272 pwm2: pwm@ff430020 {
273 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
274 reg = <0xff430020 0x10>;
275 clock-names = "pwm", "pclk";
276 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
277 pinctrl-names = "default";
278 pinctrl-0 = <&pwm2m0_pins>;
279 #pwm-cells = <3>;
280 status = "disabled";
281 };
282
294 pwm2: pwm@ff430020 {
295 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
296 reg = <0xff430020 0x10>;
297 clock-names = "pwm", "pclk";
298 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&pwm2m0_pins>;
301 #pwm-cells = <3>;
302 status = "disabled";
303 };
304
305 pwm3: pwm@ff430030 {
306 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
307 reg = <0xff430030 0x10>;
308 clock-names = "pwm", "pclk";
309 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&pwm3m0_pins>;
312 #pwm-cells = <3>;
313 status = "disabled";
314 };
315
316 pwm4: pwm@ff440000 {
317 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
318 reg = <0xff440000 0x10>;
319 clock-names = "pwm", "pclk";
320 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&pwm4m0_pins>;
323 #pwm-cells = <3>;
324 status = "disabled";
325 };
326
327 pwm5: pwm@ff440010 {
328 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
329 reg = <0xff440010 0x10>;
330 clock-names = "pwm", "pclk";
331 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pwm5m0_pins>;
334 #pwm-cells = <3>;
335 status = "disabled";
336 };
337
338 pwm6: pwm@ff440020 {
339 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
340 reg = <0xff440020 0x10>;
341 clock-names = "pwm", "pclk";
342 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pwm6m0_pins>;
345 #pwm-cells = <3>;
346 status = "disabled";
347 };
348
349 pwm7: pwm@ff440030 {
350 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
351 reg = <0xff440030 0x10>;
352 clock-names = "pwm", "pclk";
353 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&pwm7m0_pins>;
356 #pwm-cells = <3>;
357 status = "disabled";
358 };
359
283 pmucru: clock-controller@ff480000 {
284 compatible = "rockchip,rv1126-pmucru";
285 reg = <0xff480000 0x1000>;
286 rockchip,grf = <&grf>;
287 #clock-cells = <1>;
288 #reset-cells = <1>;
289 };
290

--- 27 unchanged lines hidden (view full) ---

318 pinctrl-names = "default";
319 pinctrl-0 = <&i2c3m0_xfer>;
320 rockchip,grf = <&pmugrf>;
321 #address-cells = <1>;
322 #size-cells = <0>;
323 status = "disabled";
324 };
325
360 pmucru: clock-controller@ff480000 {
361 compatible = "rockchip,rv1126-pmucru";
362 reg = <0xff480000 0x1000>;
363 rockchip,grf = <&grf>;
364 #clock-cells = <1>;
365 #reset-cells = <1>;
366 };
367

--- 27 unchanged lines hidden (view full) ---

395 pinctrl-names = "default";
396 pinctrl-0 = <&i2c3m0_xfer>;
397 rockchip,grf = <&pmugrf>;
398 #address-cells = <1>;
399 #size-cells = <0>;
400 status = "disabled";
401 };
402
403 pwm8: pwm@ff550000 {
404 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
405 reg = <0xff550000 0x10>;
406 clock-names = "pwm", "pclk";
407 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
408 pinctrl-0 = <&pwm8m0_pins>;
409 pinctrl-names = "default";
410 #pwm-cells = <3>;
411 status = "disabled";
412 };
413
414 pwm9: pwm@ff550010 {
415 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
416 reg = <0xff550010 0x10>;
417 clock-names = "pwm", "pclk";
418 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
419 pinctrl-0 = <&pwm9m0_pins>;
420 pinctrl-names = "default";
421 #pwm-cells = <3>;
422 status = "disabled";
423 };
424
425 pwm10: pwm@ff550020 {
426 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
427 reg = <0xff550020 0x10>;
428 clock-names = "pwm", "pclk";
429 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
430 pinctrl-0 = <&pwm10m0_pins>;
431 pinctrl-names = "default";
432 #pwm-cells = <3>;
433 status = "disabled";
434 };
435
326 pwm11: pwm@ff550030 {
327 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
328 reg = <0xff550030 0x10>;
329 clock-names = "pwm", "pclk";
330 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
331 pinctrl-0 = <&pwm11m0_pins>;
332 pinctrl-names = "default";
333 #pwm-cells = <3>;

--- 331 unchanged lines hidden --- 		436 pwm11: pwm@ff550030 {
437 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
438 reg = <0xff550030 0x10>;
439 clock-names = "pwm", "pclk";
440 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
441 pinctrl-0 = <&pwm11m0_pins>;
442 pinctrl-names = "default";
443 #pwm-cells = <3>;

--- 331 unchanged lines hidden ---