rk3128.dtsi (9107283badc7d058e34ef3b60a52afe6a5e0acfb) rk3128.dtsi (02941bc2a1bc8ea82617ba1fd4d2c0643399a9ea)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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29 #size-cells = <0>;
30
31 cpu0: cpu@f00 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a7";
34 reg = <0xf00>;
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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29 #size-cells = <0>;
30
31 cpu0: cpu@f00 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a7";
34 reg = <0xf00>;
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 resets = <&cru SRST_CORE0>;
37 operating-points = <
38 /* KHz uV */
39 816000 1000000
40 >;
41 #cooling-cells = <2>; /* min followed by max */
42 };
43
44 cpu1: cpu@f01 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a7";
47 reg = <0xf01>;
38 operating-points = <
39 /* KHz uV */
40 816000 1000000
41 >;
42 #cooling-cells = <2>; /* min followed by max */
43 };
44
45 cpu1: cpu@f01 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a7";
48 reg = <0xf01>;
49 resets = <&cru SRST_CORE1>;
48 };
49
50 cpu2: cpu@f02 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a7";
53 reg = <0xf02>;
50 };
51
52 cpu2: cpu@f02 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a7";
55 reg = <0xf02>;
56 resets = <&cru SRST_CORE2>;
54 };
55
56 cpu3: cpu@f03 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a7";
59 reg = <0xf03>;
57 };
58
59 cpu3: cpu@f03 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a7";
62 reg = <0xf03>;
63 resets = <&cru SRST_CORE3>;
60 };
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
67 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

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65 };
66
67 timer {
68 compatible = "arm,armv7-timer";
69 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
70 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
71 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

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