rk3128.dtsi (695b9b57443d88a1c8e0567c88a79d1a4532c75e) rk3128.dtsi (3fd6e33f8fde16869d4cd9cef71ca964b2b0789b)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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265 reset-names = "axi", "ahb",
266 "dclk";
267 power-domains = <&power RK3128_PD_VIO>;
268 status = "disabled";
269
270 vop_out: port {
271 #address-cells = <1>;
272 #size-cells = <0>;
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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265 reset-names = "axi", "ahb",
266 "dclk";
267 power-domains = <&power RK3128_PD_VIO>;
268 status = "disabled";
269
270 vop_out: port {
271 #address-cells = <1>;
272 #size-cells = <0>;
273
274 vop_out_hdmi: endpoint@0 {
275 reg = <0>;
276 remote-endpoint = <&hdmi_in_vop>;
277 };
273 };
274 };
275
276 qos_gpu: qos@1012d000 {
277 compatible = "rockchip,rk3128-qos", "syscon";
278 reg = <0x1012d000 0x20>;
279 };
280

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458 interrupt-names = "otg-bvalid", "otg-id",
459 "linestate";
460 #phy-cells = <0>;
461 status = "disabled";
462 };
463 };
464 };
465
278 };
279 };
280
281 qos_gpu: qos@1012d000 {
282 compatible = "rockchip,rk3128-qos", "syscon";
283 reg = <0x1012d000 0x20>;
284 };
285

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463 interrupt-names = "otg-bvalid", "otg-id",
464 "linestate";
465 #phy-cells = <0>;
466 status = "disabled";
467 };
468 };
469 };
470
471 hdmi: hdmi@20034000 {
472 compatible = "rockchip,rk3128-inno-hdmi";
473 reg = <0x20034000 0x4000>;
474 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&cru PCLK_HDMI>, <&cru DCLK_VOP>;
476 clock-names = "pclk", "ref";
477 pinctrl-names = "default";
478 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
479 power-domains = <&power RK3128_PD_VIO>;
480 status = "disabled";
481
482 ports {
483 #address-cells = <1>;
484 #size-cells = <0>;
485
486 hdmi_in: port@0 {
487 reg = <0>;
488 hdmi_in_vop: endpoint {
489 remote-endpoint = <&vop_out_hdmi>;
490 };
491 };
492
493 hdmi_out: port@1 {
494 reg = <1>;
495 };
496 };
497 };
498
466 timer0: timer@20044000 {
467 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
468 reg = <0x20044000 0x20>;
469 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
470 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
471 clock-names = "pclk", "timer";
472 };
473

--- 710 unchanged lines hidden --- 		499 timer0: timer@20044000 {
500 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
501 reg = <0x20044000 0x20>;
502 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
504 clock-names = "pclk", "timer";
505 };
506

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