rk3128.dtsi (65896f4a3f852f868bd5bbc0abea072b2f6e0470) rk3128.dtsi (171ea1ff14e42041af420ed3745f6f480612baa0)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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272 vop_out: port {
273 #address-cells = <1>;
274 #size-cells = <0>;
275
276 vop_out_hdmi: endpoint@0 {
277 reg = <0>;
278 remote-endpoint = <&hdmi_in_vop>;
279 };
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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272 vop_out: port {
273 #address-cells = <1>;
274 #size-cells = <0>;
275
276 vop_out_hdmi: endpoint@0 {
277 reg = <0>;
278 remote-endpoint = <&hdmi_in_vop>;
279 };
280
281 vop_out_dsi: endpoint@1 {
282 reg = <1>;
283 remote-endpoint = <&dsi_in_vop>;
284 };
280 };
281 };
282
285 };
286 };
287
288 dsi: dsi@10110000 {
289 compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi";
290 reg = <0x10110000 0x4000>;
291 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru PCLK_MIPI>;
293 clock-names = "pclk";
294 phys = <&dphy>;
295 phy-names = "dphy";
296 power-domains = <&power RK3128_PD_VIO>;
297 resets = <&cru SRST_VIO_MIPI_DSI>;
298 reset-names = "apb";
299 rockchip,grf = <&grf>;
300 status = "disabled";
301
302 ports {
303 #address-cells = <1>;
304 #size-cells = <0>;
305
306 dsi_in: port@0 {
307 reg = <0>;
308
309 dsi_in_vop: endpoint {
310 remote-endpoint = <&vop_out_dsi>;
311 };
312 };
313
314 dsi_out: port@1 {
315 reg = <1>;
316 };
317 };
318 };
319
283 qos_gpu: qos@1012d000 {
284 compatible = "rockchip,rk3128-qos", "syscon";
285 reg = <0x1012d000 0x20>;
286 };
287
288 qos_vpu: qos@1012e000 {
289 compatible = "rockchip,rk3128-qos", "syscon";
290 reg = <0x1012e000 0x20>;

--- 940 unchanged lines hidden --- 		320 qos_gpu: qos@1012d000 {
321 compatible = "rockchip,rk3128-qos", "syscon";
322 reg = <0x1012d000 0x20>;
323 };
324
325 qos_vpu: qos@1012e000 {
326 compatible = "rockchip,rk3128-qos", "syscon";
327 reg = <0x1012e000 0x20>;

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