rk3128.dtsi (2c68d26f072b449bd45427241612cb3f8f997f82) rk3128.dtsi (9107283badc7d058e34ef3b60a52afe6a5e0acfb)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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59 reg = <0xf03>;
60 };
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/clock/rk3128-cru.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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59 reg = <0xf03>;
60 };
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
66 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
67 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
68 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
67 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
69 arm,cpu-registers-not-fw-configured;
70 clock-frequency = <24000000>;
71 };
72
73 xin24m: oscillator {
74 compatible = "fixed-clock";
75 clock-frequency = <24000000>;
76 clock-output-names = "xin24m";
77 #clock-cells = <0>;
78 };
79
68 arm,cpu-registers-not-fw-configured;
69 clock-frequency = <24000000>;
70 };
71
72 xin24m: oscillator {
73 compatible = "fixed-clock";
74 clock-frequency = <24000000>;
75 clock-output-names = "xin24m";
76 #clock-cells = <0>;
77 };
78
79 imem: sram@10080000 {
80 compatible = "mmio-sram";
81 reg = <0x10080000 0x2000>;
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges = <0 0x10080000 0x2000>;
85 };
86
80 pmu: syscon@100a0000 {
81 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
82 reg = <0x100a0000 0x1000>;
83 };
84
85 gic: interrupt-controller@10139000 {
86 compatible = "arm,cortex-a7-gic";
87 reg = <0x10139000 0x1000>,

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229 };
230 };
231 };
232
233 timer0: timer@20044000 {
234 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
235 reg = <0x20044000 0x20>;
236 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
87 pmu: syscon@100a0000 {
88 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
89 reg = <0x100a0000 0x1000>;
90 };
91
92 gic: interrupt-controller@10139000 {
93 compatible = "arm,cortex-a7-gic";
94 reg = <0x10139000 0x1000>,

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236 };
237 };
238 };
239
240 timer0: timer@20044000 {
241 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
242 reg = <0x20044000 0x20>;
243 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
244 clocks = <&cru PCLK_TIMER>, <&xin24m>;
238 clock-names = "pclk", "timer";
239 };
240
241 timer1: timer@20044020 {
242 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
243 reg = <0x20044020 0x20>;
244 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 clock-names = "pclk", "timer";
246 };
247
248 timer1: timer@20044020 {
249 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
250 reg = <0x20044020 0x20>;
251 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
252 clocks = <&cru PCLK_TIMER>, <&xin24m>;
246 clock-names = "pclk", "timer";
247 };
248
249 timer2: timer@20044040 {
250 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
251 reg = <0x20044040 0x20>;
252 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
253 clock-names = "pclk", "timer";
254 };
255
256 timer2: timer@20044040 {
257 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
258 reg = <0x20044040 0x20>;
259 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
260 clocks = <&cru PCLK_TIMER>, <&xin24m>;
254 clock-names = "pclk", "timer";
255 };
256
257 timer3: timer@20044060 {
258 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
259 reg = <0x20044060 0x20>;
260 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
261 clock-names = "pclk", "timer";
262 };
263
264 timer3: timer@20044060 {
265 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
266 reg = <0x20044060 0x20>;
267 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
261 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
268 clocks = <&cru PCLK_TIMER>, <&xin24m>;
262 clock-names = "pclk", "timer";
263 };
264
265 timer4: timer@20044080 {
266 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
267 reg = <0x20044080 0x20>;
268 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
269 clock-names = "pclk", "timer";
270 };
271
272 timer4: timer@20044080 {
273 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
274 reg = <0x20044080 0x20>;
275 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
276 clocks = <&cru PCLK_TIMER>, <&xin24m>;
270 clock-names = "pclk", "timer";
271 };
272
273 timer5: timer@200440a0 {
274 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
275 reg = <0x200440a0 0x20>;
276 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
277 clock-names = "pclk", "timer";
278 };
279
280 timer5: timer@200440a0 {
281 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
282 reg = <0x200440a0 0x20>;
283 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
284 clocks = <&cru PCLK_TIMER>, <&xin24m>;
278 clock-names = "pclk", "timer";
279 };
280
281 watchdog: watchdog@2004c000 {
282 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
283 reg = <0x2004c000 0x100>;
284 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru PCLK_WDT>;

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422 resets = <&cru SRST_SARADC>;
423 reset-names = "saradc-apb";
424 #io-channel-cells = <1>;
425 status = "disabled";
426 };
427
428 i2c0: i2c@20072000 {
429 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
285 clock-names = "pclk", "timer";
286 };
287
288 watchdog: watchdog@2004c000 {
289 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
290 reg = <0x2004c000 0x100>;
291 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru PCLK_WDT>;

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429 resets = <&cru SRST_SARADC>;
430 reset-names = "saradc-apb";
431 #io-channel-cells = <1>;
432 status = "disabled";
433 };
434
435 i2c0: i2c@20072000 {
436 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
430 reg = <0x20072000 0x1000>;
437 reg = <20072000 0x1000>;
431 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
432 clock-names = "i2c";
433 clocks = <&cru PCLK_I2C0>;
434 pinctrl-names = "default";
435 pinctrl-0 = <&i2c0_xfer>;
436 #address-cells = <1>;
437 #size-cells = <0>;
438 status = "disabled";

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454 };
455
456 pdma: dma-controller@20078000 {
457 compatible = "arm,pl330", "arm,primecell";
458 reg = <0x20078000 0x4000>;
459 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
461 arm,pl330-broken-no-flushp;
438 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
439 clock-names = "i2c";
440 clocks = <&cru PCLK_I2C0>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&i2c0_xfer>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 status = "disabled";

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461 };
462
463 pdma: dma-controller@20078000 {
464 compatible = "arm,pl330", "arm,primecell";
465 reg = <0x20078000 0x4000>;
466 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
468 arm,pl330-broken-no-flushp;
462 arm,pl330-periph-burst;
463 clocks = <&cru ACLK_DMAC>;
464 clock-names = "apb_pclk";
465 #dma-cells = <1>;
466 };
467
468 pinctrl: pinctrl {
469 compatible = "rockchip,rk3128-pinctrl";
470 rockchip,grf = <&grf>;

--- 448 unchanged lines hidden --- 		469 clocks = <&cru ACLK_DMAC>;
470 clock-names = "apb_pclk";
471 #dma-cells = <1>;
472 };
473
474 pinctrl: pinctrl {
475 compatible = "rockchip,rk3128-pinctrl";
476 rockchip,grf = <&grf>;

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