imx7s.dtsi (36ec807b627b4c0a0a382f0ae48eac7187d14b2b) imx7s.dtsi (e0daff38f48ce33e5691d4bc1df93daca3213c45)
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4// Copyright 2016 Toradex AG
5
6#include <dt-bindings/clock/imx7d-clock.h>
7#include <dt-bindings/power/imx7-power.h>
8#include <dt-bindings/gpio/gpio.h>

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171 arm,cpu-registers-not-fw-configured;
172 interrupt-parent = <&intc>;
173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
177 };
178
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4// Copyright 2016 Toradex AG
5
6#include <dt-bindings/clock/imx7d-clock.h>
7#include <dt-bindings/power/imx7-power.h>
8#include <dt-bindings/gpio/gpio.h>

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171 arm,cpu-registers-not-fw-configured;
172 interrupt-parent = <&intc>;
173 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
174 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
175 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
176 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
177 };
178
179 video_mux: csi-mux {
180 compatible = "video-mux";
181 mux-controls = <&mux 0>;
182 #address-cells = <1>;
183 #size-cells = <0>;
184 status = "disabled";
185
186 port@0 {
187 reg = <0>;
188 };
189
190 port@1 {
191 reg = <1>;
192
193 csi_mux_from_mipi_vc0: endpoint {
194 remote-endpoint = <&mipi_vc0_to_csi_mux>;
195 };
196 };
197
198 port@2 {
199 reg = <2>;
200
201 csi_mux_to_csi: endpoint {
202 remote-endpoint = <&csi_from_csi_mux>;
203 };
204 };
205 };
206
179 soc: soc {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 compatible = "simple-bus";
183 interrupt-parent = <&gpc>;
184 ranges;
185
186 ocram: sram@900000 {

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524 "simple-mfd";
525 reg = <0x30340000 0x10000>;
526
527 mux: mux-controller {
528 compatible = "mmio-mux";
529 #mux-control-cells = <1>;
530 mux-reg-masks = <0x14 0x00000010>;
531 };
207 soc: soc {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 compatible = "simple-bus";
211 interrupt-parent = <&gpc>;
212 ranges;
213
214 ocram: sram@900000 {

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552 "simple-mfd";
553 reg = <0x30340000 0x10000>;
554
555 mux: mux-controller {
556 compatible = "mmio-mux";
557 #mux-control-cells = <1>;
558 mux-reg-masks = <0x14 0x00000010>;
559 };
532
533 video_mux: csi-mux {
534 compatible = "video-mux";
535 mux-controls = <&mux 0>;
536 #address-cells = <1>;
537 #size-cells = <0>;
538 status = "disabled";
539
540 port@0 {
541 reg = <0>;
542 };
543
544 port@1 {
545 reg = <1>;
546
547 csi_mux_from_mipi_vc0: endpoint {
548 remote-endpoint = <&mipi_vc0_to_csi_mux>;
549 };
550 };
551
552 port@2 {
553 reg = <2>;
554
555 csi_mux_to_csi: endpoint {
556 remote-endpoint = <&csi_from_csi_mux>;
557 };
558 };
559 };
560 };
561
562 ocotp: efuse@30350000 {
563 #address-cells = <1>;
564 #size-cells = <1>;
565 compatible = "fsl,imx7d-ocotp", "syscon";
566 reg = <0x30350000 0x10000>;
567 clocks = <&clks IMX7D_OCOTP_CLK>;

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561
562 ocotp: efuse@30350000 {
563 #address-cells = <1>;
564 #size-cells = <1>;
565 compatible = "fsl,imx7d-ocotp", "syscon";
566 reg = <0x30350000 0x10000>;
567 clocks = <&clks IMX7D_OCOTP_CLK>;

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