| head.S (d585a021c0b10b0477d6b608c53e1feb8cde0507) | head.S (26584853a44c58f3d6ac7360d697a2ddcd1a3efa) |
|---|---|
| 1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 424 unchanged lines hidden (view full) --- 433 mov r12, lr 434 bl __setup_mmu 435 mov r0, #0 436 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 437 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 438 mrc p15, 0, r0, c1, c0, 0 @ read control reg 439 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 440 orr r0, r0, #0x0030 | 1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 424 unchanged lines hidden (view full) --- 433 mov r12, lr 434 bl __setup_mmu 435 mov r0, #0 436 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 437 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 438 mrc p15, 0, r0, c1, c0, 0 @ read control reg 439 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 440 orr r0, r0, #0x0030 |
| 441#ifdef CONFIG_CPU_ENDIAN_BE8 442 orr r0, r0, #1 << 25 @ big-endian page tables 443#endif |
|
| 441 bl __common_mmu_cache_on 442 mov r0, #0 443 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 444 mov pc, r12 445 446__armv7_mmu_cache_on: 447 mov r12, lr 448 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 449 tst r11, #0xf @ VMSA 450 blne __setup_mmu 451 mov r0, #0 452 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 453 tst r11, #0xf @ VMSA 454 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 455 mrc p15, 0, r0, c1, c0, 0 @ read control reg 456 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 457 orr r0, r0, #0x003c @ write buffer | 444 bl __common_mmu_cache_on 445 mov r0, #0 446 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 447 mov pc, r12 448 449__armv7_mmu_cache_on: 450 mov r12, lr 451 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 452 tst r11, #0xf @ VMSA 453 blne __setup_mmu 454 mov r0, #0 455 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 456 tst r11, #0xf @ VMSA 457 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 458 mrc p15, 0, r0, c1, c0, 0 @ read control reg 459 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 460 orr r0, r0, #0x003c @ write buffer |
| 461#ifdef CONFIG_CPU_ENDIAN_BE8 462 orr r0, r0, #1 << 25 @ big-endian page tables 463#endif |
|
| 458 orrne r0, r0, #1 @ MMU enabled 459 movne r1, #-1 460 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 461 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 462 mcr p15, 0, r0, c1, c0, 0 @ load control register 463 mrc p15, 0, r0, c1, c0, 0 @ and read it back 464 mov r0, #0 465 mcr p15, 0, r0, c7, c5, 4 @ ISB --- 540 unchanged lines hidden --- | 464 orrne r0, r0, #1 @ MMU enabled 465 movne r1, #-1 466 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 467 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 468 mcr p15, 0, r0, c1, c0, 0 @ load control register 469 mrc p15, 0, r0, c1, c0, 0 @ and read it back 470 mov r0, #0 471 mcr p15, 0, r0, c7, c5, 4 @ ISB --- 540 unchanged lines hidden --- |