platform.c (ed32f8d42cee118b075e4372a55c7739a11094b2) platform.c (ce0eff0d9b4d37702df48a39e3fddb5e39b2c25b)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ARC HSDK Platform support code
4 *
5 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
6 */
7
8#include <linux/init.h>
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ARC HSDK Platform support code
4 *
5 * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
6 */
7
8#include <linux/init.h>
9#include <linux/of_fdt.h>
10#include <linux/libfdt.h>
9#include <linux/smp.h>
10#include <asm/arcregs.h>
11#include <asm/io.h>
12#include <asm/mach_desc.h>
13
11#include <linux/smp.h>
12#include <asm/arcregs.h>
13#include <asm/io.h>
14#include <asm/mach_desc.h>
15
16int arc_hsdk_axi_dmac_coherent __section(.data) = 0;
17
14#define ARC_CCM_UNUSED_ADDR 0x60000000
15
16static void __init hsdk_init_per_cpu(unsigned int cpu)
17{
18 /*
19 * By default ICCM is mapped to 0x7z while this area is used for
20 * kernel virtual mappings, so move it to currently unused area.
21 */

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92
93 iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);
94 iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK);
95 iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);
96 iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);
97 iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
98}
99
18#define ARC_CCM_UNUSED_ADDR 0x60000000
19
20static void __init hsdk_init_per_cpu(unsigned int cpu)
21{
22 /*
23 * By default ICCM is mapped to 0x7z while this area is used for
24 * kernel virtual mappings, so move it to currently unused area.
25 */

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96
97 iowrite32(0xffffffff, (void __iomem *) GPIO_INTMASK);
98 iowrite32(~GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTMASK);
99 iowrite32(0x00000000, (void __iomem *) GPIO_INTTYPE_LEVEL);
100 iowrite32(0xffffffff, (void __iomem *) GPIO_INT_POLARITY);
101 iowrite32(GPIO_INT_CONNECTED_MASK, (void __iomem *) GPIO_INTEN);
102}
103
104static int __init hsdk_tweak_node_coherency(const char *path, bool coherent)
105{
106 void *fdt = initial_boot_params;
107 const void *prop;
108 int node, ret;
109 bool dt_coh_set;
110
111 node = fdt_path_offset(fdt, path);
112 if (node < 0)
113 goto tweak_fail;
114
115 prop = fdt_getprop(fdt, node, "dma-coherent", &ret);
116 if (!prop && ret != -FDT_ERR_NOTFOUND)
117 goto tweak_fail;
118
119 dt_coh_set = ret != -FDT_ERR_NOTFOUND;
120 ret = 0;
121
122 /* need to remove "dma-coherent" property */
123 if (dt_coh_set && !coherent)
124 ret = fdt_delprop(fdt, node, "dma-coherent");
125
126 /* need to set "dma-coherent" property */
127 if (!dt_coh_set && coherent)
128 ret = fdt_setprop(fdt, node, "dma-coherent", NULL, 0);
129
130 if (ret < 0)
131 goto tweak_fail;
132
133 return 0;
134
135tweak_fail:
136 pr_err("failed to tweak %s to %scoherent\n", path, coherent ? "" : "non");
137 return -EFAULT;
138}
139
100enum hsdk_axi_masters {
101 M_HS_CORE = 0,
102 M_HS_RTT,
103 M_AXI_TUN,
104 M_HDMI_VIDEO,
105 M_HDMI_AUDIO,
106 M_USB_HOST,
107 M_ETHERNET,

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157#define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))
158#define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))
159
160#define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
161
162#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
163#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
164
140enum hsdk_axi_masters {
141 M_HS_CORE = 0,
142 M_HS_RTT,
143 M_AXI_TUN,
144 M_HDMI_VIDEO,
145 M_HDMI_AUDIO,
146 M_USB_HOST,
147 M_ETHERNET,

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197#define CREG_AXI_M_OFT1(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x0C))
198#define CREG_AXI_M_UPDT(m) ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x14))
199
200#define CREG_AXI_M_HS_CORE_BOOT ((void __iomem *)(CREG_BASE + 0x010))
201
202#define CREG_PAE ((void __iomem *)(CREG_BASE + 0x180))
203#define CREG_PAE_UPDT ((void __iomem *)(CREG_BASE + 0x194))
204
205static void __init hsdk_init_memory_bridge_axi_dmac(void)
206{
207 bool coherent = !!arc_hsdk_axi_dmac_coherent;
208 u32 axi_m_slv1, axi_m_oft1;
209
210 /*
211 * Don't tweak memory bridge configuration if we failed to tweak DTB
212 * as we will end up in a inconsistent state.
213 */
214 if (hsdk_tweak_node_coherency("/soc/dmac@80000", coherent))
215 return;
216
217 if (coherent) {
218 axi_m_slv1 = 0x77999999;
219 axi_m_oft1 = 0x76DCBA98;
220 } else {
221 axi_m_slv1 = 0x77777777;
222 axi_m_oft1 = 0x76543210;
223 }
224
225 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
226 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
227 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));
228 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_0));
229 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
230
231 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
232 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
233 writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));
234 writel(axi_m_oft1, CREG_AXI_M_OFT1(M_DMAC_1));
235 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
236}
237
165static void __init hsdk_init_memory_bridge(void)
166{
167 u32 reg;
168
169 /*
170 * M_HS_CORE has one unique register - BOOT.
171 * We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first
172 * aperture to be masked by 'boot mirror'.

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222 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
223
224 writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
225 writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
226 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
227 writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
228 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
229
238static void __init hsdk_init_memory_bridge(void)
239{
240 u32 reg;
241
242 /*
243 * M_HS_CORE has one unique register - BOOT.
244 * We need to clean boot mirror (BOOT[1:0]) bits in them to avoid first
245 * aperture to be masked by 'boot mirror'.

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295 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
296
297 writel(0x77777777, CREG_AXI_M_SLV0(M_GPU));
298 writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));
299 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));
300 writel(0x76543210, CREG_AXI_M_OFT1(M_GPU));
301 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_GPU));
302
230 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_0));
231 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_0));
232 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));
233 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_0));
234 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_0));
235
236 writel(0x77777777, CREG_AXI_M_SLV0(M_DMAC_1));
237 writel(0x77777777, CREG_AXI_M_SLV1(M_DMAC_1));
238 writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));
239 writel(0x76543210, CREG_AXI_M_OFT1(M_DMAC_1));
240 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DMAC_1));
241
242 writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
243 writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
244 writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
245 writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
246 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
247
303 writel(0x00000000, CREG_AXI_M_SLV0(M_DVFS));
304 writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));
305 writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));
306 writel(0x00000000, CREG_AXI_M_OFT1(M_DVFS));
307 writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_DVFS));
308
309 hsdk_init_memory_bridge_axi_dmac();
310
248 /*
249 * PAE remapping for DMA clients does not work due to an RTL bug, so
250 * CREG_PAE register must be programmed to all zeroes, otherwise it
251 * will cause problems with DMA to/from peripherals even if PAE40 is
252 * not used.
253 */
254 writel(0x00000000, CREG_PAE);
255 writel(UPDATE_VAL, CREG_PAE_UPDT);

--- 25 unchanged lines hidden --- 		311 /*
312 * PAE remapping for DMA clients does not work due to an RTL bug, so
313 * CREG_PAE register must be programmed to all zeroes, otherwise it
314 * will cause problems with DMA to/from peripherals even if PAE40 is
315 * not used.
316 */
317 writel(0x00000000, CREG_PAE);
318 writel(UPDATE_VAL, CREG_PAE_UPDT);

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