tlbex.S (0ef88a54aa341f754707414500158addbf35c780) tlbex.S (41195d236e84458bebd4fdc218610a92231ac791)
1/*
2 * TLB Exception Handling for ARC
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

--- 43 unchanged lines hidden (view full) ---

52; scratch memory to save the registers (r0-r3) used to code TLB refill Handler
53; For details refer to comments before TLBMISS_FREEUP_REGS below
54;--------------------------------------------------------------------------
55
56 .section .data
57 .global ex_saved_reg1
58 .align 1 << L1_CACHE_SHIFT ; IMP: Must be Cache Line aligned
59 .type ex_saved_reg1, @object
1/*
2 * TLB Exception Handling for ARC
3 *
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

--- 43 unchanged lines hidden (view full) ---

52; scratch memory to save the registers (r0-r3) used to code TLB refill Handler
53; For details refer to comments before TLBMISS_FREEUP_REGS below
54;--------------------------------------------------------------------------
55
56 .section .data
57 .global ex_saved_reg1
58 .align 1 << L1_CACHE_SHIFT ; IMP: Must be Cache Line aligned
59 .type ex_saved_reg1, @object
60#ifdef CONFIG_SMP
61 .size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
62ex_saved_reg1:
63 .zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
64#else
60 .size ex_saved_reg1, 16
61ex_saved_reg1:
62 .zero 16
65 .size ex_saved_reg1, 16
66ex_saved_reg1:
67 .zero 16
68#endif
63
64;============================================================================
65; Troubleshooting Stuff
66;============================================================================
67
68; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
69; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
70; we use the MMU PID Reg to get current ASID.

--- 40 unchanged lines hidden (view full) ---

111
112;-----------------------------------------------------------------------------
113; This macro does the page-table lookup for the faulting address.
114; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
115.macro LOAD_FAULT_PTE
116
117 lr r2, [efa]
118
69
70;============================================================================
71; Troubleshooting Stuff
72;============================================================================
73
74; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
75; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
76; we use the MMU PID Reg to get current ASID.

--- 40 unchanged lines hidden (view full) ---

117
118;-----------------------------------------------------------------------------
119; This macro does the page-table lookup for the faulting address.
120; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
121.macro LOAD_FAULT_PTE
122
123 lr r2, [efa]
124
125#ifndef CONFIG_SMP
119 lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
126 lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
127#else
128 GET_CURR_TASK_ON_CPU r1
129 ld r1, [r1, TASK_ACT_MM]
130 ld r1, [r1, MM_PGD]
131#endif
120
121 lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
122 ld.as r1, [r1, r0] ; PGD entry corresp to faulting addr
123 and.f r1, r1, PAGE_MASK ; Ignoring protection and other flags
124 ; contains Ptr to Page Table
125 bz.d do_slow_path_pf ; if no Page Table, do page fault
126
127 ; Get the PTE entry: The idea is

--- 59 unchanged lines hidden (view full) ---

187; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
188; "global" is used to free-up FIRST core reg to be able to code the rest of
189; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
190; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
191; need to be saved as well by extending the "global" to be 4 words. Hence
192; ".size ex_saved_reg1, 16"
193; [All of this dance is to avoid stack switching for each TLB Miss, since we
194; only need to save only a handful of regs, as opposed to complete reg file]
132
133 lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
134 ld.as r1, [r1, r0] ; PGD entry corresp to faulting addr
135 and.f r1, r1, PAGE_MASK ; Ignoring protection and other flags
136 ; contains Ptr to Page Table
137 bz.d do_slow_path_pf ; if no Page Table, do page fault
138
139 ; Get the PTE entry: The idea is

--- 59 unchanged lines hidden (view full) ---

199; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
200; "global" is used to free-up FIRST core reg to be able to code the rest of
201; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
202; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
203; need to be saved as well by extending the "global" to be 4 words. Hence
204; ".size ex_saved_reg1, 16"
205; [All of this dance is to avoid stack switching for each TLB Miss, since we
206; only need to save only a handful of regs, as opposed to complete reg file]
207;
208; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
209; core reg as it will not be SMP safe.
210; Thus scratch AUX reg is used (and no longer used to cache task PGD).
211; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
212; Epilogue thus has to locate the "per-cpu" storage for regs.
213; To avoid cache line bouncing the per-cpu global is aligned/sized per
214; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
215; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
195
196; As simple as that....
197
198.macro TLBMISS_FREEUP_REGS
216
217; As simple as that....
218
219.macro TLBMISS_FREEUP_REGS
220#ifdef CONFIG_SMP
221 sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
222 GET_CPU_ID r0 ; get to per cpu scratch mem,
223 lsl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
224 add r0, @ex_saved_reg1, r0
225#else
199 st r0, [@ex_saved_reg1]
200 mov_s r0, @ex_saved_reg1
226 st r0, [@ex_saved_reg1]
227 mov_s r0, @ex_saved_reg1
228#endif
201 st_s r1, [r0, 4]
202 st_s r2, [r0, 8]
203 st_s r3, [r0, 12]
204
205 ; VERIFY if the ASID in MMU-PID Reg is same as
206 ; one in Linux data structures
207
208 DBG_ASID_MISMATCH
209.endm
210
211;-----------------------------------------------------------------
212.macro TLBMISS_RESTORE_REGS
229 st_s r1, [r0, 4]
230 st_s r2, [r0, 8]
231 st_s r3, [r0, 12]
232
233 ; VERIFY if the ASID in MMU-PID Reg is same as
234 ; one in Linux data structures
235
236 DBG_ASID_MISMATCH
237.endm
238
239;-----------------------------------------------------------------
240.macro TLBMISS_RESTORE_REGS
241#ifdef CONFIG_SMP
242 GET_CPU_ID r0 ; get to per cpu scratch mem
243 lsl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
244 add r0, @ex_saved_reg1, r0
245 ld_s r3, [r0,12]
246 ld_s r2, [r0, 8]
247 ld_s r1, [r0, 4]
248 lr r0, [ARC_REG_SCRATCH_DATA0]
249#else
213 mov_s r0, @ex_saved_reg1
214 ld_s r3, [r0,12]
215 ld_s r2, [r0, 8]
216 ld_s r1, [r0, 4]
217 ld_s r0, [r0]
250 mov_s r0, @ex_saved_reg1
251 ld_s r3, [r0,12]
252 ld_s r2, [r0, 8]
253 ld_s r1, [r0, 4]
254 ld_s r0, [r0]
255#endif
218.endm
219
220.section .text, "ax",@progbits ;Fast Path Code, candidate for ICCM
221
222;-----------------------------------------------------------------------------
223; I-TLB Miss Exception Handler
224;-----------------------------------------------------------------------------
225

--- 146 unchanged lines hidden --- 		256.endm
257
258.section .text, "ax",@progbits ;Fast Path Code, candidate for ICCM
259
260;-----------------------------------------------------------------------------
261; I-TLB Miss Exception Handler
262;-----------------------------------------------------------------------------
263

--- 146 unchanged lines hidden ---