cache.c (e497c8e52a83ebb5309ab41c8851c9cb53f28b73) cache.c (76894a72a0d7e0759de272bf3f4d2279ebd86d0b)
1/*
2 * ARC Cache Management
3 *
4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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988 * doesn't perturb caches or coherency unit
989 *
990 * 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
991 * otherwise any straggler data might behave strangely post IOC enabling
992 *
993 * 3. All Caches need to be disabled when setting up IOC to elide any in-flight
994 * Coherency transactions
995 */
1/*
2 * ARC Cache Management
3 *
4 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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988 * doesn't perturb caches or coherency unit
989 *
990 * 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
991 * otherwise any straggler data might behave strangely post IOC enabling
992 *
993 * 3. All Caches need to be disabled when setting up IOC to elide any in-flight
994 * Coherency transactions
995 */
996noinline void arc_ioc_setup(void)
996noinline void __init arc_ioc_setup(void)
997{
998 unsigned int ap_sz;
999
1000 /* Flush + invalidate + disable L1 dcache */
1001 __dc_disable();
1002
1003 /* Flush + invalidate SLC */
1004 if (read_aux_reg(ARC_REG_SLC_BCR))

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1018
1019 write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
1020 write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
1021
1022 /* Re-enable L1 dcache */
1023 __dc_enable();
1024}
1025
997{
998 unsigned int ap_sz;
999
1000 /* Flush + invalidate + disable L1 dcache */
1001 __dc_disable();
1002
1003 /* Flush + invalidate SLC */
1004 if (read_aux_reg(ARC_REG_SLC_BCR))

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1018
1019 write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
1020 write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
1021
1022 /* Re-enable L1 dcache */
1023 __dc_enable();
1024}
1025
1026void arc_cache_init(void)
1026void __init arc_cache_init_master(void)
1027{
1028 unsigned int __maybe_unused cpu = smp_processor_id();
1027{
1028 unsigned int __maybe_unused cpu = smp_processor_id();
1029 char str[256];
1030
1029
1031 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
1032
1033 /*
1034 * Only master CPU needs to execute rest of function:
1035 * - Assume SMP so all cores will have same cache config so
1036 * any geomtry checks will be same for all
1037 * - IOC setup / dma callbacks only need to be setup once
1038 */
1039 if (cpu)
1040 return;
1041
1042 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
1043 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
1044
1045 if (!ic->line_len)
1046 panic("cache support enabled but non-existent cache\n");
1047
1048 if (ic->line_len != L1_CACHE_BYTES)
1049 panic("ICache line [%d] != kernel Config [%d]",

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1101 __dma_cache_inv = __dma_cache_inv_slc;
1102 __dma_cache_wback = __dma_cache_wback_slc;
1103 } else {
1104 __dma_cache_wback_inv = __dma_cache_wback_inv_l1;
1105 __dma_cache_inv = __dma_cache_inv_l1;
1106 __dma_cache_wback = __dma_cache_wback_l1;
1107 }
1108}
1030 if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
1031 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
1032
1033 if (!ic->line_len)
1034 panic("cache support enabled but non-existent cache\n");
1035
1036 if (ic->line_len != L1_CACHE_BYTES)
1037 panic("ICache line [%d] != kernel Config [%d]",

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1089 __dma_cache_inv = __dma_cache_inv_slc;
1090 __dma_cache_wback = __dma_cache_wback_slc;
1091 } else {
1092 __dma_cache_wback_inv = __dma_cache_wback_inv_l1;
1093 __dma_cache_inv = __dma_cache_inv_l1;
1094 __dma_cache_wback = __dma_cache_wback_l1;
1095 }
1096}
1097
1098void __ref arc_cache_init(void)
1099{
1100 unsigned int __maybe_unused cpu = smp_processor_id();
1101 char str[256];
1102
1103 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
1104
1105 /*
1106 * Only master CPU needs to execute rest of function:
1107 * - Assume SMP so all cores will have same cache config so
1108 * any geomtry checks will be same for all
1109 * - IOC setup / dma callbacks only need to be setup once
1110 */
1111 if (!cpu)
1112 arc_cache_init_master();
1113}