irq_pyxis.c (f0eef25339f92f7cd4aeea23d9ae97987a5a1e82) irq_pyxis.c (44377f622ee4f23ea0afc9b83dba5d3ec2d560cd)
1/*
2 * linux/arch/alpha/kernel/irq_pyxis.c
3 *
4 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
5 *
6 * IRQ Code common to all PYXIS core logic chips.
7 */
8

--- 56 unchanged lines hidden (view full) ---

65 wmb();
66 /* Ack PYXIS PCI interrupt. */
67 *(vulp)PYXIS_INT_REQ = bit;
68 mb();
69 /* Re-read to force both writes. */
70 *(vulp)PYXIS_INT_MASK;
71}
72
1/*
2 * linux/arch/alpha/kernel/irq_pyxis.c
3 *
4 * Based on code written by David A Rusling (david.rusling@reo.mts.dec.com).
5 *
6 * IRQ Code common to all PYXIS core logic chips.
7 */
8

--- 56 unchanged lines hidden (view full) ---

65 wmb();
66 /* Ack PYXIS PCI interrupt. */
67 *(vulp)PYXIS_INT_REQ = bit;
68 mb();
69 /* Re-read to force both writes. */
70 *(vulp)PYXIS_INT_MASK;
71}
72
73static struct hw_interrupt_type pyxis_irq_type = {
73static struct irq_chip pyxis_irq_type = {
74 .typename = "PYXIS",
75 .startup = pyxis_startup_irq,
76 .shutdown = pyxis_disable_irq,
77 .enable = pyxis_enable_irq,
78 .disable = pyxis_disable_irq,
79 .ack = pyxis_mask_and_ack_irq,
80 .end = pyxis_end_irq,
81};

--- 46 unchanged lines hidden --- 		74 .typename = "PYXIS",
75 .startup = pyxis_startup_irq,
76 .shutdown = pyxis_disable_irq,
77 .enable = pyxis_enable_irq,
78 .disable = pyxis_disable_irq,
79 .ack = pyxis_mask_and_ack_irq,
80 .end = pyxis_end_irq,
81};

--- 46 unchanged lines hidden ---