mpic.txt (6b7b8e488bbdedeccabdd001a78ffcbe43bb8a3a) mpic.txt (180076cb11a5f02de7d26f8cb82969b895a26f40)
1=====================================================================
2Freescale MPIC Interrupt Controller Node
3Copyright (C) 2010,2011 Freescale Semiconductor Inc.
4=====================================================================
5
6The Freescale MPIC interrupt controller is found on all PowerQUICC
7and QorIQ processors and is compatible with the Open PIC. The
8notable difference from Open PIC binding is the addition of 2

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185EXAMPLE 4
186 /*
187 * Definition of a node defining the MPIC
188 * global timers. Note the interrupt
189 * type of 3.
190 */
191 timer0: timer@41100 {
192 compatible = "fsl,mpic-global-timer";
1=====================================================================
2Freescale MPIC Interrupt Controller Node
3Copyright (C) 2010,2011 Freescale Semiconductor Inc.
4=====================================================================
5
6The Freescale MPIC interrupt controller is found on all PowerQUICC
7and QorIQ processors and is compatible with the Open PIC. The
8notable difference from Open PIC binding is the addition of 2

--- 176 unchanged lines hidden (view full) ---

185EXAMPLE 4
186 /*
187 * Definition of a node defining the MPIC
188 * global timers. Note the interrupt
189 * type of 3.
190 */
191 timer0: timer@41100 {
192 compatible = "fsl,mpic-global-timer";
193 reg = <0x41100 0x100>;
193 reg = <0x41100 0x100 0x41300 4>;
194 interrupts = <0 0 3 0
195 1 0 3 0
196 2 0 3 0
197 3 0 3 0>;
198 };
199
200EXAMPLE 5
201 /*
202 * Definition of an error interrupt (interrupt type 1).
203 * SoC interrupt number is 16 and the specific error
204 * interrupt bit in the error interrupt summary register
205 * is 23.
206 */
207 memory-controller@8000 {
208 compatible = "fsl,p4080-memory-controller";
209 reg = <0x8000 0x1000>;
210 interrupts = <16 2 1 23>;
211 };
194 interrupts = <0 0 3 0
195 1 0 3 0
196 2 0 3 0
197 3 0 3 0>;
198 };
199
200EXAMPLE 5
201 /*
202 * Definition of an error interrupt (interrupt type 1).
203 * SoC interrupt number is 16 and the specific error
204 * interrupt bit in the error interrupt summary register
205 * is 23.
206 */
207 memory-controller@8000 {
208 compatible = "fsl,p4080-memory-controller";
209 reg = <0x8000 0x1000>;
210 interrupts = <16 2 1 23>;
211 };