mediatek,tphy.yaml (9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e) mediatek,tphy.yaml (188a447b20f83b58f89413aaa811d7f1dc247638)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek T-PHY Controller

--- 50 unchanged lines hidden (view full) ---

59
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
62 added on V2; the FMREG bank for slew rate calibration is not used anymore
63 and reserved on V3;
64
65properties:
66 $nodename:
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek T-PHY Controller

--- 50 unchanged lines hidden (view full) ---

59
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
62 added on V2; the FMREG bank for slew rate calibration is not used anymore
63 and reserved on V3;
64
65properties:
66 $nodename:
67 pattern: "^t-phy@[0-9a-f]+$"
67 pattern: "^t-phy(@[0-9a-f]+)?$"
68
69 compatible:
70 oneOf:
71 - items:
72 - enum:
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy

--- 238 unchanged lines hidden --- 		68
69 compatible:
70 oneOf:
71 - items:
72 - enum:
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy

--- 238 unchanged lines hidden ---