nand-controller.yaml (db6da59cf27b5661ced03754ae0550f8914eda9e) nand-controller.yaml (46721a1c9f829fe934eb1ec03e19b9e2896b995a)
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NAND Controller Common Properties
8
9maintainers:
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
12
13description: |
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers supporting only one chip.
18
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NAND Controller Common Properties
8
9maintainers:
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
12
13description: |
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers supporting only one chip.
18
19 The ECC strength and ECC step size properties define the user
20 desires in terms of correction capability of a controller. Together,
21 they request the ECC engine to correct {strength} bit errors per
22 {size} bytes.
23
24 The interpretation of these parameters is implementation-defined, so
25 not all implementations must support all possible
26 combinations. However, implementations are encouraged to further
27 specify the value(s) they support.
28
29properties:
30 $nodename:
31 pattern: "^nand-controller(@.*)?"
32
33 "#address-cells":
34 const: 1
35
36 "#size-cells":

--- 9 unchanged lines hidden (view full) ---

46 chip-select as needed may follow and should be phandles of GPIO
47 lines. 'reg' entries of the NAND chip subnodes become indexes of
48 this array when this property is present.
49 minItems: 1
50 maxItems: 8
51
52patternProperties:
53 "^nand@[a-f0-9]$":
19properties:
20 $nodename:
21 pattern: "^nand-controller(@.*)?"
22
23 "#address-cells":
24 const: 1
25
26 "#size-cells":

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36 chip-select as needed may follow and should be phandles of GPIO
37 lines. 'reg' entries of the NAND chip subnodes become indexes of
38 this array when this property is present.
39 minItems: 1
40 maxItems: 8
41
42patternProperties:
43 "^nand@[a-f0-9]$":
54 $ref: nand-chip.yaml#
44 type: object
45 $ref: raw-nand-chip.yaml#
55
46
56 properties:
57 reg:
58 description:
59 Contains the chip-select IDs.
60
61 nand-ecc-placement:
62 description:
63 Location of the ECC bytes. This location is unknown by default
64 but can be explicitly set to "oob", if all ECC bytes are
65 known to be stored in the OOB area, or "interleaved" if ECC
66 bytes will be interleaved with regular data in the main area.
67 $ref: /schemas/types.yaml#/definitions/string
68 enum: [ oob, interleaved ]
69
70 nand-bus-width:
71 description:
72 Bus width to the NAND chip
73 $ref: /schemas/types.yaml#/definitions/uint32
74 enum: [8, 16]
75 default: 8
76
77 nand-on-flash-bbt:
78 description:
79 With this property, the OS will search the device for a Bad
80 Block Table (BBT). If not found, it will create one, reserve
81 a few blocks at the end of the device to store it and update
82 it as the device ages. Otherwise, the out-of-band area of a
83 few pages of all the blocks will be scanned at boot time to
84 find Bad Block Markers (BBM). These markers will help to
85 build a volatile BBT in RAM.
86 $ref: /schemas/types.yaml#/definitions/flag
87
88 nand-ecc-maximize:
89 description:
90 Whether or not the ECC strength should be maximized. The
91 maximum ECC strength is both controller and chip
92 dependent. The ECC engine has to select the ECC config
93 providing the best strength and taking the OOB area size
94 constraint into account. This is particularly useful when
95 only the in-band area is used by the upper layers, and you
96 want to make your NAND as reliable as possible.
97 $ref: /schemas/types.yaml#/definitions/flag
98
99 nand-is-boot-medium:
100 description:
101 Whether or not the NAND chip is a boot medium. Drivers might
102 use this information to select ECC algorithms supported by
103 the boot ROM or similar restrictions.
104 $ref: /schemas/types.yaml#/definitions/flag
105
106 nand-rb:
107 description:
108 Contains the native Ready/Busy IDs.
109 $ref: /schemas/types.yaml#/definitions/uint32-array
110
111 rb-gpios:
112 description:
113 Contains one or more GPIO descriptor (the numper of descriptor
114 depends on the number of R/B pins exposed by the flash) for the
115 Ready/Busy pins. Active state refers to the NAND ready state and
116 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
117
118 wp-gpios:
119 description:
120 Contains one GPIO descriptor for the Write Protect pin.
121 Active state refers to the NAND Write Protect state and should be
122 set to GPIOD_ACTIVE_LOW unless the signal is inverted.
123 maxItems: 1
124
125 required:
126 - reg
127
128required:
129 - "#address-cells"
130 - "#size-cells"
131
132# This is a generic file other binding inherit from and extend
133additionalProperties: true
134
135examples:

--- 17 unchanged lines hidden --- 		47required:
48 - "#address-cells"
49 - "#size-cells"
50
51# This is a generic file other binding inherit from and extend
52additionalProperties: true
53
54examples:

--- 17 unchanged lines hidden ---