| hwprobe.rst (bf4cd84111c6139313504310ff934df901a5ed3e) | hwprobe.rst (74ba42b250a7339c72e5803490b1ea42c3556f26) |
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| 1.. SPDX-License-Identifier: GPL-2.0 2 3RISC-V Hardware Probing Interface 4--------------------------------- 5 6The RISC-V hardware probing interface is based around a single syscall, which 7is defined in <asm/hwprobe.h>:: 8 --- 132 unchanged lines hidden (view full) --- 141 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. 142 143 * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported 144 as defined in the RISC-V ISA manual. 145 146 * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is 147 supported as defined in the RISC-V ISA manual. 148 | 1.. SPDX-License-Identifier: GPL-2.0 2 3RISC-V Hardware Probing Interface 4--------------------------------- 5 6The RISC-V hardware probing interface is based around a single syscall, which 7is defined in <asm/hwprobe.h>:: 8 --- 132 unchanged lines hidden (view full) --- 141 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. 142 143 * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported 144 as defined in the RISC-V ISA manual. 145 146 * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is 147 supported as defined in the RISC-V ISA manual. 148 |
| 149 * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 150 is supported as defined in the RISC-V ISA manual. 151 |
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| 149* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance 150 information about the selected set of processors. 151 152 * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned 153 accesses is unknown. 154 155 * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are 156 emulated via software, either in or below the kernel. These accesses are --- 14 unchanged lines hidden --- | 152* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance 153 information about the selected set of processors. 154 155 * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned 156 accesses is unknown. 157 158 * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are 159 emulated via software, either in or below the kernel. These accesses are --- 14 unchanged lines hidden --- |