| spr.h (cf0c300484581ec1cd37b915fb1ba487754b3cf1) | spr.h (fe48da3f4114650c9db621804278205587259be5) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 546 unchanged lines hidden (view full) --- 555#define ESR_SPE 0x00000080 /* SPE exception bit */ 556 557#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */ 558#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ 559#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ 560#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ 561 562#define SPR_SVR 0x3ff /* ..8 1023 System Version Register */ | 1/*- 2 * Copyright (c) 2001 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 546 unchanged lines hidden (view full) --- 555#define ESR_SPE 0x00000080 /* SPE exception bit */ 556 557#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */ 558#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ 559#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ 560#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ 561 562#define SPR_SVR 0x3ff /* ..8 1023 System Version Register */ |
| 563#define SVR_MPC8533 0x803c0010 564#define SVR_MPC8533E 0x80340010 565#define SVR_MPC8541 0x80720011 566#define SVR_MPC8541E 0x807a0011 567#define SVR_MPC8555 0x80710011 568#define SVR_MPC8555E 0x80790011 569#define SVR_MPC8572 0x80e00010 570#define SVR_MPC8572E 0x80e80010 | 563#define SVR_MPC8533 0x803c 564#define SVR_MPC8533E 0x8034 565#define SVR_MPC8541 0x8072 566#define SVR_MPC8541E 0x807a 567#define SVR_MPC8555 0x8071 568#define SVR_MPC8555E 0x8079 569#define SVR_MPC8572 0x80e0 570#define SVR_MPC8572E 0x80e8 571#define SVR_VER(svr) (((svr) >> 16) & 0xffff) |
| 571 572#define SPR_PID0 0x030 /* ..8 Process ID Register 0 */ 573#define SPR_PID1 0x279 /* ..8 Process ID Register 1 */ 574#define SPR_PID2 0x27a /* ..8 Process ID Register 2 */ 575 576#define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */ 577#define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */ 578#define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */ --- 39 unchanged lines hidden (view full) --- 618#define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */ 619#define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */ 620#define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */ 621#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 622#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 623 624#endif /* #elif defined(E500) */ 625 | 572 573#define SPR_PID0 0x030 /* ..8 Process ID Register 0 */ 574#define SPR_PID1 0x279 /* ..8 Process ID Register 1 */ 575#define SPR_PID2 0x27a /* ..8 Process ID Register 2 */ 576 577#define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */ 578#define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */ 579#define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */ --- 39 unchanged lines hidden (view full) --- 619#define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */ 620#define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */ 621#define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */ 622#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 623#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 624 625#endif /* #elif defined(E500) */ 626 |
| 626 | |
| 627#endif /* !_POWERPC_SPR_H_ */ | 627#endif /* !_POWERPC_SPR_H_ */ |