spr.h (2598954edc2fa4daadfb2eaf4698e3d918c0a897) spr.h (b57e802a8521cd90a2f8e3f2612ac107ac9a3591)
1/*-
1/*
2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the NetBSD
16 * Foundation, Inc. and its contributors.
17 * 4. Neither the name of The NetBSD Foundation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
15 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 *
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
26 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $
27 * $FreeBSD$
28 */
29#ifndef _POWERPC_SPR_H_
30#define _POWERPC_SPR_H_
31
32#ifndef _LOCORE
33#define mtspr(reg, val) \
34 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
35#define mfspr(reg) \
33 * $FreeBSD$
34 */
35#ifndef _POWERPC_SPR_H_
36#define _POWERPC_SPR_H_
37
38#ifndef _LOCORE
39#define mtspr(reg, val) \
40 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
41#define mfspr(reg) \
36 ( { register_t val; \
42 ( { u_int32_t val; \
37 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
38 val; } )
43 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
44 val; } )
39
40/* The following routines allow manipulation of the full 64-bit width
41 * of SPRs on 64 bit CPUs in bridge mode */
42
43#define mtspr64(reg,valhi,vallo,scratch) \
44 __asm __volatile(" \
45 mfmsr %0; \
46 insrdi %0,%5,1,0; \
47 mtmsrd %0; \
48 isync; \
49 \
50 sld %1,%1,%4; \
51 or %1,%1,%2; \
52 mtspr %3,%1; \
53 srd %1,%1,%4; \
54 \
55 clrldi %0,%0,1; \
56 mtmsrd %0; \
57 isync;" \
58 : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1))
59
60#define mfspr64upper(reg,scratch) \
61 ( { register_t val; \
62 __asm __volatile(" \
63 mfmsr %0; \
64 insrdi %0,%4,1,0; \
65 mtmsrd %0; \
66 isync; \
67 \
68 mfspr %1,%2; \
69 srd %1,%1,%3; \
70 \
71 clrldi %0,%0,1; \
72 mtmsrd %0; \
73 isync;" \
74 : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \
75 val; } )
76
77#endif /* _LOCORE */
78
79/*
80 * Special Purpose Register declarations.
81 *
82 * The first column in the comments indicates which PowerPC
83 * architectures the SPR is valid on - 4 for 4xx series,
84 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series.

--- 16 unchanged lines hidden (view full) ---

101#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
102#define SPR_DAR 0x013 /* .68 Data Address Register */
103#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */
104#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */
105#define SPR_DEC 0x016 /* .68 DECrementer register */
106#define SPR_SDR1 0x019 /* .68 Page table base address register */
107#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
108#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
45#endif /* _LOCORE */
46
47/*
48 * Special Purpose Register declarations.
49 *
50 * The first column in the comments indicates which PowerPC
51 * architectures the SPR is valid on - 4 for 4xx series,
52 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series.

--- 16 unchanged lines hidden (view full) ---

69#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */
70#define SPR_DAR 0x013 /* .68 Data Address Register */
71#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */
72#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */
73#define SPR_DEC 0x016 /* .68 DECrementer register */
74#define SPR_SDR1 0x019 /* .68 Page table base address register */
75#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
76#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
109#define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */
110#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */
111#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */
112#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */
113#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
77#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
114#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
115#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
116#define SPR_SPRG1 0x111 /* 468 SPR General 1 */
117#define SPR_SPRG2 0x112 /* 468 SPR General 2 */
118#define SPR_SPRG3 0x113 /* 468 SPR General 3 */
119#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */
120#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */
121#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */
122#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */
78#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
79#define SPR_SPRG1 0x111 /* 468 SPR General 1 */
80#define SPR_SPRG2 0x112 /* 468 SPR General 2 */
81#define SPR_SPRG3 0x113 /* 468 SPR General 3 */
82#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */
83#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */
84#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */
85#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */
123#define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */
124#define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */
125#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */
126#define SPR_EAR 0x11a /* .68 External Access Register */
86#define SPR_EAR 0x11a /* .68 External Access Register */
87#define SPR_TBL 0x11c /* 468 Time Base Lower */
88#define SPR_TBU 0x11d /* 468 Time Base Upper */
127#define SPR_PVR 0x11f /* 468 Processor Version Register */
89#define SPR_PVR 0x11f /* 468 Processor Version Register */
128#define MPC601 0x0001
129#define MPC603 0x0003
130#define MPC604 0x0004
131#define MPC602 0x0005
132#define MPC603e 0x0006
133#define MPC603ev 0x0007
134#define MPC750 0x0008
135#define MPC604ev 0x0009
136#define MPC7400 0x000c
137#define MPC620 0x0014
138#define IBM403 0x0020
139#define IBM401A1 0x0021
140#define IBM401B2 0x0022
141#define IBM401C2 0x0023
142#define IBM401D2 0x0024
143#define IBM401E2 0x0025
144#define IBM401F2 0x0026
145#define IBM401G2 0x0027
146#define IBM970 0x0039
147#define IBM970FX 0x003c
148#define IBMPOWER3 0x0041
149#define IBM970MP 0x0044
150#define IBM970GX 0x0045
151#define MPC860 0x0050
152#define MPC8240 0x0081
153#define IBM405GP 0x4011
154#define IBM405L 0x4161
155#define IBM750FX 0x7000
156#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000)
157#define MPC7450 0x8000
158#define MPC7455 0x8001
159#define MPC7457 0x8002
160#define MPC7447A 0x8003
161#define MPC7448 0x8004
162#define MPC7410 0x800c
163#define MPC8245 0x8081
164#define FSL_E500v1 0x8020
165#define FSL_E500v2 0x8021
166
90#define MPC601 0x0001
91#define MPC603 0x0003
92#define MPC604 0x0004
93#define MPC602 0x0005
94#define MPC603e 0x0006
95#define MPC603ev 0x0007
96#define MPC750 0x0008
97#define MPC604ev 0x0009
98#define MPC7400 0x000c
99#define MPC620 0x0014
100#define MPC860 0x0050
101#define MPC8240 0x0081
102#define MPC7450 0x8000
103#define MPC7455 0x8001
104#define MPC7410 0x800c
105#define IBM405GP 0x4011
106#define IBM405L 0x4161
167#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
107#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
168#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */
169#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */
170#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */
171#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */
172#define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */
173#define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */
174#define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */
175#define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */
176#define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */
177#define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */
178#define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */
179#define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */
180#define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */
181#define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */
182#define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */
183#define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */
184#define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */
185#define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */
186#define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */
187#define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */
188#define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */
189#define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */
190#define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */
191#define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */
192#define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */
193#define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */
194#define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */
195#define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */
196#define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */
197#define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */
198#define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */
199#define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */
200#define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */
201#define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */
202#define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */
203#define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */
204#define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */
205#define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */
206#define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */
207#define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */
208#define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */
209#define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */
210#define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */
211#define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */
212#define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */
213#define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */
214#define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */
215#define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */
216#define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */
217#define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */
218#define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */
219#define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */
220#define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */
221#define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */
222#define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */
223#define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */
224#define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */
225#define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */
226#define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */
227#define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */
228#define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */
229#define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */
230#define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */
231#define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */
232#define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */
233#define SPR_MI_CTR 0x310 /* ..8 IMMU control */
234#define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */
235#define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */
236#define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */
237#define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */
238#define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */
239#define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */
240#define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */
241#define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */
242#define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */
243#define SPR_MI_AP 0x312 /* ..8 IMMU access protection */
244#define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */
245#define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */
246#define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */
247#define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */
248#define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */
249#define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */
250#define Mx_EPN_EV 0x00000020 /* Entry Valid */
251#define Mx_EPN_ASID 0x0000000f /* Address Space ID */
252#define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */
253#define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */
254#define Mx_TWC_APG 0x000001e0 /* Access Protection Group */
255#define Mx_TWC_G 0x00000010 /* Guarded memory */
256#define Mx_TWC_PS 0x0000000c /* Page Size (L1) */
257#define MD_TWC_WT 0x00000002 /* Write-Through */
258#define Mx_TWC_V 0x00000001 /* Entry Valid */
259#define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */
260#define Mx_RPN_RPN 0xfffff000 /* Real Page Number */
261#define Mx_RPN_PP 0x00000ff0 /* Page Protection */
262#define Mx_RPN_SPS 0x00000008 /* Small Page Size */
263#define Mx_RPN_SH 0x00000004 /* SHared page */
264#define Mx_RPN_CI 0x00000002 /* Cache Inhibit */
265#define Mx_RPN_V 0x00000001 /* Valid */
266#define SPR_MD_CTR 0x318 /* ..8 DMMU control */
267#define SPR_M_CASID 0x319 /* ..8 CASID */
268#define M_CASID 0x0000000f /* Current AS Id */
269#define SPR_MD_AP 0x31a /* ..8 DMMU access protection */
270#define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */
271#define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */
272#define M_TWB_L1TB 0xfffff000 /* level-1 translation base */
273#define M_TWB_L1INDX 0x00000ffc /* level-1 index */
274#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */
275#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */
276#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */
277#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */
278#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */
279#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */
280#define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */
281#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */
282#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */
108#define SPR_IBAT0L 0x211 /* .68 Instruction BAT Reg 0 Lower */
109#define SPR_IBAT1U 0x212 /* .68 Instruction BAT Reg 1 Upper */
110#define SPR_IBAT1L 0x213 /* .68 Instruction BAT Reg 1 Lower */
111#define SPR_IBAT2U 0x214 /* .68 Instruction BAT Reg 2 Upper */
112#define SPR_IBAT2L 0x215 /* .68 Instruction BAT Reg 2 Lower */
113#define SPR_IBAT3U 0x216 /* .68 Instruction BAT Reg 3 Upper */
114#define SPR_IBAT3L 0x217 /* .68 Instruction BAT Reg 3 Lower */
115#define SPR_DBAT0U 0x218 /* .68 Data BAT Reg 0 Upper */
116#define SPR_DBAT0L 0x219 /* .68 Data BAT Reg 0 Lower */
117#define SPR_DBAT1U 0x21a /* .68 Data BAT Reg 1 Upper */
118#define SPR_DBAT1L 0x21b /* .68 Data BAT Reg 1 Lower */
119#define SPR_DBAT2U 0x21c /* .68 Data BAT Reg 2 Upper */
120#define SPR_DBAT2L 0x21d /* .68 Data BAT Reg 2 Lower */
121#define SPR_DBAT3U 0x21e /* .68 Data BAT Reg 3 Upper */
122#define SPR_DBAT3L 0x21f /* .68 Data BAT Reg 3 Lower */
123#define SPI_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */
124#define SPI_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */
125#define SPI_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */
126#define SPI_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */
127#define SPI_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */
128#define SPI_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */
129#define SPI_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */
130#define SPI_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */
131#define SPI_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */
132#define SPI_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */
133#define SPI_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */
134#define SPI_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */
135#define SPI_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */
136#define SPI_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */
137#define SPI_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */
138#define SPI_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */
283#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */
284#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */
285#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */
286#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */
287#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */
288#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */
289#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */
290#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */
291#define SPR_PID 0x3b1 /* 4.. Process ID */
292#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */
293#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */
294#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */
295#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */
296#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */
297#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */
298#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */
299#define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */
139#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */
140#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */
141#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */
142#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */
143#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */
144#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */
145#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */
146#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */
147#define SPR_PID 0x3b1 /* 4.. Process ID */
148#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */
149#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */
150#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */
151#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */
152#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */
153#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */
154#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */
155#define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */
300
301#define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */
302#define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */
303#define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */
304#define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */
305#define SPR_970PMC1 0x313 /* ... PMC 1 */
306#define SPR_970PMC2 0x314 /* ... PMC 2 */
307#define SPR_970PMC3 0x315 /* ... PMC 3 */
308#define SPR_970PMC4 0x316 /* ... PMC 4 */
309#define SPR_970PMC5 0x317 /* ... PMC 5 */
310#define SPR_970PMC6 0x318 /* ... PMC 6 */
311#define SPR_970PMC7 0x319 /* ... PMC 7 */
312#define SPR_970PMC8 0x31a /* ... PMC 8 */
313
314#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */
315#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */
316#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */
317#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */
318#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */
319#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */
320#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */
321#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */
322#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */
323#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */
324#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */
325#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */
326#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */
327#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */
328#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */
329#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */
330#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */
331#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */
156#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */
157#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */
158#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */
159#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */
160#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */
161#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */
162#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */
163#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */
164#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */
165#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */
166#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */
167#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */
168#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */
169#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */
170#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */
171#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */
172#define SPR_MMCR0_PMC1SEL(x) ((x) << 6) /* PMC1 selector */
173#define SPR_MMCR0_PMC2SEL(x) ((x) << 0) /* PMC2 selector */
332#define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */
333#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */
334#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */
335#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */
336#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */
337#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */
338#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */
339#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */
340#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */
341#define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */
342#define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */
343#define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */
344#define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */
345
346#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */
174#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */
175#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */
176#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */
177#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */
178#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */
179#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */
180#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */
181#define SPR_MMCR1_PMC3SEL(x) ((x) << 27) /* PMC 3 selector */
182#define SPR_MMCR1_PMC4SEL(x) ((x) << 22) /* PMC 4 selector */
183#define SPR_MMCR1_PMC5SEL(x) ((x) << 17) /* PMC 5 selector */
184#define SPR_MMCR1_PMC6SEL(x) ((x) << 11) /* PMC 6 selector */
185
186#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */
187#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */
347#define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */
348#define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */
349#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */
350#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */
351#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */
352#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */
353#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */
188#define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */
189#define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */
190#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */
191#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */
192#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */
193#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */
194#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */
195#define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */
196#define ESR_MCI 0x80000000 /* Machine check - instruction */
197#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
198#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
199#define ESR_PTR 0x02000000 /* Program interrupt - trap */
200#define ESR_DST 0x00800000 /* Data storage interrupt - store fault */
201#define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */
202#define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */
354#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */
355#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */
356#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */
357#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */
358#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */
359#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */
360#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */
361#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */
203#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */
204#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */
205#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */
206#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */
207#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */
208#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */
209#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */
210#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */
362
363#define SPR_TSR 0x150 /* ..8 Timer Status Register */
364#define SPR_TCR 0x154 /* ..8 Timer Control Register */
365
211#define SPR_TSR 0x3d8 /* 4.. Timer Status Register */
366#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
367#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */
368#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */
369#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */
370#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */
371#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */
372#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */
373#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
212#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
213#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */
214#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */
215#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */
216#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */
217#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */
218#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */
219#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
374#define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */
375#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
220#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
376
221#define SPR_TCR 0x3da /* 4.. Timer Control Register */
377#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */
378#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */
379#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */
380#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */
381#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */
382#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */
383#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */
384#define TCR_WRC_CORE 0x10000000 /* Core reset */
385#define TCR_WRC_CHIP 0x20000000 /* Chip reset */
386#define TCR_WRC_SYSTEM 0x30000000 /* System reset */
387#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
388#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
222#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */
223#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */
224#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */
225#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */
226#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */
227#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */
228#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */
229#define TCR_WRC_CORE 0x10000000 /* Core reset */
230#define TCR_WRC_CHIP 0x20000000 /* Chip reset */
231#define TCR_WRC_SYSTEM 0x30000000 /* System reset */
232#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
233#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
389#define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */
390#define TCR_FP_MASK 0x03000000 /* FIT Period */
391#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */
392#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */
393#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */
394#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */
395#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
396#define TCR_ARE 0x00400000 /* Auto Reload Enable */
234#define TCR_FP_MASK 0x03000000 /* FIT Period */
235#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */
236#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */
237#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */
238#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */
239#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
240#define TCR_ARE 0x00400000 /* Auto Reload Enable */
397
398#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */
399#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */
400#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */
241#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */
242#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */
243#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */
401#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */
402#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */
403#define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */
404#define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */
405
406#if defined(AIM)
407#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */
408#define DBSR_IC 0x80000000 /* Instruction completion debug event */
409#define DBSR_BT 0x40000000 /* Branch Taken debug event */
410#define DBSR_EDE 0x20000000 /* Exception debug event */
411#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */
412#define DBSR_UDE 0x08000000 /* Unconditional debug event */
413#define DBSR_IA1 0x04000000 /* IAC1 debug event */
414#define DBSR_IA2 0x02000000 /* IAC2 debug event */
415#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */
416#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */
417#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */
418#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */
419#define DBSR_IDE 0x00100000 /* Imprecise debug event */
420#define DBSR_IA3 0x00080000 /* IAC3 debug event */
421#define DBSR_IA4 0x00040000 /* IAC4 debug event */
422#define DBSR_MRR 0x00000300 /* Most recent reset */
244#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */
245#define DBSR_IC 0x80000000 /* Instruction completion debug event */
246#define DBSR_BT 0x40000000 /* Branch Taken debug event */
247#define DBSR_EDE 0x20000000 /* Exception debug event */
248#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */
249#define DBSR_UDE 0x08000000 /* Unconditional debug event */
250#define DBSR_IA1 0x04000000 /* IAC1 debug event */
251#define DBSR_IA2 0x02000000 /* IAC2 debug event */
252#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */
253#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */
254#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */
255#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */
256#define DBSR_IDE 0x00100000 /* Imprecise debug event */
257#define DBSR_IA3 0x00080000 /* IAC3 debug event */
258#define DBSR_IA4 0x00040000 /* IAC4 debug event */
259#define DBSR_MRR 0x00000300 /* Most recent reset */
260#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */
261#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */
423#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */
262#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */
424#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */
425#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */
426#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */
427#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */
428#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */
429#define SPR_PIR 0x3ff /* .6. Processor Identification Register */
430#elif defined(E500)
431#define SPR_PIR 0x11e /* ..8 Processor Identification Register */
432#define SPR_DBSR 0x130 /* ..8 Debug Status Register */
433#define DBSR_IDE 0x80000000 /* Imprecise debug event. */
434#define DBSR_UDE 0x40000000 /* Unconditional debug event. */
435#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */
436#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */
437#define DBSR_BRT 0x04000000 /* Branch taken debug event. */
438#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */
439#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */
440#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */
441#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */
442#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */
443#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */
444#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */
445#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */
446#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */
447#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */
448#define DBSR_RET 0x00008000 /* Return debug event. */
449#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */
450#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */
451#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */
452#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */
453#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */
454#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */
455#endif
456
457#define DBCR0_EDM 0x80000000 /* External Debug Mode */
458#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
459#define DBCR0_RST_MASK 0x30000000 /* ReSeT */
460#define DBCR0_RST_NONE 0x00000000 /* No action */
461#define DBCR0_RST_CORE 0x10000000 /* Core reset */
462#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
463#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
464#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */

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471#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */
472#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */
473#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */
474#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */
475#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */
476#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
477#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
478#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
263#define DBCR0_EDM 0x80000000 /* External Debug Mode */
264#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
265#define DBCR0_RST_MASK 0x30000000 /* ReSeT */
266#define DBCR0_RST_NONE 0x00000000 /* No action */
267#define DBCR0_RST_CORE 0x10000000 /* Core reset */
268#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */
269#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */
270#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */

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277#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */
278#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */
279#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */
280#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */
281#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */
282#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
283#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
284#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
479
480#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */
285#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */
286#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */
287#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */
288#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */
481#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */
289#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */
482#define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */
483#define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */
484#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
485#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
486#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/
487#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */
488#define MSSCR0_MBO 0x00400000 /* 9: must be one */
489#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */
490#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */
491#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */
290#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */
291#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */
492#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */
493#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */
292#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */
293#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */
494#define L2CR_L2E 0x80000000 /* 0: L2 enable */
495#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */
496#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
497#define L2SIZ_2M 0x00000000
498#define L2SIZ_256K 0x10000000
499#define L2SIZ_512K 0x20000000
500#define L2SIZ_1M 0x30000000
501#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */
502#define L2CLK_DIS 0x00000000 /* disable L2 clock */
503#define L2CLK_10 0x02000000 /* core clock / 1 */
504#define L2CLK_15 0x04000000 /* / 1.5 */
505#define L2CLK_20 0x08000000 /* / 2 */
506#define L2CLK_25 0x0a000000 /* / 2.5 */
507#define L2CLK_30 0x0c000000 /* / 3 */
508#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
509#define L2RAM_FLOWTHRU_BURST 0x00000000
510#define L2RAM_PIPELINE_BURST 0x01000000
511#define L2RAM_PIPELINE_LATE 0x01800000
512#define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
294#define L2CR_L2E 0x80000000 /* 0: L2 enable */
295#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */
296#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
297#define L2SIZ_2M 0x00000000
298#define L2SIZ_256K 0x10000000
299#define L2SIZ_512K 0x20000000
300#define L2SIZ_1M 0x30000000
301#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */
302#define L2CLK_DIS 0x00000000 /* disable L2 clock */
303#define L2CLK_10 0x02000000 /* core clock / 1 */
304#define L2CLK_15 0x04000000 /* / 1.5 */
305#define L2CLK_20 0x08000000 /* / 2 */
306#define L2CLK_25 0x0a000000 /* / 2.5 */
307#define L2CLK_30 0x0c000000 /* / 3 */
308#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
309#define L2RAM_FLOWTHRU_BURST 0x00000000
310#define L2RAM_PIPELINE_BURST 0x01000000
311#define L2RAM_PIPELINE_LATE 0x01800000
312#define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
513 Setting this bit disables instruction
514 caching. */
313 Setting this bit disables instruction
314 caching. */
515#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */
516#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable).
315#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */
316#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable).
517 Enables automatic operation of the
518 L2ZZ (low-power mode) signal. */
317 Enables automatic operation of the
318 L2ZZ (low-power mode) signal. */
519#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
520#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */
521#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
522#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */
523#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */
524#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */
525#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */
526#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */
527#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */
528#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */
529#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */
530#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */
319#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
320#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */
321#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
322#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */
323#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */
324#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */
325#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */
531 /* progress (read only). */
326 /* progress (read only). */
532
533#define SPR_L3CR 0x3fa /* .6. L3 Control Register */
327#define SPR_L3CR 0x3fa /* .6. L3 Control Register */
534#define L3CR_L3E 0x80000000 /* 0: L3 enable */
535#define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */
536#define L3CR_L3APE 0x20000000
537#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
538#define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */
539#define L3CR_L3CLK 0x03800000
540#define L3CR_L3IO 0x00400000
541#define L3CR_L3CLKEXT 0x00200000
542#define L3CR_L3CKSPEXT 0x00100000
543#define L3CR_L3OH1 0x00080000
544#define L3CR_L3SPO 0x00040000
545#define L3CR_L3CKSP 0x00030000
546#define L3CR_L3PSP 0x0000e000
547#define L3CR_L3REP 0x00001000
548#define L3CR_L3HWF 0x00000800
549#define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */
550#define L3CR_L3RT 0x00000300
551#define L3CR_L3NIRCA 0x00000080
552#define L3CR_L3DO 0x00000040
553#define L3CR_PMEN 0x00000004
554#define L3CR_PMSIZ 0x00000003
555
328#define L3CR_L3E 0x80000000 /* 0: L3 enable */
329#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */
556#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */
557#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */
558#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */
559#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */
560#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */
561#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */
562#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */
563#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */
564#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */
565#define SPR_THRM_VALID 0x00000001 /* Valid bit */
566#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */
567#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */
568#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */
569#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */
330#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */
331#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */
332#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */
333#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */
334#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */
335#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */
336#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */
337#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */
338#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */
339#define SPR_THRM_VALID 0x00000001 /* Valid bit */
340#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */
341#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */
342#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */
343#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */
344#define SPR_PIR 0x3ff /* .6. Processor Identification Register */
570
571/* Time Base Register declarations */
345
346/* Time Base Register declarations */
572#define TBR_TBL 0x10c /* 468 Time Base Lower - read */
573#define TBR_TBU 0x10d /* 468 Time Base Upper - read */
574#define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */
575#define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */
347#define TBR_TBL 0x10c /* 468 Time Base Lower */
348#define TBR_TBU 0x10d /* 468 Time Base Upper */
576
577/* Performance counter declarations */
578#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */
579
349
350/* Performance counter declarations */
351#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */
352
580/* The first five countable [non-]events are common to many PMC's */
353/* The first five countable [non-]events are common to all the PMC's */
581#define PMCN_NONE 0 /* Count nothing */
582#define PMCN_CYCLES 1 /* Processor cycles */
583#define PMCN_ICOMP 2 /* Instructions completed */
584#define PMCN_TBLTRANS 3 /* TBL bit transitions */
585#define PCMN_IDISPATCH 4 /* Instructions dispatched */
586
354#define PMCN_NONE 0 /* Count nothing */
355#define PMCN_CYCLES 1 /* Processor cycles */
356#define PMCN_ICOMP 2 /* Instructions completed */
357#define PMCN_TBLTRANS 3 /* TBL bit transitions */
358#define PCMN_IDISPATCH 4 /* Instructions dispatched */
359
587/* Similar things for the 970 PMC direct counters */
588#define PMC970N_NONE 0x8 /* Count nothing */
589#define PMC970N_CYCLES 0xf /* Processor cycles */
590#define PMC970N_ICOMP 0x9 /* Instructions completed */
591
592#if defined(AIM)
593
594#define SPR_ESR 0x3d4 /* 4.. Exception Syndrome Register */
595#define ESR_MCI 0x80000000 /* Machine check - instruction */
596#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
597#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
598#define ESR_PTR 0x02000000 /* Program interrupt - trap */
599#define ESR_ST 0x01000000 /* Store operation */
600#define ESR_DST 0x00800000 /* Data storage interrupt - store fault */
601#define ESR_DIZ 0x00800000 /* Data/instruction storage interrupt - zone fault */
602#define ESR_U0F 0x00008000 /* Data storage interrupt - U0 fault */
603
604#elif defined(E500)
605
606#define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */
607#define ESR_PIL 0x08000000 /* Program interrupt - illegal */
608#define ESR_PPR 0x04000000 /* Program interrupt - privileged */
609#define ESR_PTR 0x02000000 /* Program interrupt - trap */
610#define ESR_ST 0x00800000 /* Store operation */
611#define ESR_DLK 0x00200000 /* Data storage, D cache locking */
612#define ESR_ILK 0x00100000 /* Data storage, I cache locking */
613#define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */
614#define ESR_SPE 0x00000080 /* SPE exception bit */
615
616#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */
617#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */
618#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */
619#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */
620
621#define SPR_SVR 0x3ff /* ..8 1023 System Version Register */
622#define SVR_MPC8533 0x803c
623#define SVR_MPC8533E 0x8034
624#define SVR_MPC8541 0x8072
625#define SVR_MPC8541E 0x807a
626#define SVR_MPC8548 0x8031
627#define SVR_MPC8548E 0x8039
628#define SVR_MPC8555 0x8071
629#define SVR_MPC8555E 0x8079
630#define SVR_MPC8572 0x80e0
631#define SVR_MPC8572E 0x80e8
632#define SVR_VER(svr) (((svr) >> 16) & 0xffff)
633
634#define SPR_PID0 0x030 /* ..8 Process ID Register 0 */
635#define SPR_PID1 0x279 /* ..8 Process ID Register 1 */
636#define SPR_PID2 0x27a /* ..8 Process ID Register 2 */
637
638#define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */
639#define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */
640#define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */
641#define TLBCFG_ASSOC_SHIFT 24
642#define TLBCFG_NENTRY_MASK 0x00000fff /* Number of entries in TLB */
643
644#define SPR_IVPR 0x03f /* ..8 Interrupt Vector Prefix Register */
645#define SPR_IVOR0 0x190 /* ..8 Critical input */
646#define SPR_IVOR1 0x191 /* ..8 Machine check */
647#define SPR_IVOR2 0x192
648#define SPR_IVOR3 0x193
649#define SPR_IVOR4 0x194
650#define SPR_IVOR5 0x195
651#define SPR_IVOR6 0x196
652#define SPR_IVOR7 0x197
653#define SPR_IVOR8 0x198
654#define SPR_IVOR9 0x199
655#define SPR_IVOR10 0x19a
656#define SPR_IVOR11 0x19b
657#define SPR_IVOR12 0x19c
658#define SPR_IVOR13 0x19d
659#define SPR_IVOR14 0x19e
660#define SPR_IVOR15 0x19f
661#define SPR_IVOR32 0x210
662#define SPR_IVOR33 0x211
663#define SPR_IVOR34 0x212
664#define SPR_IVOR35 0x213
665
666#define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */
667#define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */
668#define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */
669#define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */
670#define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */
671#define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */
672#define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */
673#define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */
674
675#define SPR_L1CSR0 0x3F2 /* ..8 L1 Cache Control and Status Register 0 */
676#define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */
677#define L1CSR0_DCLFR 0x00000100 /* Data Cache Lock Bits Flash Reset */
678#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
679#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
680#define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */
681#define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */
682#define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */
683#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
684#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
685
686#define SPR_BUCSR 0x3F5 /* ..8 Branch Unit Control and Status Register */
687#define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */
688
689#endif /* #elif defined(E500) */
690
691#endif /* !_POWERPC_SPR_H_ */
360#endif /* !_POWERPC_SPR_H_ */