spr.h (09c817ba36db7c3a4ff5e25ac55816ca181a403d) spr.h (999987e51a2db77e5407c5a2cdb5d759b1317714)
1/*-
2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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45 val; } )
46
47/* The following routines allow manipulation of the full 64-bit width
48 * of SPRs on 64 bit CPUs in bridge mode */
49
50#define mtspr64(reg,valhi,vallo,scratch) \
51 __asm __volatile(" \
52 mfmsr %0; \
1/*-
2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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45 val; } )
46
47/* The following routines allow manipulation of the full 64-bit width
48 * of SPRs on 64 bit CPUs in bridge mode */
49
50#define mtspr64(reg,valhi,vallo,scratch) \
51 __asm __volatile(" \
52 mfmsr %0; \
53 insrdi %0,1,1,0; \
53 insrdi %0,%5,1,0; \
54 mtmsrd %0; \
55 isync; \
56 \
57 sld %1,%1,%4; \
58 or %1,%1,%2; \
59 mtspr %3,%1; \
60 srd %1,%1,%4; \
61 \
62 clrldi %0,%0,1; \
63 mtmsrd %0; \
64 isync;" \
54 mtmsrd %0; \
55 isync; \
56 \
57 sld %1,%1,%4; \
58 or %1,%1,%2; \
59 mtspr %3,%1; \
60 srd %1,%1,%4; \
61 \
62 clrldi %0,%0,1; \
63 mtmsrd %0; \
64 isync;" \
65 : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32))
65 : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1))
66
67#define mfspr64upper(reg,scratch) \
68 ( { register_t val; \
69 __asm __volatile(" \
70 mfmsr %0; \
66
67#define mfspr64upper(reg,scratch) \
68 ( { register_t val; \
69 __asm __volatile(" \
70 mfmsr %0; \
71 insrdi %0,1,1,0; \
71 insrdi %0,%4,1,0; \
72 mtmsrd %0; \
73 isync; \
74 \
75 mfspr %1,%2; \
76 srd %1,%1,%3; \
77 \
78 clrldi %0,%0,1; \
79 mtmsrd %0; \
80 isync;" \
72 mtmsrd %0; \
73 isync; \
74 \
75 mfspr %1,%2; \
76 srd %1,%1,%3; \
77 \
78 clrldi %0,%0,1; \
79 mtmsrd %0; \
80 isync;" \
81 : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32)); \
81 : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \
82 val; } )
83
84#endif /* _LOCORE */
85
86/*
87 * Special Purpose Register declarations.
88 *
89 * The first column in the comments indicates which PowerPC

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83
84#endif /* _LOCORE */
85
86/*
87 * Special Purpose Register declarations.
88 *
89 * The first column in the comments indicates which PowerPC

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