mp_cpudep.c (2e370a5c7a5528afb124f6273136736e5d5fb798) mp_cpudep.c (999987e51a2db77e5407c5a2cdb5d759b1317714)
1/*-
2 * Copyright (c) 2008 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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43#include <machine/psl.h>
44#include <machine/smp.h>
45#include <machine/spr.h>
46#include <machine/trap_aim.h>
47
48#include <dev/ofw/openfirm.h>
49#include <machine/ofw_machdep.h>
50
1/*-
2 * Copyright (c) 2008 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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43#include <machine/psl.h>
44#include <machine/smp.h>
45#include <machine/spr.h>
46#include <machine/trap_aim.h>
47
48#include <dev/ofw/openfirm.h>
49#include <machine/ofw_machdep.h>
50
51extern void *rstcode;
52extern register_t l2cr_config;
53extern register_t l3cr_config;
54
55void *ap_pcpu;
56
51void *ap_pcpu;
52
53static register_t bsp_state[8];
54
55static void cpudep_save_config(void *dummy);
56SYSINIT(cpu_save_config, SI_SUB_CPU, SI_ORDER_ANY, cpudep_save_config, NULL);
57
58uintptr_t
59cpudep_ap_bootstrap(void)
60{
61 register_t msr, sp;
62
63 msr = PSL_KERNSET & ~PSL_EE;
64 mtmsr(msr);
65 isync();
66
67 __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
68 powerpc_sync();
69
70 pcpup->pc_curthread = pcpup->pc_idlethread;
71 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
72 sp = pcpup->pc_curpcb->pcb_sp;
73
74 return (sp);
75}
76
57static register_t
77static register_t
58l2_enable(void)
78mpc745x_l2_enable(register_t l2cr_config)
59{
60 register_t ccr;
61
62 ccr = mfspr(SPR_L2CR);
63 if (ccr & L2CR_L2E)
64 return (ccr);
65
66 /* Configure L2 cache. */

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72 powerpc_sync();
73 mtspr(SPR_L2CR, l2cr_config);
74 powerpc_sync();
75
76 return (l2cr_config);
77}
78
79static register_t
79{
80 register_t ccr;
81
82 ccr = mfspr(SPR_L2CR);
83 if (ccr & L2CR_L2E)
84 return (ccr);
85
86 /* Configure L2 cache. */

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92 powerpc_sync();
93 mtspr(SPR_L2CR, l2cr_config);
94 powerpc_sync();
95
96 return (l2cr_config);
97}
98
99static register_t
80l3_enable(void)
100mpc745x_l3_enable(register_t l3cr_config)
81{
82 register_t ccr;
83
84 ccr = mfspr(SPR_L3CR);
85 if (ccr & L3CR_L3E)
86 return (ccr);
87
88 /* Configure L3 cache. */

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104 ccr |= L3CR_L3E;
105 mtspr(SPR_L3CR, ccr);
106 powerpc_sync();
107
108 return(ccr);
109}
110
111static register_t
101{
102 register_t ccr;
103
104 ccr = mfspr(SPR_L3CR);
105 if (ccr & L3CR_L3E)
106 return (ccr);
107
108 /* Configure L3 cache. */

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124 ccr |= L3CR_L3E;
125 mtspr(SPR_L3CR, ccr);
126 powerpc_sync();
127
128 return(ccr);
129}
130
131static register_t
112l1d_enable(void)
132mpc745x_l1d_enable(void)
113{
114 register_t hid;
115
116 hid = mfspr(SPR_HID0);
117 if (hid & HID0_DCE)
118 return (hid);
119
120 /* Enable L1 D-cache */
121 hid |= HID0_DCE;
122 powerpc_sync();
123 mtspr(SPR_HID0, hid | HID0_DCFI);
124 powerpc_sync();
125
126 return (hid);
127}
128
129static register_t
133{
134 register_t hid;
135
136 hid = mfspr(SPR_HID0);
137 if (hid & HID0_DCE)
138 return (hid);
139
140 /* Enable L1 D-cache */
141 hid |= HID0_DCE;
142 powerpc_sync();
143 mtspr(SPR_HID0, hid | HID0_DCFI);
144 powerpc_sync();
145
146 return (hid);
147}
148
149static register_t
130l1i_enable(void)
150mpc745x_l1i_enable(void)
131{
132 register_t hid;
133
134 hid = mfspr(SPR_HID0);
135 if (hid & HID0_ICE)
136 return (hid);
137
138 /* Enable L1 I-cache */
139 hid |= HID0_ICE;
140 isync();
141 mtspr(SPR_HID0, hid | HID0_ICFI);
142 isync();
143
144 return (hid);
145}
146
151{
152 register_t hid;
153
154 hid = mfspr(SPR_HID0);
155 if (hid & HID0_ICE)
156 return (hid);
157
158 /* Enable L1 I-cache */
159 hid |= HID0_ICE;
160 isync();
161 mtspr(SPR_HID0, hid | HID0_ICFI);
162 isync();
163
164 return (hid);
165}
166
147uint32_t
148cpudep_ap_bootstrap(void)
167static void
168cpudep_save_config(void *dummy)
149{
169{
150 uint32_t hid, msr, reg, sp;
170 uint16_t vers;
151
171
152 // reg = mfspr(SPR_MSSCR0);
153 // mtspr(SPR_MSSCR0, reg | 0x3);
172 vers = mfpvr() >> 16;
154
173
155 __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu));
156 powerpc_sync();
174 switch(vers) {
175 case IBM970:
176 case IBM970FX:
177 case IBM970MP:
178 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
179 : "=r" (bsp_state[0]),"=r" (bsp_state[1]) : "K" (SPR_HID0));
180 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
181 : "=r" (bsp_state[2]),"=r" (bsp_state[3]) : "K" (SPR_HID1));
182 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
183 : "=r" (bsp_state[4]),"=r" (bsp_state[5]) : "K" (SPR_HID4));
184 __asm __volatile ("mfspr %0,%2; mr %1,%0; srdi %0,%0,32"
185 : "=r" (bsp_state[6]),"=r" (bsp_state[7]) : "K" (SPR_HID5));
157
186
158 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
159 __asm __volatile("mfspr %0,1023" : "=r"(pcpup->pc_pir));
187 break;
188 case MPC7450:
189 case MPC7455:
190 case MPC7457:
191 /* Only MPC745x CPUs have an L3 cache. */
192 bsp_state[3] = mfspr(SPR_L3CR);
160
193
161 msr = PSL_FP | PSL_IR | PSL_DR | PSL_ME | PSL_RI;
162 powerpc_sync();
163 isync();
164 mtmsr(msr);
165 isync();
194 /* Fallthrough */
195 case MPC7400:
196 case MPC7410:
197 case MPC7447A:
198 case MPC7448:
199 bsp_state[2] = mfspr(SPR_L2CR);
200 bsp_state[1] = mfspr(SPR_HID1);
201 bsp_state[0] = mfspr(SPR_HID0);
202 break;
203 }
204}
166
205
167 if (l3cr_config != 0)
168 reg = l3_enable();
169 if (l2cr_config != 0)
170 reg = l2_enable();
171 reg = l1d_enable();
172 reg = l1i_enable();
206void
207cpudep_ap_setup()
208{
209 register_t reg;
210 uint16_t vers;
173
211
174 hid = mfspr(SPR_HID0);
175 hid &= ~(HID0_DOZE | HID0_SLEEP);
176 hid |= HID0_NAP | HID0_DPM;
177 mtspr(SPR_HID0, hid);
178 isync();
212 vers = mfpvr() >> 16;
179
213
180 pcpup->pc_curthread = pcpup->pc_idlethread;
181 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
182 sp = pcpup->pc_curpcb->pcb_sp;
214 switch(vers) {
215 case IBM970:
216 case IBM970FX:
217 case IBM970MP:
218 /* Set HIOR to 0 */
219 __asm __volatile("mtspr 311,%0" :: "r"(0));
220 powerpc_sync();
183
221
184 return (sp);
222 /*
223 * The 970 has strange rules about how to update HID registers.
224 * See Table 2-3, 970MP manual
225 */
226
227 __asm __volatile(" \
228 ld %0,0(%2); \
229 mtspr %1, %0; \
230 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1; \
231 mfspr %0, %1; mfspr %0, %1; mfspr %0, %1;"
232 : "=r"(reg) : "K"(SPR_HID0), "r"(bsp_state));
233 __asm __volatile("ld %0, 8(%2); mtspr %1, %0; mtspr %1, %0; \
234 isync" : "=r"(reg) : "K"(SPR_HID1), "r"(bsp_state));
235 __asm __volatile("ld %0, 16(%2); sync; mtspr %1, %0; isync;"
236 : "=r"(reg) : "K"(SPR_HID4), "r"(bsp_state));
237 __asm __volatile("ld %0, 24(%2); sync; mtspr %1, %0; isync;"
238 : "=r"(reg) : "K"(SPR_HID5), "r"(bsp_state));
239
240 powerpc_sync();
241 break;
242 case MPC7450:
243 case MPC7455:
244 case MPC7457:
245 /* Only MPC745x CPUs have an L3 cache. */
246 reg = mpc745x_l3_enable(bsp_state[3]);
247
248 /* Fallthrough */
249 case MPC7400:
250 case MPC7410:
251 case MPC7447A:
252 case MPC7448:
253 /* XXX: Program the CPU ID into PIR */
254 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid)));
255
256 powerpc_sync();
257 isync();
258
259 mtspr(SPR_HID0, bsp_state[0]); isync();
260 mtspr(SPR_HID1, bsp_state[1]); isync();
261
262 reg = mpc745x_l2_enable(bsp_state[2]);
263 reg = mpc745x_l1d_enable();
264 reg = mpc745x_l1i_enable();
265
266 break;
267 default:
268 printf("WARNING: Unknown CPU type. Cache performace may be "
269 "suboptimal.\n");
270 break;
271 }
185}
186
272}
273