1 /*- 2 * Copyright (c) 2008 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/bus.h> 34 #include <sys/pcpu.h> 35 #include <sys/proc.h> 36 #include <sys/smp.h> 37 38 #include <machine/bus.h> 39 #include <machine/cpu.h> 40 #include <machine/hid.h> 41 #include <machine/intr_machdep.h> 42 #include <machine/pcb.h> 43 #include <machine/psl.h> 44 #include <machine/smp.h> 45 #include <machine/spr.h> 46 #include <machine/trap_aim.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <machine/ofw_machdep.h> 50 51 extern void *rstcode; 52 extern register_t l2cr_config; 53 extern register_t l3cr_config; 54 55 void *ap_pcpu; 56 57 static register_t 58 l2_enable(void) 59 { 60 register_t ccr; 61 62 ccr = mfspr(SPR_L2CR); 63 if (ccr & L2CR_L2E) 64 return (ccr); 65 66 /* Configure L2 cache. */ 67 ccr = l2cr_config & ~L2CR_L2E; 68 mtspr(SPR_L2CR, ccr | L2CR_L2I); 69 do { 70 ccr = mfspr(SPR_L2CR); 71 } while (ccr & L2CR_L2I); 72 powerpc_sync(); 73 mtspr(SPR_L2CR, l2cr_config); 74 powerpc_sync(); 75 76 return (l2cr_config); 77 } 78 79 static register_t 80 l3_enable(void) 81 { 82 register_t ccr; 83 84 ccr = mfspr(SPR_L3CR); 85 if (ccr & L3CR_L3E) 86 return (ccr); 87 88 /* Configure L3 cache. */ 89 ccr = l3cr_config & ~(L3CR_L3E | L3CR_L3I | L3CR_L3PE | L3CR_L3CLKEN); 90 mtspr(SPR_L3CR, ccr); 91 ccr |= 0x4000000; /* Magic, but documented. */ 92 mtspr(SPR_L3CR, ccr); 93 ccr |= L3CR_L3CLKEN; 94 mtspr(SPR_L3CR, ccr); 95 mtspr(SPR_L3CR, ccr | L3CR_L3I); 96 while (mfspr(SPR_L3CR) & L3CR_L3I) 97 ; 98 mtspr(SPR_L3CR, ccr & ~L3CR_L3CLKEN); 99 powerpc_sync(); 100 DELAY(100); 101 mtspr(SPR_L3CR, ccr); 102 powerpc_sync(); 103 DELAY(100); 104 ccr |= L3CR_L3E; 105 mtspr(SPR_L3CR, ccr); 106 powerpc_sync(); 107 108 return(ccr); 109 } 110 111 static register_t 112 l1d_enable(void) 113 { 114 register_t hid; 115 116 hid = mfspr(SPR_HID0); 117 if (hid & HID0_DCE) 118 return (hid); 119 120 /* Enable L1 D-cache */ 121 hid |= HID0_DCE; 122 powerpc_sync(); 123 mtspr(SPR_HID0, hid | HID0_DCFI); 124 powerpc_sync(); 125 126 return (hid); 127 } 128 129 static register_t 130 l1i_enable(void) 131 { 132 register_t hid; 133 134 hid = mfspr(SPR_HID0); 135 if (hid & HID0_ICE) 136 return (hid); 137 138 /* Enable L1 I-cache */ 139 hid |= HID0_ICE; 140 isync(); 141 mtspr(SPR_HID0, hid | HID0_ICFI); 142 isync(); 143 144 return (hid); 145 } 146 147 uint32_t 148 cpudep_ap_bootstrap(void) 149 { 150 uint32_t hid, msr, reg, sp; 151 152 // reg = mfspr(SPR_MSSCR0); 153 // mtspr(SPR_MSSCR0, reg | 0x3); 154 155 __asm __volatile("mtsprg 0, %0" :: "r"(ap_pcpu)); 156 powerpc_sync(); 157 158 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid))); 159 __asm __volatile("mfspr %0,1023" : "=r"(pcpup->pc_pir)); 160 161 msr = PSL_FP | PSL_IR | PSL_DR | PSL_ME | PSL_RI; 162 powerpc_sync(); 163 isync(); 164 mtmsr(msr); 165 isync(); 166 167 if (l3cr_config != 0) 168 reg = l3_enable(); 169 if (l2cr_config != 0) 170 reg = l2_enable(); 171 reg = l1d_enable(); 172 reg = l1i_enable(); 173 174 hid = mfspr(SPR_HID0); 175 hid &= ~(HID0_DOZE | HID0_SLEEP); 176 hid |= HID0_NAP | HID0_DPM; 177 mtspr(SPR_HID0, hid); 178 isync(); 179 180 pcpup->pc_curthread = pcpup->pc_idlethread; 181 pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb; 182 sp = pcpup->pc_curpcb->pcb_sp; 183 184 return (sp); 185 } 186 187