uart_bus.h (874108aed99d76099ff9eb6c8d830479a504c1ad) uart_bus.h (27d5dc189c8e2eaf1cbe7e47078bf065854ba210)
1/*-
1/*
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright

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24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#ifndef _DEV_UART_BUS_H_
30#define _DEV_UART_BUS_H_
31
2 * Copyright (c) 2003 Marcel Moolenaar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright

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24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#ifndef _DEV_UART_BUS_H_
30#define _DEV_UART_BUS_H_
31
32#ifndef KLD_MODULE
33#include "opt_uart.h"
34#endif
35
36#include <sys/serial.h>
37#include <sys/timepps.h>
38
39/* Drain and flush targets. */
40#define UART_DRAIN_RECEIVER 0x0001
41#define UART_DRAIN_TRANSMITTER 0x0002
42#define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER
43#define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER
44
32/* Drain and flush targets. */
33#define UART_DRAIN_RECEIVER 0x0001
34#define UART_DRAIN_TRANSMITTER 0x0002
35#define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER
36#define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER
37
38/*
39 * Interrupt sources (in priority order). See also uart_core.c
40 * Note that the low order 16 bits are used to pass modem signals
41 * from the hardware interrupt handler to the software interrupt
42 * handler. See UART_SIG_* and UART_SIGMASK_* below.
43 */
44#define UART_IPEND_OVERRUN 0x010000
45#define UART_IPEND_BREAK 0x020000
46#define UART_IPEND_RXREADY 0x040000
47#define UART_IPEND_SIGCHG 0x080000
48#define UART_IPEND_TXIDLE 0x100000
49
50#define UART_IPEND_MASK 0x1f0000
51#define UART_IPEND_SIGMASK 0x00ffff
52
45/* Received character status bits. */
46#define UART_STAT_BREAK 0x0100
47#define UART_STAT_FRAMERR 0x0200
48#define UART_STAT_OVERRUN 0x0400
49#define UART_STAT_PARERR 0x0800
50
53/* Received character status bits. */
54#define UART_STAT_BREAK 0x0100
55#define UART_STAT_FRAMERR 0x0200
56#define UART_STAT_OVERRUN 0x0400
57#define UART_STAT_PARERR 0x0800
58
51#ifdef UART_PPS_ON_CTS
52#define UART_SIG_DPPS SER_DCTS
53#define UART_SIG_PPS SER_CTS
54#else
55#define UART_SIG_DPPS SER_DDCD
56#define UART_SIG_PPS SER_DCD
57#endif
59/* Modem and line signals. */
60#define UART_SIG_DTR 0x0001
61#define UART_SIG_RTS 0x0002
62#define UART_SIG_DSR 0x0004
63#define UART_SIG_CTS 0x0008
64#define UART_SIG_DCD 0x0010
65#define UART_SIG_RI 0x0020
66#define UART_SIG_DDTR 0x0100
67#define UART_SIG_DRTS 0x0200
68#define UART_SIG_DDSR 0x0400
69#define UART_SIG_DCTS 0x0800
70#define UART_SIG_DDCD 0x1000
71#define UART_SIG_DRI 0x2000
58
72
73#define UART_SIGMASK_DTE 0x0003
74#define UART_SIGMASK_DCE 0x003c
75#define UART_SIGMASK_STATE 0x003f
76#define UART_SIGMASK_DELTA 0x3f00
77
59/* UART_IOCTL() requests */
60#define UART_IOCTL_BREAK 1
61#define UART_IOCTL_IFLOW 2
62#define UART_IOCTL_OFLOW 3
78/* UART_IOCTL() requests */
79#define UART_IOCTL_BREAK 1
80#define UART_IOCTL_IFLOW 2
81#define UART_IOCTL_OFLOW 3
63#define UART_IOCTL_BAUD 4
64
65/*
66 * UART class & instance (=softc)
67 */
68struct uart_class {
69 KOBJ_CLASS_FIELDS;
82
83/*
84 * UART class & instance (=softc)
85 */
86struct uart_class {
87 KOBJ_CLASS_FIELDS;
70 struct uart_ops *uc_ops; /* Low-level console operations. */
71 u_int uc_range; /* Bus space address range. */
72 u_int uc_rclk; /* Default rclk for this device. */
73};
74
88 u_int uc_range; /* Bus space address range. */
89 u_int uc_rclk; /* Default rclk for this device. */
90};
91
92extern struct uart_class uart_ns8250_class;
93extern struct uart_class uart_sab82532_class;
94extern struct uart_class uart_z8530_class;
95
75struct uart_softc {
76 KOBJ_FIELDS;
77 struct uart_class *sc_class;
78 struct uart_bas sc_bas;
79 device_t sc_dev;
80
96struct uart_softc {
97 KOBJ_FIELDS;
98 struct uart_class *sc_class;
99 struct uart_bas sc_bas;
100 device_t sc_dev;
101
81 struct mtx sc_hwmtx_s; /* Spinlock protecting hardware. */
82 struct mtx *sc_hwmtx;
83
84 struct resource *sc_rres; /* Register resource. */
85 int sc_rrid;
86 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */
87 struct resource *sc_ires; /* Interrupt resource. */
88 void *sc_icookie;
89 int sc_irid;
90
91 int sc_callout:1; /* This UART is opened for callout. */
92 int sc_fastintr:1; /* This UART uses fast interrupts. */
102 struct resource *sc_rres; /* Register resource. */
103 int sc_rrid;
104 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */
105 struct resource *sc_ires; /* Interrupt resource. */
106 void *sc_icookie;
107 int sc_irid;
108
109 int sc_callout:1; /* This UART is opened for callout. */
110 int sc_fastintr:1; /* This UART uses fast interrupts. */
111 int sc_hasfifo:1; /* This UART has FIFOs. */
93 int sc_hwiflow:1; /* This UART has HW input flow ctl. */
94 int sc_hwoflow:1; /* This UART has HW output flow ctl. */
95 int sc_leaving:1; /* This UART is going away. */
96 int sc_opened:1; /* This UART is open for business. */
97 int sc_polled:1; /* This UART has no interrupts. */
98 int sc_txbusy:1; /* This UART is transmitting. */
112 int sc_hwiflow:1; /* This UART has HW input flow ctl. */
113 int sc_hwoflow:1; /* This UART has HW output flow ctl. */
114 int sc_leaving:1; /* This UART is going away. */
115 int sc_opened:1; /* This UART is open for business. */
116 int sc_polled:1; /* This UART has no interrupts. */
117 int sc_txbusy:1; /* This UART is transmitting. */
99 int sc_isquelch:1; /* This UART has input squelched. */
100
101 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */
102
103 int sc_altbrk; /* State for alt break sequence. */
104 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */
105
106 /* Receiver data. */
107 uint16_t *sc_rxbuf;
108 int sc_rxbufsz;
109 int sc_rxput;
110 int sc_rxget;
111 int sc_rxfifosz; /* Size of RX FIFO. */
112
113 /* Transmitter data. */
114 uint8_t *sc_txbuf;
115 int sc_txdatasz;
116 int sc_txfifosz; /* Size of TX FIFO and buffer. */
117
118
119 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */
120
121 int sc_altbrk; /* State for alt break sequence. */
122 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */
123
124 /* Receiver data. */
125 uint16_t *sc_rxbuf;
126 int sc_rxbufsz;
127 int sc_rxput;
128 int sc_rxget;
129 int sc_rxfifosz; /* Size of RX FIFO. */
130
131 /* Transmitter data. */
132 uint8_t *sc_txbuf;
133 int sc_txdatasz;
134 int sc_txfifosz; /* Size of TX FIFO and buffer. */
135
118 /* Pulse capturing support (PPS). */
119 struct pps_state sc_pps;
120
121 /* Upper layer data. */
122 void *sc_softih;
123 uint32_t sc_ttypend;
124 union {
125 /* TTY specific data. */
126 struct {
136 /* Upper layer data. */
137 void *sc_softih;
138 uint32_t sc_ttypend;
139 union {
140 /* TTY specific data. */
141 struct {
142 dev_t si[2]; /* We have 2 device special files. */
127 struct tty *tp;
128 } u_tty;
129 /* Keyboard specific data. */
130 struct {
131 } u_kbd;
132 } sc_u;
133};
134
135extern devclass_t uart_devclass;
136extern char uart_driver_name[];
137
138int uart_bus_attach(device_t dev);
139int uart_bus_detach(device_t dev);
143 struct tty *tp;
144 } u_tty;
145 /* Keyboard specific data. */
146 struct {
147 } u_kbd;
148 } sc_u;
149};
150
151extern devclass_t uart_devclass;
152extern char uart_driver_name[];
153
154int uart_bus_attach(device_t dev);
155int uart_bus_detach(device_t dev);
140serdev_intr_t *uart_bus_ihand(device_t dev, int ipend);
141int uart_bus_ipend(device_t dev);
142int uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan);
143int uart_bus_sysdev(device_t dev);
156int uart_bus_probe(device_t dev, int regshft, int rclk, int rid);
144
157
145void uart_sched_softih(struct uart_softc *, uint32_t);
146
147int uart_tty_attach(struct uart_softc *);
148int uart_tty_detach(struct uart_softc *);
149void uart_tty_intr(void *arg);
150
151/*
152 * Receive buffer operations.
153 */
154static __inline int

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173 if (ptr == sc->sc_rxput)
174 return (-1);
175 xc = sc->sc_rxbuf[ptr++];
176 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
177 return (xc);
178}
179
180static __inline int
158int uart_tty_attach(struct uart_softc *);
159int uart_tty_detach(struct uart_softc *);
160void uart_tty_intr(void *arg);
161
162/*
163 * Receive buffer operations.
164 */
165static __inline int

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184 if (ptr == sc->sc_rxput)
185 return (-1);
186 xc = sc->sc_rxbuf[ptr++];
187 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
188 return (xc);
189}
190
191static __inline int
181uart_rx_next(struct uart_softc *sc)
182{
183 int ptr;
184
185 ptr = sc->sc_rxget;
186 if (ptr == sc->sc_rxput)
187 return (-1);
188 ptr += 1;
189 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0;
190 return (0);
191}
192
193static __inline int
194uart_rx_peek(struct uart_softc *sc)
195{
196 int ptr;
197
198 ptr = sc->sc_rxget;
199 return ((ptr == sc->sc_rxput) ? -1 : sc->sc_rxbuf[ptr]);
200}
201
202static __inline int
203uart_rx_put(struct uart_softc *sc, int xc)
204{
205 int ptr;
206
207 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0;
208 if (ptr == sc->sc_rxget)
209 return (ENOSPC);
210 sc->sc_rxbuf[sc->sc_rxput] = xc;
211 sc->sc_rxput = ptr;
212 return (0);
213}
214
215#endif /* _DEV_UART_BUS_H_ */
192uart_rx_put(struct uart_softc *sc, int xc)
193{
194 int ptr;
195
196 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0;
197 if (ptr == sc->sc_rxget)
198 return (ENOSPC);
199 sc->sc_rxbuf[sc->sc_rxput] = xc;
200 sc->sc_rxput = ptr;
201 return (0);
202}
203
204#endif /* _DEV_UART_BUS_H_ */