1 /* 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _DEV_UART_BUS_H_ 30 #define _DEV_UART_BUS_H_ 31 32 /* Drain and flush targets. */ 33 #define UART_DRAIN_RECEIVER 0x0001 34 #define UART_DRAIN_TRANSMITTER 0x0002 35 #define UART_FLUSH_RECEIVER UART_DRAIN_RECEIVER 36 #define UART_FLUSH_TRANSMITTER UART_DRAIN_TRANSMITTER 37 38 /* 39 * Interrupt sources (in priority order). See also uart_core.c 40 * Note that the low order 16 bits are used to pass modem signals 41 * from the hardware interrupt handler to the software interrupt 42 * handler. See UART_SIG_* and UART_SIGMASK_* below. 43 */ 44 #define UART_IPEND_OVERRUN 0x010000 45 #define UART_IPEND_BREAK 0x020000 46 #define UART_IPEND_RXREADY 0x040000 47 #define UART_IPEND_SIGCHG 0x080000 48 #define UART_IPEND_TXIDLE 0x100000 49 50 #define UART_IPEND_MASK 0x1f0000 51 #define UART_IPEND_SIGMASK 0x00ffff 52 53 /* Received character status bits. */ 54 #define UART_STAT_BREAK 0x0100 55 #define UART_STAT_FRAMERR 0x0200 56 #define UART_STAT_OVERRUN 0x0400 57 #define UART_STAT_PARERR 0x0800 58 59 /* Modem and line signals. */ 60 #define UART_SIG_DTR 0x0001 61 #define UART_SIG_RTS 0x0002 62 #define UART_SIG_DSR 0x0004 63 #define UART_SIG_CTS 0x0008 64 #define UART_SIG_DCD 0x0010 65 #define UART_SIG_RI 0x0020 66 #define UART_SIG_DDTR 0x0100 67 #define UART_SIG_DRTS 0x0200 68 #define UART_SIG_DDSR 0x0400 69 #define UART_SIG_DCTS 0x0800 70 #define UART_SIG_DDCD 0x1000 71 #define UART_SIG_DRI 0x2000 72 73 #define UART_SIGMASK_DTE 0x0003 74 #define UART_SIGMASK_DCE 0x003c 75 #define UART_SIGMASK_STATE 0x003f 76 #define UART_SIGMASK_DELTA 0x3f00 77 78 /* UART_IOCTL() requests */ 79 #define UART_IOCTL_BREAK 1 80 #define UART_IOCTL_IFLOW 2 81 #define UART_IOCTL_OFLOW 3 82 83 /* 84 * UART class & instance (=softc) 85 */ 86 struct uart_class { 87 KOBJ_CLASS_FIELDS; 88 u_int uc_range; /* Bus space address range. */ 89 u_int uc_rclk; /* Default rclk for this device. */ 90 }; 91 92 extern struct uart_class uart_ns8250_class; 93 extern struct uart_class uart_sab82532_class; 94 extern struct uart_class uart_z8530_class; 95 96 struct uart_softc { 97 KOBJ_FIELDS; 98 struct uart_class *sc_class; 99 struct uart_bas sc_bas; 100 device_t sc_dev; 101 102 struct resource *sc_rres; /* Register resource. */ 103 int sc_rrid; 104 int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */ 105 struct resource *sc_ires; /* Interrupt resource. */ 106 void *sc_icookie; 107 int sc_irid; 108 109 int sc_callout:1; /* This UART is opened for callout. */ 110 int sc_fastintr:1; /* This UART uses fast interrupts. */ 111 int sc_hasfifo:1; /* This UART has FIFOs. */ 112 int sc_hwiflow:1; /* This UART has HW input flow ctl. */ 113 int sc_hwoflow:1; /* This UART has HW output flow ctl. */ 114 int sc_leaving:1; /* This UART is going away. */ 115 int sc_opened:1; /* This UART is open for business. */ 116 int sc_polled:1; /* This UART has no interrupts. */ 117 int sc_txbusy:1; /* This UART is transmitting. */ 118 119 struct uart_devinfo *sc_sysdev; /* System device (or NULL). */ 120 121 int sc_altbrk; /* State for alt break sequence. */ 122 uint32_t sc_hwsig; /* Signal state. Used by HW driver. */ 123 124 /* Receiver data. */ 125 uint16_t *sc_rxbuf; 126 int sc_rxbufsz; 127 int sc_rxput; 128 int sc_rxget; 129 int sc_rxfifosz; /* Size of RX FIFO. */ 130 131 /* Transmitter data. */ 132 uint8_t *sc_txbuf; 133 int sc_txdatasz; 134 int sc_txfifosz; /* Size of TX FIFO and buffer. */ 135 136 /* Upper layer data. */ 137 void *sc_softih; 138 uint32_t sc_ttypend; 139 union { 140 /* TTY specific data. */ 141 struct { 142 dev_t si[2]; /* We have 2 device special files. */ 143 struct tty *tp; 144 } u_tty; 145 /* Keyboard specific data. */ 146 struct { 147 } u_kbd; 148 } sc_u; 149 }; 150 151 extern devclass_t uart_devclass; 152 extern char uart_driver_name[]; 153 154 int uart_bus_attach(device_t dev); 155 int uart_bus_detach(device_t dev); 156 int uart_bus_probe(device_t dev, int regshft, int rclk, int rid); 157 158 int uart_tty_attach(struct uart_softc *); 159 int uart_tty_detach(struct uart_softc *); 160 void uart_tty_intr(void *arg); 161 162 /* 163 * Receive buffer operations. 164 */ 165 static __inline int 166 uart_rx_empty(struct uart_softc *sc) 167 { 168 return ((sc->sc_rxget == sc->sc_rxput) ? 1 : 0); 169 } 170 171 static __inline int 172 uart_rx_full(struct uart_softc *sc) 173 { 174 return ((sc->sc_rxput + 1 < sc->sc_rxbufsz) 175 ? (sc->sc_rxput + 1 == sc->sc_rxget) : (sc->sc_rxget == 0)); 176 } 177 178 static __inline int 179 uart_rx_get(struct uart_softc *sc) 180 { 181 int ptr, xc; 182 183 ptr = sc->sc_rxget; 184 if (ptr == sc->sc_rxput) 185 return (-1); 186 xc = sc->sc_rxbuf[ptr++]; 187 sc->sc_rxget = (ptr < sc->sc_rxbufsz) ? ptr : 0; 188 return (xc); 189 } 190 191 static __inline int 192 uart_rx_put(struct uart_softc *sc, int xc) 193 { 194 int ptr; 195 196 ptr = (sc->sc_rxput + 1 < sc->sc_rxbufsz) ? sc->sc_rxput + 1 : 0; 197 if (ptr == sc->sc_rxget) 198 return (ENOSPC); 199 sc->sc_rxbuf[sc->sc_rxput] = xc; 200 sc->sc_rxput = ptr; 201 return (0); 202 } 203 204 #endif /* _DEV_UART_BUS_H_ */ 205