nctgpio.c (7f8d2ed03bc670393d7a8322b0681f46ead745e7) nctgpio.c (8e6ea10c31220b5f56dbd966a0ee7163d46d30d1)
1/*-
2 * Copyright (c) 2016 Daniel Wyatt <Daniel.Wyatt@gmail.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 137 unchanged lines hidden (view full) ---

146struct nct_device {
147 uint16_t devid;
148 int extid;
149 const char *descr;
150 int ngroups;
151 struct nct_gpio_group groups[NCT_MAX_GROUP + 1];
152} nct_devices[] = {
153 {
1/*-
2 * Copyright (c) 2016 Daniel Wyatt <Daniel.Wyatt@gmail.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 137 unchanged lines hidden (view full) ---

146struct nct_device {
147 uint16_t devid;
148 int extid;
149 const char *descr;
150 int ngroups;
151 struct nct_gpio_group groups[NCT_MAX_GROUP + 1];
152} nct_devices[] = {
153 {
154 .devid = 0xa025,
155 .descr = "GPIO on Winbond 83627DHG IC ver. 5",
156 .ngroups = 5,
157 .groups = {
158 {
159 .grpnum = 2,
160 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
161 .enable_ldn = 0x09,
162 .enable_reg = 0x30,
163 .enable_mask = 0x01,
164 .data_ldn = 0x09,
165 .ppod_reg = 0xe0, /* FIXME Need to check for this group. */
166 .caps = NCT_GPIO_CAPS,
167 .npins = 8,
168 .iobase = 0xe3,
169 },
170 {
171 .grpnum = 3,
172 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
173 .enable_ldn = 0x09,
174 .enable_reg = 0x30,
175 .enable_mask = 0x02,
176 .data_ldn = 0x09,
177 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
178 .caps = NCT_GPIO_CAPS,
179 .npins = 8,
180 .iobase = 0xf0,
181 },
182 {
183 .grpnum = 4,
184 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
185 .enable_ldn = 0x09,
186 .enable_reg = 0x30,
187 .enable_mask = 0x04,
188 .data_ldn = 0x09,
189 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
190 .caps = NCT_GPIO_CAPS,
191 .npins = 8,
192 .iobase = 0xf4,
193 },
194 {
195 .grpnum = 5,
196 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
197 .enable_ldn = 0x09,
198 .enable_reg = 0x30,
199 .enable_mask = 0x08,
200 .data_ldn = 0x09,
201 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
202 .caps = NCT_GPIO_CAPS,
203 .npins = 8,
204 .iobase = 0xe0,
205 },
206 {
207 .grpnum = 6,
208 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
209 .enable_ldn = 0x07,
210 .enable_reg = 0x30,
211 .enable_mask = 0x01,
212 .data_ldn = 0x07,
213 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
214 .caps = NCT_GPIO_CAPS,
215 .npins = 8,
216 .iobase = 0xf4,
217 },
218 },
219 },
220 {
154 .devid = 0x1061,
155 .descr = "GPIO on Nuvoton NCT5104D",
156 .ngroups = 2,
157 .groups = {
158 {
159 .grpnum = 0,
160 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
161 .enable_ldn = 0x07,

--- 15 unchanged lines hidden (view full) ---

177 .ppod_reg = 0xe1,
178 .caps = NCT_GPIO_CAPS,
179 .npins = 8,
180 .iobase = 0xe4,
181 },
182 },
183 },
184 {
221 .devid = 0x1061,
222 .descr = "GPIO on Nuvoton NCT5104D",
223 .ngroups = 2,
224 .groups = {
225 {
226 .grpnum = 0,
227 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
228 .enable_ldn = 0x07,

--- 15 unchanged lines hidden (view full) ---

244 .ppod_reg = 0xe1,
245 .caps = NCT_GPIO_CAPS,
246 .npins = 8,
247 .iobase = 0xe4,
248 },
249 },
250 },
251 {
185 .devid = 0xc452,
252 .devid = 0xc452, /* FIXME Conflict with Nuvoton NCT6106D. See NetBSD's nct_match. */
186 .descr = "GPIO on Nuvoton NCT5104D (PC-Engines APU)",
187 .ngroups = 2,
188 .groups = {
189 {
190 .grpnum = 0,
191 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
192 .enable_ldn = 0x07,
193 .enable_reg = 0x30,

--- 44 unchanged lines hidden (view full) ---

238 .data_ldn = 0x07,
239 .ppod_reg = 0xe1,
240 .caps = NCT_GPIO_CAPS,
241 .npins = 8,
242 .iobase = 0xe4,
243 },
244 },
245 },
253 .descr = "GPIO on Nuvoton NCT5104D (PC-Engines APU)",
254 .ngroups = 2,
255 .groups = {
256 {
257 .grpnum = 0,
258 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
259 .enable_ldn = 0x07,
260 .enable_reg = 0x30,

--- 44 unchanged lines hidden (view full) ---

305 .data_ldn = 0x07,
306 .ppod_reg = 0xe1,
307 .caps = NCT_GPIO_CAPS,
308 .npins = 8,
309 .iobase = 0xe4,
310 },
311 },
312 },
313 {
314 .devid = 0xd42a,
315 .extid = 1,
316 .descr = "GPIO on Nuvoton NCT6796D-E",
317 .ngroups = 10,
318 .groups = {
319 {
320 .grpnum = 0,
321 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
322 .enable_ldn = 0x08,
323 .enable_reg = 0x30,
324 .enable_mask = 0x02,
325 .data_ldn = 0x08,
326 .ppod_reg = 0xe0, /* FIXME Need to check for this group. */
327 .caps = NCT_GPIO_CAPS,
328 .npins = 8,
329 .iobase = 0xe0,
330 },
331 {
332 .grpnum = 1,
333 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
334 .enable_ldn = 0x08,
335 .enable_reg = 0x30,
336 .enable_mask = 0x80,
337 .data_ldn = 0x08,
338 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
339 .caps = NCT_GPIO_CAPS,
340 .npins = 8,
341 .iobase = 0xf0,
342 },
343 {
344 .grpnum = 2,
345 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
346 .enable_ldn = 0x09,
347 .enable_reg = 0x30,
348 .enable_mask = 0x01,
349 .data_ldn = 0x09,
350 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
351 .caps = NCT_GPIO_CAPS,
352 .npins = 8,
353 .iobase = 0xe0,
354 },
355 {
356 .grpnum = 3,
357 .pinbits = { 0, 1, 2, 3, 4, 5, 6 },
358 .enable_ldn = 0x09,
359 .enable_reg = 0x30,
360 .enable_mask = 0x02,
361 .data_ldn = 0x09,
362 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
363 .caps = NCT_GPIO_CAPS,
364 .npins = 7,
365 .iobase = 0xe4,
366 },
367 {
368 .grpnum = 4,
369 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
370 .enable_ldn = 0x09,
371 .enable_reg = 0x30,
372 .enable_mask = 0x04,
373 .data_ldn = 0x09,
374 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
375 .caps = NCT_GPIO_CAPS,
376 .npins = 8,
377 .iobase = 0xf0, /* FIXME Page 344 say "F0~F2, E8",
378 not "F0~F3". */
379 },
380 {
381 .grpnum = 5,
382 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
383 .enable_ldn = 0x09,
384 .enable_reg = 0x30,
385 .enable_mask = 0x08,
386 .data_ldn = 0x09,
387 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
388 .caps = NCT_GPIO_CAPS,
389 .npins = 8,
390 .iobase = 0xf4,
391 },
392 {
393 .grpnum = 6,
394 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
395 .enable_ldn = 0x07,
396 .enable_reg = 0x30,
397 .enable_mask = 0x01,
398 .data_ldn = 0x07,
399 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
400 .caps = NCT_GPIO_CAPS,
401 .npins = 8,
402 .iobase = 0xf4,
403 },
404 {
405 .grpnum = 7,
406 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
407 .enable_ldn = 0x07,
408 .enable_reg = 0x30,
409 .enable_mask = 0x02,
410 .data_ldn = 0x07,
411 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
412 .caps = NCT_GPIO_CAPS,
413 .npins = 8,
414 .iobase = 0xe0,
415 },
416 {
417 .grpnum = 8,
418 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
419 .enable_ldn = 0x07,
420 .enable_reg = 0x30,
421 .enable_mask = 0x04,
422 .data_ldn = 0x07,
423 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
424 .caps = NCT_GPIO_CAPS,
425 .npins = 8,
426 .iobase = 0xe4,
427 },
428 {
429 .grpnum = 9,
430 .pinbits = { 0, 1, 2, 3 },
431 .enable_ldn = 0x07,
432 .enable_reg = 0x30,
433 .enable_mask = 0x08,
434 .data_ldn = 0x07,
435 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
436 .caps = NCT_GPIO_CAPS,
437 .npins = 4,
438 .iobase = 0xe8,
439 },
440 },
441 },
442 {
443 .devid = 0xd42a,
444 .extid = 2,
445 .descr = "GPIO on Nuvoton NCT5585D",
446 .ngroups = 6,
447 .groups = {
448 {
449 .grpnum = 2,
450 .pinbits = { 0, 1, 2, 3, 4, 5, 6 },
451 .enable_ldn = 0x09,
452 .enable_reg = 0x30,
453 .enable_mask = 0x01,
454 .data_ldn = 0x09,
455 .ppod_reg = 0xe1,
456 .caps = NCT_GPIO_CAPS,
457 .npins = 7,
458 .iobase = 0xe0,
459 },
460 {
461 .grpnum = 3,
462 .pinbits = { 1, 2, 3 },
463 .enable_ldn = 0x09,
464 .enable_reg = 0x30,
465 .enable_mask = 0x02,
466 .data_ldn = 0x09,
467 .ppod_reg = 0xe2,
468 .caps = NCT_GPIO_CAPS,
469 .npins = 3,
470 .iobase = 0xe4,
471 },
472 {
473 .grpnum = 5,
474 .pinbits = { 0, 2, 6, 7 },
475 .enable_ldn = 0x09,
476 .enable_reg = 0x30,
477 .enable_mask = 0x08,
478 .data_ldn = 0x09,
479 .ppod_reg = 0xe4,
480 .caps = NCT_GPIO_CAPS,
481 .npins = 4,
482 .iobase = 0xf4,
483 },
484 {
485 .grpnum = 7,
486 .pinbits = { 4 },
487 .enable_ldn = 0x07,
488 .enable_reg = 0x30,
489 .enable_mask = 0x02,
490 .data_ldn = 0x07,
491 .ppod_reg = 0xe6,
492 .caps = NCT_GPIO_CAPS,
493 .npins = 1,
494 .iobase = 0xe0,
495 },
496 {
497 .grpnum = 8,
498 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
499 .enable_ldn = 0x07,
500 .enable_reg = 0x30,
501 .enable_mask = 0x04,
502 .data_ldn = 0x07,
503 .ppod_reg = 0xe7,
504 .caps = NCT_GPIO_CAPS,
505 .npins = 8,
506 .iobase = 0xe4,
507 },
508 {
509 .grpnum = 9,
510 .pinbits = { 0, 2 },
511 .enable_ldn = 0x07,
512 .enable_reg = 0x30,
513 .enable_mask = 0x08,
514 .data_ldn = 0x07,
515 .ppod_reg = 0xea,
516 .caps = NCT_GPIO_CAPS,
517 .npins = 2,
518 .iobase = 0xe8,
519 },
520 },
521 },
522 {
523 .devid = 0xc562,
524 .descr = "GPIO on Nuvoton NCT6779D",
525 .ngroups = 9,
526 .groups = {
527 {
528 .grpnum = 0,
529 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
530 .enable_ldn = 0x08,
531 .enable_reg = 0x30,
532 .enable_mask = 0x01,
533 .data_ldn = 0x08,
534 .ppod_reg = 0xe0, /* FIXME Need to check for this group. */
535 .caps = NCT_GPIO_CAPS,
536 .npins = 8,
537 .iobase = 0xe0,
538 },
539 {
540 .grpnum = 1,
541 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
542 .enable_ldn = 0x09,
543 .enable_reg = 0x30,
544 .enable_mask = 0x01,
545 .data_ldn = 0x08,
546 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
547 .caps = NCT_GPIO_CAPS,
548 .npins = 8,
549 .iobase = 0xf0,
550 },
551 {
552 .grpnum = 2,
553 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
554 .enable_ldn = 0x09,
555 .enable_reg = 0x30,
556 .enable_mask = 0x01,
557 .data_ldn = 0x09,
558 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
559 .caps = NCT_GPIO_CAPS,
560 .npins = 8,
561 .iobase = 0xe0,
562 },
563 {
564 .grpnum = 3,
565 .pinbits = { 0, 1, 2, 3, 4, 5, 6 },
566 .enable_ldn = 0x09,
567 .enable_reg = 0x30,
568 .enable_mask = 0x02,
569 .data_ldn = 0x09,
570 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
571 .caps = NCT_GPIO_CAPS,
572 .npins = 7,
573 .iobase = 0xe4,
574 },
575 {
576 .grpnum = 4,
577 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
578 .enable_ldn = 0x09,
579 .enable_reg = 0x30,
580 .enable_mask = 0x04,
581 .data_ldn = 0x09,
582 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
583 .caps = NCT_GPIO_CAPS,
584 .npins = 8,
585 .iobase = 0xf0,
586 },
587 {
588 .grpnum = 5,
589 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
590 .enable_ldn = 0x09,
591 .enable_reg = 0x30,
592 .enable_mask = 0x08,
593 .data_ldn = 0x09,
594 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
595 .caps = NCT_GPIO_CAPS,
596 .npins = 8,
597 .iobase = 0xf4,
598 },
599 {
600 .grpnum = 6,
601 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
602 .enable_ldn = 0x09,
603 .enable_reg = 0x30,
604 .enable_mask = 0x01,
605 .data_ldn = 0x07,
606 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
607 .caps = NCT_GPIO_CAPS,
608 .npins = 8,
609 .iobase = 0xf4,
610 },
611 {
612 .grpnum = 7,
613 .pinbits = { 0, 1, 2, 3, 4, 5, 6 },
614 .enable_ldn = 0x09,
615 .enable_reg = 0x30,
616 .enable_mask = 0x02,
617 .data_ldn = 0x07,
618 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
619 .caps = NCT_GPIO_CAPS,
620 .npins = 7,
621 .iobase = 0xe0,
622 },
623 {
624 .grpnum = 8,
625 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
626 .enable_ldn = 0x09,
627 .enable_reg = 0x30,
628 .enable_mask = 0x04,
629 .data_ldn = 0x07,
630 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
631 .caps = NCT_GPIO_CAPS,
632 .npins = 8,
633 .iobase = 0xe4,
634 },
635 },
636 },
637 {
638 .devid = 0xd282,
639 .descr = "GPIO on Nuvoton NCT6112D/NCT6114D/NCT6116D",
640 .ngroups = 2,
641 .groups = {
642 {
643 .grpnum = 0,
644 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
645 .enable_ldn = 0x07,
646 .enable_reg = 0x30,
647 .enable_mask = 0x01,
648 .data_ldn = 0x07,
649 .ppod_reg = 0xe0, /* FIXME Need to check for this group. */
650 .caps = NCT_GPIO_CAPS,
651 .npins = 8,
652 .iobase = 0xe0,
653 },
654 {
655 .grpnum = 1,
656 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
657 .enable_ldn = 0x07,
658 .enable_reg = 0x30,
659 .enable_mask = 0x02,
660 .data_ldn = 0x07,
661 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
662 .caps = NCT_GPIO_CAPS,
663 .npins = 8,
664 .iobase = 0xe4,
665 },
666 {
667 .grpnum = 2,
668 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
669 .enable_ldn = 0x07,
670 .enable_reg = 0x30,
671 .enable_mask = 0x04,
672 .data_ldn = 0x07,
673 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
674 .caps = NCT_GPIO_CAPS,
675 .npins = 8,
676 .iobase = 0xe8,
677 },
678 {
679 .grpnum = 3,
680 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
681 .enable_ldn = 0x07,
682 .enable_reg = 0x30,
683 .enable_mask = 0x08,
684 .data_ldn = 0x07,
685 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
686 .caps = NCT_GPIO_CAPS,
687 .npins = 8,
688 .iobase = 0xec,
689 },
690 {
691 .grpnum = 4,
692 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
693 .enable_ldn = 0x07,
694 .enable_reg = 0x30,
695 .enable_mask = 0x10,
696 .data_ldn = 0x07,
697 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
698 .caps = NCT_GPIO_CAPS,
699 .npins = 8,
700 .iobase = 0xf0,
701 },
702 {
703 .grpnum = 5,
704 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
705 .enable_ldn = 0x07,
706 .enable_reg = 0x30,
707 .enable_mask = 0x20,
708 .data_ldn = 0x07,
709 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
710 .caps = NCT_GPIO_CAPS,
711 .npins = 8,
712 .iobase = 0xf4,
713 },
714 {
715 .grpnum = 6,
716 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
717 .enable_ldn = 0x07,
718 .enable_reg = 0x30,
719 .enable_mask = 0x40,
720 .data_ldn = 0x07,
721 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
722 .caps = NCT_GPIO_CAPS,
723 .npins = 8,
724 .iobase = 0xf8,
725 },
726 {
727 .grpnum = 7,
728 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
729 .enable_ldn = 0x07,
730 .enable_reg = 0x30,
731 .enable_mask = 0x80,
732 .data_ldn = 0x07,
733 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
734 .caps = NCT_GPIO_CAPS,
735 .npins = 8,
736 .iobase = 0xfc,
737 },
738 {
739 .grpnum = 8,
740 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 },
741 .enable_ldn = 0x09,
742 .enable_reg = 0x30,
743 .enable_mask = 0x01,
744 .data_ldn = 0x09,
745 .ppod_reg = 0xe1, /* FIXME Need to check for this group. */
746 .caps = NCT_GPIO_CAPS,
747 .npins = 8,
748 .iobase = 0xf0,
749 },
750 },
751 },
246};
247
248static const char *
249io2str(uint8_t ioport)
250{
251 switch (ioport) {
252 case NCT_IO_GSR: return ("grpsel");
253 case NCT_IO_IOR: return ("io");

--- 274 unchanged lines hidden (view full) ---

528 sc->cache.out_known[group] |= 1 << bit;
529 if (val)
530 sc->cache.out[group] |= 1 << bit;
531 else
532 sc->cache.out[group] &= ~(1 << bit);
533 return (val);
534}
535
752};
753
754static const char *
755io2str(uint8_t ioport)
756{
757 switch (ioport) {
758 case NCT_IO_GSR: return ("grpsel");
759 case NCT_IO_IOR: return ("io");

--- 274 unchanged lines hidden (view full) ---

1034 sc->cache.out_known[group] |= 1 << bit;
1035 if (val)
1036 sc->cache.out[group] |= 1 << bit;
1037 else
1038 sc->cache.out[group] &= ~(1 << bit);
1039 return (val);
1040}
1041
1042/* FIXME Incorret for NCT5585D and probably other chips. */
536static uint8_t
537nct_ppod_reg(struct nct_softc *sc, uint32_t pin_num)
538{
539 uint8_t group = NCT_PIN_GRPNUM(sc, pin_num);
540
541 return (sc->grpmap[group]->ppod_reg);
542}
543

--- 110 unchanged lines hidden (view full) ---

654 iobase = superio_get_iobase(dev_8);
655 if (iobase != 0 && iobase != 0xffff) {
656 int err;
657
658 NCT_VERBOSE_PRINTF(dev, "iobase %#x\n", iobase);
659 sc->curgrp = -1;
660 sc->iorid = 0;
661 err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid,
1043static uint8_t
1044nct_ppod_reg(struct nct_softc *sc, uint32_t pin_num)
1045{
1046 uint8_t group = NCT_PIN_GRPNUM(sc, pin_num);
1047
1048 return (sc->grpmap[group]->ppod_reg);
1049}
1050

--- 110 unchanged lines hidden (view full) ---

1161 iobase = superio_get_iobase(dev_8);
1162 if (iobase != 0 && iobase != 0xffff) {
1163 int err;
1164
1165 NCT_VERBOSE_PRINTF(dev, "iobase %#x\n", iobase);
1166 sc->curgrp = -1;
1167 sc->iorid = 0;
1168 err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid,
662 iobase, 7);
1169 iobase, 7); /* FIXME NCT6796D-E have 8 registers according to table 18.3. */
663 if (err == 0) {
664 sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
665 &sc->iorid, RF_ACTIVE);
666 if (sc->iores == NULL) {
667 device_printf(dev, "can't map i/o space, "
668 "iobase=%#x\n", iobase);
669 }
670 } else {

--- 343 unchanged lines hidden --- 		1170 if (err == 0) {
1171 sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
1172 &sc->iorid, RF_ACTIVE);
1173 if (sc->iores == NULL) {
1174 device_printf(dev, "can't map i/o space, "
1175 "iobase=%#x\n", iobase);
1176 }
1177 } else {

--- 343 unchanged lines hidden ---