1 /*- 2 * Copyright (c) 2016 Daniel Wyatt <Daniel.Wyatt@gmail.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 /* 31 * Nuvoton GPIO driver. 32 */ 33 34 #include <sys/cdefs.h> 35 36 #include <sys/param.h> 37 #include <sys/kernel.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/eventhandler.h> 41 #include <sys/lock.h> 42 43 #include <sys/module.h> 44 #include <sys/gpio.h> 45 46 #include <machine/bus.h> 47 48 #include <dev/gpio/gpiobusvar.h> 49 #include <dev/superio/superio.h> 50 51 #include "gpio_if.h" 52 53 #define NCT_PPOD_LDN 0xf /* LDN used to select Push-Pull/Open-Drain */ 54 55 /* Direct access through GPIO register table */ 56 #define NCT_IO_GSR 0 /* Group Select */ 57 #define NCT_IO_IOR 1 /* I/O */ 58 #define NCT_IO_DAT 2 /* Data */ 59 #define NCT_IO_INV 3 /* Inversion */ 60 #define NCT_IO_DST 4 /* Status */ 61 62 #define NCT_MAX_GROUP 9 63 #define NCT_MAX_PIN 75 64 65 #define NCT_PIN_IS_VALID(_sc, _p) ((_p) < (_sc)->npins) 66 #define NCT_PIN_GROUP(_sc, _p) ((_sc)->pinmap[(_p)].group) 67 #define NCT_PIN_GRPNUM(_sc, _p) ((_sc)->pinmap[(_p)].grpnum) 68 #define NCT_PIN_BIT(_sc, _p) ((_sc)->pinmap[(_p)].bit) 69 #define NCT_PIN_BITMASK(_p) (1 << ((_p) & 7)) 70 71 #define NCT_GPIO_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 72 GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \ 73 GPIO_PIN_INVIN | GPIO_PIN_INVOUT) 74 75 #define NCT_PREFER_INDIRECT_CHANNEL 2 76 77 #define NCT_VERBOSE_PRINTF(dev, ...) \ 78 do { \ 79 if (__predict_false(bootverbose)) \ 80 device_printf(dev, __VA_ARGS__); \ 81 } while (0) 82 83 /* 84 * Note that the values are important. 85 * They match actual register offsets. 86 */ 87 typedef enum { 88 REG_IOR = 0, 89 REG_DAT = 1, 90 REG_INV = 2, 91 } reg_t; 92 93 struct nct_gpio_group { 94 uint32_t caps; 95 uint8_t enable_ldn; 96 uint8_t enable_reg; 97 uint8_t enable_mask; 98 uint8_t data_ldn; 99 uint8_t iobase; 100 uint8_t ppod_reg; /* Push-Pull/Open-Drain */ 101 uint8_t grpnum; 102 uint8_t pinbits[8]; 103 uint8_t npins; 104 }; 105 106 struct nct_softc { 107 device_t dev; 108 device_t busdev; 109 struct mtx mtx; 110 struct resource *iores; 111 int iorid; 112 int curgrp; 113 struct { 114 uint8_t ior[NCT_MAX_GROUP + 1]; /* direction, 1: input 0: output */ 115 uint8_t out[NCT_MAX_GROUP + 1]; /* output value */ 116 uint8_t out_known[NCT_MAX_GROUP + 1]; /* whether out is valid */ 117 uint8_t inv[NCT_MAX_GROUP + 1]; /* inversion, 1: inverted */ 118 } cache; 119 struct gpio_pin pins[NCT_MAX_PIN + 1]; 120 struct nct_device *nctdevp; 121 int npins; /* Total number of pins */ 122 123 /* Lookup tables */ 124 struct { 125 struct nct_gpio_group *group; 126 uint8_t grpnum; 127 uint8_t bit; 128 } pinmap[NCT_MAX_PIN+1]; 129 struct nct_gpio_group *grpmap[NCT_MAX_GROUP+1]; 130 }; 131 132 #define GPIO_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \ 133 device_get_nameunit(dev), NULL, MTX_DEF) 134 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx) 135 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx) 136 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 137 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED) 138 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED) 139 140 #define GET_BIT(v, b) (((v) >> (b)) & 1) 141 142 /* 143 * For most devices there are several GPIO devices, we attach only to one of 144 * them and use the rest without attaching. 145 */ 146 struct nct_device { 147 uint16_t devid; 148 int extid; 149 const char *descr; 150 int ngroups; 151 struct nct_gpio_group groups[NCT_MAX_GROUP + 1]; 152 } nct_devices[] = { 153 { 154 .devid = 0x1061, 155 .descr = "GPIO on Nuvoton NCT5104D", 156 .ngroups = 2, 157 .groups = { 158 { 159 .grpnum = 0, 160 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, 161 .enable_ldn = 0x07, 162 .enable_reg = 0x30, 163 .enable_mask = 0x01, 164 .data_ldn = 0x07, 165 .ppod_reg = 0xe0, 166 .caps = NCT_GPIO_CAPS, 167 .npins = 8, 168 .iobase = 0xe0, 169 }, 170 { 171 .grpnum = 1, 172 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, 173 .enable_ldn = 0x07, 174 .enable_reg = 0x30, 175 .enable_mask = 0x02, 176 .data_ldn = 0x07, 177 .ppod_reg = 0xe1, 178 .caps = NCT_GPIO_CAPS, 179 .npins = 8, 180 .iobase = 0xe4, 181 }, 182 }, 183 }, 184 { 185 .devid = 0xc452, 186 .descr = "GPIO on Nuvoton NCT5104D (PC-Engines APU)", 187 .ngroups = 2, 188 .groups = { 189 { 190 .grpnum = 0, 191 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, 192 .enable_ldn = 0x07, 193 .enable_reg = 0x30, 194 .enable_mask = 0x01, 195 .data_ldn = 0x07, 196 .ppod_reg = 0xe0, 197 .caps = NCT_GPIO_CAPS, 198 .npins = 8, 199 .iobase = 0xe0, 200 }, 201 { 202 .grpnum = 1, 203 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, 204 .enable_ldn = 0x07, 205 .enable_reg = 0x30, 206 .enable_mask = 0x02, 207 .data_ldn = 0x07, 208 .ppod_reg = 0xe1, 209 .caps = NCT_GPIO_CAPS, 210 .npins = 8, 211 .iobase = 0xe4, 212 }, 213 }, 214 }, 215 { 216 .devid = 0xc453, 217 .descr = "GPIO on Nuvoton NCT5104D (PC-Engines APU3)", 218 .ngroups = 2, 219 .groups = { 220 { 221 .grpnum = 0, 222 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, 223 .enable_ldn = 0x07, 224 .enable_reg = 0x30, 225 .enable_mask = 0x01, 226 .data_ldn = 0x07, 227 .ppod_reg = 0xe0, 228 .caps = NCT_GPIO_CAPS, 229 .npins = 8, 230 .iobase = 0xe0, 231 }, 232 { 233 .grpnum = 1, 234 .pinbits = { 0, 1, 2, 3, 4, 5, 6, 7 }, 235 .enable_ldn = 0x07, 236 .enable_reg = 0x30, 237 .enable_mask = 0x02, 238 .data_ldn = 0x07, 239 .ppod_reg = 0xe1, 240 .caps = NCT_GPIO_CAPS, 241 .npins = 8, 242 .iobase = 0xe4, 243 }, 244 }, 245 }, 246 }; 247 248 static const char * 249 io2str(uint8_t ioport) 250 { 251 switch (ioport) { 252 case NCT_IO_GSR: return ("grpsel"); 253 case NCT_IO_IOR: return ("io"); 254 case NCT_IO_DAT: return ("data"); 255 case NCT_IO_INV: return ("inv"); 256 case NCT_IO_DST: return ("status"); 257 default: return ("?"); 258 } 259 } 260 261 static void 262 nct_io_set_group(struct nct_softc *sc, uint8_t grpnum) 263 { 264 GPIO_ASSERT_LOCKED(sc); 265 266 if (grpnum == sc->curgrp) 267 return; 268 269 NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x ioport %d\n", 270 io2str(NCT_IO_GSR), grpnum, NCT_IO_GSR); 271 bus_write_1(sc->iores, NCT_IO_GSR, grpnum); 272 sc->curgrp = grpnum; 273 } 274 275 static uint8_t 276 nct_io_read(struct nct_softc *sc, uint8_t grpnum, uint8_t reg) 277 { 278 uint8_t val; 279 280 nct_io_set_group(sc, grpnum); 281 282 val = bus_read_1(sc->iores, reg); 283 NCT_VERBOSE_PRINTF(sc->dev, "read %s 0x%x ioport %d\n", 284 io2str(reg), val, reg); 285 return (val); 286 } 287 288 static void 289 nct_io_write(struct nct_softc *sc, uint8_t grpnum, uint8_t reg, uint8_t val) 290 { 291 nct_io_set_group(sc, grpnum); 292 293 NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x ioport %d\n", 294 io2str(reg), val, reg); 295 bus_write_1(sc->iores, reg, val); 296 } 297 298 static uint8_t 299 nct_get_ioreg(struct nct_softc *sc, reg_t reg, uint8_t grpnum) 300 { 301 uint8_t iobase; 302 303 if (sc->iores != NULL) 304 iobase = NCT_IO_IOR; 305 else 306 iobase = sc->grpmap[grpnum]->iobase; 307 return (iobase + reg); 308 } 309 310 static const char * 311 reg2str(reg_t reg) 312 { 313 switch (reg) { 314 case REG_IOR: return ("io"); 315 case REG_DAT: return ("data"); 316 case REG_INV: return ("inv"); 317 default: return ("?"); 318 } 319 } 320 321 static uint8_t 322 nct_read_reg(struct nct_softc *sc, reg_t reg, uint8_t grpnum) 323 { 324 struct nct_gpio_group *gp; 325 uint8_t ioreg; 326 uint8_t val; 327 328 ioreg = nct_get_ioreg(sc, reg, grpnum); 329 330 if (sc->iores != NULL) 331 return (nct_io_read(sc, grpnum, ioreg)); 332 333 gp = sc->grpmap[grpnum]; 334 val = superio_ldn_read(sc->dev, gp->data_ldn, ioreg); 335 NCT_VERBOSE_PRINTF(sc->dev, "read %s 0x%x from group GPIO%u ioreg 0x%x\n", 336 reg2str(reg), val, grpnum, ioreg); 337 return (val); 338 } 339 340 static int 341 nct_get_pin_cache(struct nct_softc *sc, uint32_t pin_num, uint8_t *cache) 342 { 343 uint8_t bit; 344 uint8_t group; 345 uint8_t val; 346 347 KASSERT(NCT_PIN_IS_VALID(sc, pin_num), ("%s: invalid pin number %d", 348 __func__, pin_num)); 349 350 group = NCT_PIN_GRPNUM(sc, pin_num); 351 bit = NCT_PIN_BIT(sc, pin_num); 352 val = cache[group]; 353 return (GET_BIT(val, bit)); 354 } 355 356 static void 357 nct_write_reg(struct nct_softc *sc, reg_t reg, uint8_t grpnum, uint8_t val) 358 { 359 struct nct_gpio_group *gp; 360 uint8_t ioreg; 361 362 ioreg = nct_get_ioreg(sc, reg, grpnum); 363 364 if (sc->iores != NULL) { 365 nct_io_write(sc, grpnum, ioreg, val); 366 return; 367 } 368 369 gp = sc->grpmap[grpnum]; 370 superio_ldn_write(sc->dev, gp->data_ldn, ioreg, val); 371 372 NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x to group GPIO%u ioreg 0x%x\n", 373 reg2str(reg), val, grpnum, ioreg); 374 } 375 376 static void 377 nct_set_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num, bool val) 378 { 379 uint8_t *cache; 380 uint8_t bit; 381 uint8_t bitval; 382 uint8_t group; 383 uint8_t mask; 384 385 KASSERT(NCT_PIN_IS_VALID(sc, pin_num), 386 ("%s: invalid pin number %d", __func__, pin_num)); 387 KASSERT(reg == REG_IOR || reg == REG_INV, 388 ("%s: unsupported register %d", __func__, reg)); 389 390 group = NCT_PIN_GRPNUM(sc, pin_num); 391 bit = NCT_PIN_BIT(sc, pin_num); 392 mask = (uint8_t)1 << bit; 393 bitval = (uint8_t)val << bit; 394 395 if (reg == REG_IOR) 396 cache = &sc->cache.ior[group]; 397 else 398 cache = &sc->cache.inv[group]; 399 if ((*cache & mask) == bitval) 400 return; 401 *cache &= ~mask; 402 *cache |= bitval; 403 nct_write_reg(sc, reg, group, *cache); 404 } 405 406 /* 407 * Set a pin to input (val is true) or output (val is false) mode. 408 */ 409 static void 410 nct_set_pin_input(struct nct_softc *sc, uint32_t pin_num, bool val) 411 { 412 nct_set_pin_reg(sc, REG_IOR, pin_num, val); 413 } 414 415 /* 416 * Check whether a pin is configured as an input. 417 */ 418 static bool 419 nct_pin_is_input(struct nct_softc *sc, uint32_t pin_num) 420 { 421 return (nct_get_pin_cache(sc, pin_num, sc->cache.ior)); 422 } 423 424 /* 425 * Set a pin to inverted (val is true) or normal (val is false) mode. 426 */ 427 static void 428 nct_set_pin_inverted(struct nct_softc *sc, uint32_t pin_num, bool val) 429 { 430 nct_set_pin_reg(sc, REG_INV, pin_num, val); 431 } 432 433 static bool 434 nct_pin_is_inverted(struct nct_softc *sc, uint32_t pin_num) 435 { 436 return (nct_get_pin_cache(sc, pin_num, sc->cache.inv)); 437 } 438 439 /* 440 * Write a value to an output pin. 441 * NB: the hardware remembers last output value across switching from 442 * output mode to input mode and back. 443 * Writes to a pin in input mode are not allowed here as they cannot 444 * have any effect and would corrupt the output value cache. 445 */ 446 static void 447 nct_write_pin(struct nct_softc *sc, uint32_t pin_num, bool val) 448 { 449 uint8_t bit; 450 uint8_t group; 451 452 KASSERT(!nct_pin_is_input(sc, pin_num), ("attempt to write input pin")); 453 group = NCT_PIN_GRPNUM(sc, pin_num); 454 bit = NCT_PIN_BIT(sc, pin_num); 455 456 if (GET_BIT(sc->cache.out_known[group], bit) && 457 GET_BIT(sc->cache.out[group], bit) == val) { 458 /* The pin is already in requested state. */ 459 return; 460 } 461 sc->cache.out_known[group] |= 1 << bit; 462 if (val) 463 sc->cache.out[group] |= 1 << bit; 464 else 465 sc->cache.out[group] &= ~(1 << bit); 466 nct_write_reg(sc, REG_DAT, group, sc->cache.out[group]); 467 } 468 469 static bool 470 nct_get_pin_reg(struct nct_softc *sc, reg_t reg, uint32_t pin_num) 471 { 472 uint8_t bit; 473 uint8_t group; 474 uint8_t val; 475 bool b; 476 477 KASSERT(NCT_PIN_IS_VALID(sc, pin_num), ("%s: invalid pin number %d", 478 __func__, pin_num)); 479 480 group = NCT_PIN_GRPNUM(sc, pin_num); 481 bit = NCT_PIN_BIT(sc, pin_num); 482 val = nct_read_reg(sc, reg, group); 483 b = GET_BIT(val, bit); 484 485 if (__predict_false(bootverbose)) { 486 if (nct_pin_is_input(sc, pin_num)) 487 NCT_VERBOSE_PRINTF(sc->dev, "read %d from input pin %u<GPIO%u%u>\n", 488 b, pin_num, group, bit); 489 else 490 NCT_VERBOSE_PRINTF(sc->dev, 491 "read %d from output pin %u<GPIO%u%u>, cache miss\n", 492 b, pin_num, group, bit); 493 } 494 495 return (b); 496 } 497 498 /* 499 * NB: state of an input pin cannot be cached, of course. 500 * For an output we can either take the value from the cache if it's valid 501 * or read the state from the hadrware and cache it. 502 */ 503 static bool 504 nct_read_pin(struct nct_softc *sc, uint32_t pin_num) 505 { 506 uint8_t bit; 507 uint8_t group; 508 bool val; 509 510 if (nct_pin_is_input(sc, pin_num)) { 511 return (nct_get_pin_reg(sc, REG_DAT, pin_num)); 512 } 513 514 group = NCT_PIN_GRPNUM(sc, pin_num); 515 bit = NCT_PIN_BIT(sc, pin_num); 516 517 if (GET_BIT(sc->cache.out_known[group], bit)) { 518 val = GET_BIT(sc->cache.out[group], bit); 519 520 NCT_VERBOSE_PRINTF(sc->dev, 521 "read %d from output pin %u<GPIO%u%u>, cache hit\n", 522 val, pin_num, group, bit); 523 524 return (val); 525 } 526 527 val = nct_get_pin_reg(sc, REG_DAT, pin_num); 528 sc->cache.out_known[group] |= 1 << bit; 529 if (val) 530 sc->cache.out[group] |= 1 << bit; 531 else 532 sc->cache.out[group] &= ~(1 << bit); 533 return (val); 534 } 535 536 static uint8_t 537 nct_ppod_reg(struct nct_softc *sc, uint32_t pin_num) 538 { 539 uint8_t group = NCT_PIN_GRPNUM(sc, pin_num); 540 541 return (sc->grpmap[group]->ppod_reg); 542 } 543 544 /* 545 * NB: PP/OD can be configured only via configuration registers. 546 * Also, the registers are in a different logical device. 547 * So, this is a special case. No caching too. 548 */ 549 static void 550 nct_set_pin_opendrain(struct nct_softc *sc, uint32_t pin_num) 551 { 552 uint8_t reg; 553 uint8_t outcfg; 554 555 reg = nct_ppod_reg(sc, pin_num); 556 outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg); 557 outcfg |= NCT_PIN_BITMASK(pin_num); 558 superio_ldn_write(sc->dev, 0xf, reg, outcfg); 559 } 560 561 static void 562 nct_set_pin_pushpull(struct nct_softc *sc, uint32_t pin_num) 563 { 564 uint8_t reg; 565 uint8_t outcfg; 566 567 reg = nct_ppod_reg(sc, pin_num); 568 outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg); 569 outcfg &= ~NCT_PIN_BITMASK(pin_num); 570 superio_ldn_write(sc->dev, 0xf, reg, outcfg); 571 } 572 573 static bool 574 nct_pin_is_opendrain(struct nct_softc *sc, uint32_t pin_num) 575 { 576 uint8_t reg; 577 uint8_t outcfg; 578 579 reg = nct_ppod_reg(sc, pin_num); 580 outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg); 581 return (outcfg & NCT_PIN_BITMASK(pin_num)); 582 } 583 584 static struct nct_device * 585 nct_lookup_device(device_t dev) 586 { 587 struct nct_device *nctdevp; 588 uint16_t devid; 589 int i, extid; 590 591 devid = superio_devid(dev); 592 extid = superio_extid(dev); 593 for (i = 0, nctdevp = nct_devices; i < nitems(nct_devices); i++, nctdevp++) { 594 if (devid == nctdevp->devid && nctdevp->extid == extid) 595 return (nctdevp); 596 } 597 return (NULL); 598 } 599 600 static int 601 nct_probe(device_t dev) 602 { 603 struct nct_device *nctdevp; 604 uint8_t ldn; 605 606 ldn = superio_get_ldn(dev); 607 608 if (superio_vendor(dev) != SUPERIO_VENDOR_NUVOTON) { 609 NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not a Nuvoton device\n", ldn); 610 return (ENXIO); 611 } 612 if (superio_get_type(dev) != SUPERIO_DEV_GPIO) { 613 NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not a GPIO device\n", ldn); 614 return (ENXIO); 615 } 616 617 nctdevp = nct_lookup_device(dev); 618 if (nctdevp == NULL) { 619 NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not supported\n", ldn); 620 return (ENXIO); 621 } 622 device_set_desc(dev, nctdevp->descr); 623 return (BUS_PROBE_DEFAULT); 624 } 625 626 static int 627 nct_attach(device_t dev) 628 { 629 struct nct_softc *sc; 630 struct nct_gpio_group *gp; 631 uint32_t pin_num; 632 uint8_t v; 633 int flags, i, g; 634 635 sc = device_get_softc(dev); 636 sc->dev = dev; 637 sc->nctdevp = nct_lookup_device(dev); 638 639 flags = 0; 640 (void)resource_int_value(device_get_name(dev), device_get_unit(dev), "flags", &flags); 641 642 if ((flags & NCT_PREFER_INDIRECT_CHANNEL) == 0) { 643 uint16_t iobase; 644 device_t dev_8; 645 646 /* 647 * As strange as it may seem, I/O port base is configured in the 648 * Logical Device 8 which is primarily used for WDT, but also plays 649 * a role in GPIO configuration. 650 */ 651 iobase = 0; 652 dev_8 = superio_find_dev(device_get_parent(dev), SUPERIO_DEV_WDT, 8); 653 if (dev_8 != NULL) 654 iobase = superio_get_iobase(dev_8); 655 if (iobase != 0 && iobase != 0xffff) { 656 int err; 657 658 NCT_VERBOSE_PRINTF(dev, "iobase %#x\n", iobase); 659 sc->curgrp = -1; 660 sc->iorid = 0; 661 err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid, 662 iobase, 7); 663 if (err == 0) { 664 sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 665 &sc->iorid, RF_ACTIVE); 666 if (sc->iores == NULL) { 667 device_printf(dev, "can't map i/o space, " 668 "iobase=%#x\n", iobase); 669 } 670 } else { 671 device_printf(dev, 672 "failed to set io port resource at %#x\n", iobase); 673 } 674 } 675 } 676 NCT_VERBOSE_PRINTF(dev, "iores %p %s channel\n", 677 sc->iores, (sc->iores ? "direct" : "indirect")); 678 679 /* Enable GPIO groups */ 680 for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) { 681 NCT_VERBOSE_PRINTF(dev, 682 "GPIO%d: %d pins, enable with mask 0x%x via ldn 0x%x reg 0x%x\n", 683 gp->grpnum, gp->npins, gp->enable_mask, gp->enable_ldn, 684 gp->enable_reg); 685 v = superio_ldn_read(dev, gp->enable_ldn, gp->enable_reg); 686 v |= gp->enable_mask; 687 superio_ldn_write(dev, gp->enable_ldn, gp->enable_reg, v); 688 } 689 690 GPIO_LOCK_INIT(sc); 691 GPIO_LOCK(sc); 692 693 pin_num = 0; 694 sc->npins = 0; 695 for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) { 696 sc->npins += gp->npins; 697 for (i = 0; i < gp->npins; i++, pin_num++) { 698 struct gpio_pin *pin; 699 700 sc->pinmap[pin_num].group = gp; 701 sc->pinmap[pin_num].grpnum = gp->grpnum; 702 sc->pinmap[pin_num].bit = gp->pinbits[i]; 703 704 sc->grpmap[gp->grpnum] = gp; 705 706 pin = &sc->pins[pin_num]; 707 pin->gp_pin = pin_num; 708 pin->gp_caps = gp->caps; 709 pin->gp_flags = 0; 710 711 snprintf(pin->gp_name, GPIOMAXNAME, "GPIO%u%u", 712 gp->grpnum, gp->pinbits[i]); 713 714 if (nct_pin_is_input(sc, pin_num)) 715 pin->gp_flags |= GPIO_PIN_INPUT; 716 else 717 pin->gp_flags |= GPIO_PIN_OUTPUT; 718 719 if (nct_pin_is_opendrain(sc, pin_num)) 720 pin->gp_flags |= GPIO_PIN_OPENDRAIN; 721 else 722 pin->gp_flags |= GPIO_PIN_PUSHPULL; 723 724 if (nct_pin_is_inverted(sc, pin_num)) 725 pin->gp_flags |= (GPIO_PIN_INVIN | GPIO_PIN_INVOUT); 726 } 727 } 728 NCT_VERBOSE_PRINTF(dev, "%d pins available\n", sc->npins); 729 730 /* 731 * Caching input values is meaningless as an input can be changed at any 732 * time by an external agent. But outputs are controlled by this 733 * driver, so it can cache their state. Also, the hardware remembers 734 * the output state of a pin when the pin is switched to input mode and 735 * then back to output mode. So, the cache stays valid. 736 * The only problem is with pins that are in input mode at the attach 737 * time. For them the output state is not known until it is set by the 738 * driver for the first time. 739 * 'out' and 'out_known' bits form a tri-state output cache: 740 * |-----+-----------+---------| 741 * | out | out_known | cache | 742 * |-----+-----------+---------| 743 * | X | 0 | invalid | 744 * | 0 | 1 | 0 | 745 * | 1 | 1 | 1 | 746 * |-----+-----------+---------| 747 */ 748 for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) { 749 sc->cache.inv[gp->grpnum] = nct_read_reg(sc, REG_INV, gp->grpnum); 750 sc->cache.ior[gp->grpnum] = nct_read_reg(sc, REG_IOR, gp->grpnum); 751 sc->cache.out[gp->grpnum] = nct_read_reg(sc, REG_DAT, gp->grpnum); 752 sc->cache.out_known[gp->grpnum] = ~sc->cache.ior[gp->grpnum]; 753 } 754 755 GPIO_UNLOCK(sc); 756 757 sc->busdev = gpiobus_attach_bus(dev); 758 if (sc->busdev == NULL) { 759 device_printf(dev, "failed to attach to gpiobus\n"); 760 GPIO_LOCK_DESTROY(sc); 761 return (ENXIO); 762 } 763 764 return (0); 765 } 766 767 static int 768 nct_detach(device_t dev) 769 { 770 struct nct_softc *sc; 771 772 sc = device_get_softc(dev); 773 gpiobus_detach_bus(dev); 774 775 if (sc->iores != NULL) 776 bus_release_resource(dev, SYS_RES_IOPORT, sc->iorid, sc->iores); 777 GPIO_ASSERT_UNLOCKED(sc); 778 GPIO_LOCK_DESTROY(sc); 779 780 return (0); 781 } 782 783 static device_t 784 nct_gpio_get_bus(device_t dev) 785 { 786 struct nct_softc *sc; 787 788 sc = device_get_softc(dev); 789 790 return (sc->busdev); 791 } 792 793 static int 794 nct_gpio_pin_max(device_t dev, int *maxpin) 795 { 796 struct nct_softc *sc; 797 798 sc = device_get_softc(dev); 799 *maxpin = sc->npins - 1; 800 return (0); 801 } 802 803 static int 804 nct_gpio_pin_set(device_t dev, uint32_t pin_num, uint32_t pin_value) 805 { 806 struct nct_softc *sc; 807 808 sc = device_get_softc(dev); 809 810 if (!NCT_PIN_IS_VALID(sc, pin_num)) 811 return (EINVAL); 812 813 GPIO_LOCK(sc); 814 if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) { 815 GPIO_UNLOCK(sc); 816 return (EINVAL); 817 } 818 nct_write_pin(sc, pin_num, pin_value); 819 GPIO_UNLOCK(sc); 820 821 return (0); 822 } 823 824 static int 825 nct_gpio_pin_get(device_t dev, uint32_t pin_num, uint32_t *pin_value) 826 { 827 struct nct_softc *sc; 828 829 sc = device_get_softc(dev); 830 831 if (!NCT_PIN_IS_VALID(sc, pin_num)) 832 return (EINVAL); 833 834 GPIO_ASSERT_UNLOCKED(sc); 835 GPIO_LOCK(sc); 836 *pin_value = nct_read_pin(sc, pin_num); 837 GPIO_UNLOCK(sc); 838 839 return (0); 840 } 841 842 static int 843 nct_gpio_pin_toggle(device_t dev, uint32_t pin_num) 844 { 845 struct nct_softc *sc; 846 847 sc = device_get_softc(dev); 848 849 if (!NCT_PIN_IS_VALID(sc, pin_num)) 850 return (EINVAL); 851 852 GPIO_ASSERT_UNLOCKED(sc); 853 GPIO_LOCK(sc); 854 if ((sc->pins[pin_num].gp_flags & GPIO_PIN_OUTPUT) == 0) { 855 GPIO_UNLOCK(sc); 856 return (EINVAL); 857 } 858 if (nct_read_pin(sc, pin_num)) 859 nct_write_pin(sc, pin_num, 0); 860 else 861 nct_write_pin(sc, pin_num, 1); 862 863 GPIO_UNLOCK(sc); 864 865 return (0); 866 } 867 868 static int 869 nct_gpio_pin_getcaps(device_t dev, uint32_t pin_num, uint32_t *caps) 870 { 871 struct nct_softc *sc; 872 873 sc = device_get_softc(dev); 874 875 if (!NCT_PIN_IS_VALID(sc, pin_num)) 876 return (EINVAL); 877 878 GPIO_ASSERT_UNLOCKED(sc); 879 GPIO_LOCK(sc); 880 *caps = sc->pins[pin_num].gp_caps; 881 GPIO_UNLOCK(sc); 882 883 return (0); 884 } 885 886 static int 887 nct_gpio_pin_getflags(device_t dev, uint32_t pin_num, uint32_t *flags) 888 { 889 struct nct_softc *sc; 890 891 sc = device_get_softc(dev); 892 893 if (!NCT_PIN_IS_VALID(sc, pin_num)) 894 return (EINVAL); 895 896 GPIO_ASSERT_UNLOCKED(sc); 897 GPIO_LOCK(sc); 898 *flags = sc->pins[pin_num].gp_flags; 899 GPIO_UNLOCK(sc); 900 901 return (0); 902 } 903 904 static int 905 nct_gpio_pin_getname(device_t dev, uint32_t pin_num, char *name) 906 { 907 struct nct_softc *sc; 908 909 sc = device_get_softc(dev); 910 911 if (!NCT_PIN_IS_VALID(sc, pin_num)) 912 return (EINVAL); 913 914 GPIO_ASSERT_UNLOCKED(sc); 915 GPIO_LOCK(sc); 916 memcpy(name, sc->pins[pin_num].gp_name, GPIOMAXNAME); 917 GPIO_UNLOCK(sc); 918 919 return (0); 920 } 921 922 static int 923 nct_gpio_pin_setflags(device_t dev, uint32_t pin_num, uint32_t flags) 924 { 925 struct nct_softc *sc; 926 struct gpio_pin *pin; 927 928 sc = device_get_softc(dev); 929 930 if (!NCT_PIN_IS_VALID(sc, pin_num)) 931 return (EINVAL); 932 933 pin = &sc->pins[pin_num]; 934 if ((flags & pin->gp_caps) != flags) 935 return (EINVAL); 936 937 if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == 938 (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { 939 return (EINVAL); 940 } 941 if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) == 942 (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) { 943 return (EINVAL); 944 } 945 if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) == 946 (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) { 947 return (EINVAL); 948 } 949 950 GPIO_ASSERT_UNLOCKED(sc); 951 GPIO_LOCK(sc); 952 953 /* input or output */ 954 if ((flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) != 0) { 955 nct_set_pin_input(sc, pin_num, (flags & GPIO_PIN_INPUT) != 0); 956 pin->gp_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 957 pin->gp_flags |= flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 958 } 959 960 /* invert */ 961 if ((flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT)) != 0) { 962 nct_set_pin_inverted(sc, pin_num, 1); 963 pin->gp_flags |= (GPIO_PIN_INVIN | GPIO_PIN_INVOUT); 964 } else { 965 nct_set_pin_inverted(sc, pin_num, 0); 966 pin->gp_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT); 967 } 968 969 /* Open drain or push pull */ 970 if ((flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL)) != 0) { 971 if (flags & GPIO_PIN_OPENDRAIN) 972 nct_set_pin_opendrain(sc, pin_num); 973 else 974 nct_set_pin_pushpull(sc, pin_num); 975 pin->gp_flags &= ~(GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL); 976 pin->gp_flags |= 977 flags & (GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL); 978 } 979 GPIO_UNLOCK(sc); 980 981 return (0); 982 } 983 984 static device_method_t nct_methods[] = { 985 /* Device interface */ 986 DEVMETHOD(device_probe, nct_probe), 987 DEVMETHOD(device_attach, nct_attach), 988 DEVMETHOD(device_detach, nct_detach), 989 990 /* GPIO */ 991 DEVMETHOD(gpio_get_bus, nct_gpio_get_bus), 992 DEVMETHOD(gpio_pin_max, nct_gpio_pin_max), 993 DEVMETHOD(gpio_pin_get, nct_gpio_pin_get), 994 DEVMETHOD(gpio_pin_set, nct_gpio_pin_set), 995 DEVMETHOD(gpio_pin_toggle, nct_gpio_pin_toggle), 996 DEVMETHOD(gpio_pin_getname, nct_gpio_pin_getname), 997 DEVMETHOD(gpio_pin_getcaps, nct_gpio_pin_getcaps), 998 DEVMETHOD(gpio_pin_getflags, nct_gpio_pin_getflags), 999 DEVMETHOD(gpio_pin_setflags, nct_gpio_pin_setflags), 1000 1001 DEVMETHOD_END 1002 }; 1003 1004 static driver_t nct_driver = { 1005 "gpio", 1006 nct_methods, 1007 sizeof(struct nct_softc) 1008 }; 1009 1010 DRIVER_MODULE(nctgpio, superio, nct_driver, NULL, NULL); 1011 MODULE_DEPEND(nctgpio, gpiobus, 1, 1, 1); 1012 MODULE_DEPEND(nctgpio, superio, 1, 1, 1); 1013 MODULE_VERSION(nctgpio, 1); 1014