| z8530.h (1ba1685b25c0189a4a2f2118b7151b96ccfec929) | z8530.h (27d5dc189c8e2eaf1cbe7e47078bf065854ba210) |
|---|---|
| 1/*- | 1/* |
| 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 | 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 |
| 29#ifndef _DEV_IC_Z8530_H_ 30#define _DEV_IC_Z8530_H_ | 29#ifndef _DEV_UART_DEV_Z8530_H_ 30#define _DEV_UART_DEV_Z8530_H_ |
| 31 32/* 33 * Channel B control: 0 34 * Channel B data: 1 35 * Channel A control: 2 36 * Channel A data: 3 | 31 32/* 33 * Channel B control: 0 34 * Channel B data: 1 35 * Channel A control: 2 36 * Channel A data: 3 |
| 37 * 38 * We expect a seperate subregion for each channel. |
|
| 37 */ | 39 */ |
| 38 39/* The following apply when using a device-scoped bus handle */ 40#define CHAN_A 2 41#define CHAN_B 0 42 | |
| 43#define REG_CTRL 0 44#define REG_DATA 1 45 46/* Write registers. */ 47#define WR_CR 0 /* Command Register. */ 48#define WR_IDT 1 /* Interrupt and Data Transfer Mode. */ 49#define WR_IV 2 /* Interrupt Vector (shared). */ 50#define WR_RPC 3 /* Receive Parameters and Control. */ --- 16 unchanged lines hidden (view full) --- 67#define RR_SRC 1 /* Special Receive Condition. */ 68#define RR_IV 2 /* Interrupt Vector. */ 69#define RR_IP 3 /* Interrupt Pending (ch A only). */ 70#define RR_MPM 4 /* Miscellaneous Parameters and Modes. */ 71#define RR_TPC 5 /* Transmit Parameters and Control. */ 72#define RR_BCL 6 /* Byte Count Low. */ 73#define RR_BCH 7 /* Byte Count High. */ 74#define RR_RB 8 /* Receive Buffer. */ | 40#define REG_CTRL 0 41#define REG_DATA 1 42 43/* Write registers. */ 44#define WR_CR 0 /* Command Register. */ 45#define WR_IDT 1 /* Interrupt and Data Transfer Mode. */ 46#define WR_IV 2 /* Interrupt Vector (shared). */ 47#define WR_RPC 3 /* Receive Parameters and Control. */ --- 16 unchanged lines hidden (view full) --- 64#define RR_SRC 1 /* Special Receive Condition. */ 65#define RR_IV 2 /* Interrupt Vector. */ 66#define RR_IP 3 /* Interrupt Pending (ch A only). */ 67#define RR_MPM 4 /* Miscellaneous Parameters and Modes. */ 68#define RR_TPC 5 /* Transmit Parameters and Control. */ 69#define RR_BCL 6 /* Byte Count Low. */ 70#define RR_BCH 7 /* Byte Count High. */ 71#define RR_RB 8 /* Receive Buffer. */ |
| 75#define RR_RPC 9 /* Receive Parameters and Control. */ | 72#define RR_RPC 9 /* Receive Parameters and Contro. */ |
| 76#define RR_MSB 10 /* Miscellaneous Status Bits. */ 77#define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */ 78#define RR_TCL 12 /* BRG Time Constant Low. */ 79#define RR_TCH 13 /* BRG Time Constant High. */ 80#define RR_EFC 14 /* Extended Feature and FIFO Control. */ 81#define RR_IC 15 /* Interrupt Control. */ 82 83/* Buffer and External Status (RR0). */ --- 163 unchanged lines hidden (view full) --- 247#define TPC_TB7 0x20 /* 7 databits. */ 248#define TPC_TB5 0x00 /* 5 or fewer databits. */ 249#define TPC_BRK 0x10 /* Send break. */ 250#define TPC_TXE 0x08 /* Transmitter Enable. */ 251#define TPC_CRC16 0x04 /* CRC16. */ 252#define TPC_RTS 0x02 /* RTS. */ 253#define TPC_CRC 0x01 /* CRC Enable. */ 254 | 73#define RR_MSB 10 /* Miscellaneous Status Bits. */ 74#define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */ 75#define RR_TCL 12 /* BRG Time Constant Low. */ 76#define RR_TCH 13 /* BRG Time Constant High. */ 77#define RR_EFC 14 /* Extended Feature and FIFO Control. */ 78#define RR_IC 15 /* Interrupt Control. */ 79 80/* Buffer and External Status (RR0). */ --- 163 unchanged lines hidden (view full) --- 244#define TPC_TB7 0x20 /* 7 databits. */ 245#define TPC_TB5 0x00 /* 5 or fewer databits. */ 246#define TPC_BRK 0x10 /* Send break. */ 247#define TPC_TXE 0x08 /* Transmitter Enable. */ 248#define TPC_CRC16 0x04 /* CRC16. */ 249#define TPC_RTS 0x02 /* RTS. */ 250#define TPC_CRC 0x01 /* CRC Enable. */ 251 |
| 255#endif /* _DEV_IC_Z8530_H_ */ | 252#endif /* _DEV_UART_DEV_Z8530_H_ */ |