pmc_events.h (477129542c073f9c1e46c12e27da454b82ac8ff3) pmc_events.h (6411d14d62a6bca53ba67bc581a1d89448f34944)
1/*-
2 * Copyright (c) 2005 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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4752 __PMC_EV(XSCALE, ADDRESS_BUS_TRANS) \
4753 __PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS) \
4754 __PMC_EV(XSCALE, DATA_BUS_TRANS)
4755
4756#define PMC_EV_XSCALE_FIRST PMC_EV_XSCALE_IC_FETCH
4757#define PMC_EV_XSCALE_LAST PMC_EV_XSCALE_DATA_BUS_TRANS
4758
4759/*
1/*-
2 * Copyright (c) 2005 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 4743 unchanged lines hidden (view full) ---

4752 __PMC_EV(XSCALE, ADDRESS_BUS_TRANS) \
4753 __PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS) \
4754 __PMC_EV(XSCALE, DATA_BUS_TRANS)
4755
4756#define PMC_EV_XSCALE_FIRST PMC_EV_XSCALE_IC_FETCH
4757#define PMC_EV_XSCALE_LAST PMC_EV_XSCALE_DATA_BUS_TRANS
4758
4759/*
4760 * ARMv7 Events
4761 */
4762
4763#define __PMC_EV_ARMV7() \
4764 __PMC_EV(ARMV7, PMNC_SW_INCR) \
4765 __PMC_EV(ARMV7, L1_ICACHE_REFILL) \
4766 __PMC_EV(ARMV7, ITLB_REFILL) \
4767 __PMC_EV(ARMV7, L1_DCACHE_REFILL) \
4768 __PMC_EV(ARMV7, L1_DCACHE_ACCESS) \
4769 __PMC_EV(ARMV7, DTLB_REFILL) \
4770 __PMC_EV(ARMV7, MEM_READ) \
4771 __PMC_EV(ARMV7, MEM_WRITE) \
4772 __PMC_EV(ARMV7, INSTR_EXECUTED) \
4773 __PMC_EV(ARMV7, EXC_TAKEN) \
4774 __PMC_EV(ARMV7, EXC_EXECUTED) \
4775 __PMC_EV(ARMV7, CID_WRITE) \
4776 __PMC_EV(ARMV7, PC_WRITE) \
4777 __PMC_EV(ARMV7, PC_IMM_BRANCH) \
4778 __PMC_EV(ARMV7, PC_PROC_RETURN) \
4779 __PMC_EV(ARMV7, MEM_UNALIGNED_ACCESS) \
4780 __PMC_EV(ARMV7, PC_BRANCH_MIS_PRED) \
4781 __PMC_EV(ARMV7, CLOCK_CYCLES) \
4782 __PMC_EV(ARMV7, PC_BRANCH_PRED) \
4783 __PMC_EV(ARMV7, MEM_ACCESS) \
4784 __PMC_EV(ARMV7, L1_ICACHE_ACCESS) \
4785 __PMC_EV(ARMV7, L1_DCACHE_WB) \
4786 __PMC_EV(ARMV7, L2_CACHE_ACCESS) \
4787 __PMC_EV(ARMV7, L2_CACHE_REFILL) \
4788 __PMC_EV(ARMV7, L2_CACHE_WB) \
4789 __PMC_EV(ARMV7, BUS_ACCESS) \
4790 __PMC_EV(ARMV7, MEM_ERROR) \
4791 __PMC_EV(ARMV7, INSTR_SPEC) \
4792 __PMC_EV(ARMV7, TTBR_WRITE) \
4793 __PMC_EV(ARMV7, BUS_CYCLES) \
4794 __PMC_EV(ARMV7, CPU_CYCLES)
4795
4796#define PMC_EV_ARMV7_FIRST PMC_EV_ARMV7_PMNC_SW_INCR
4797#define PMC_EV_ARMV7_LAST PMC_EV_ARMV7_CPU_CYCLES
4798
4799/*
4760 * MIPS Events from "Programming the MIPS32 24K Core Family",
4761 * Document Number: MD00355 Revision 04.63 December 19, 2008
4762 * These events are kept in the order found in Table 7.4.
4763 * For counters which are different between the left hand
4764 * column (0/2) and the right hand column (1/3) the left
4765 * hand is given first, e.g. BRANCH_COMPLETED and BRANCH_MISPRED
4766 * in the definition below.
4767 */

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5214 * 0x2000 0x0080 AMD K7 events
5215 * 0x2080 0x0100 AMD K8 events
5216 * 0x10000 0x0080 INTEL architectural fixed-function events
5217 * 0x10080 0x0F80 INTEL architectural programmable events
5218 * 0x11000 0x0080 INTEL Pentium 4 events
5219 * 0x11080 0x0080 INTEL Pentium MMX events
5220 * 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events
5221 * 0x11200 0x00FF INTEL XScale events
4800 * MIPS Events from "Programming the MIPS32 24K Core Family",
4801 * Document Number: MD00355 Revision 04.63 December 19, 2008
4802 * These events are kept in the order found in Table 7.4.
4803 * For counters which are different between the left hand
4804 * column (0/2) and the right hand column (1/3) the left
4805 * hand is given first, e.g. BRANCH_COMPLETED and BRANCH_MISPRED
4806 * in the definition below.
4807 */

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5254 * 0x2000 0x0080 AMD K7 events
5255 * 0x2080 0x0100 AMD K8 events
5256 * 0x10000 0x0080 INTEL architectural fixed-function events
5257 * 0x10080 0x0F80 INTEL architectural programmable events
5258 * 0x11000 0x0080 INTEL Pentium 4 events
5259 * 0x11080 0x0080 INTEL Pentium MMX events
5260 * 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events
5261 * 0x11200 0x00FF INTEL XScale events
5222 * 0x11300 0x00FF MIPS 24K events
5262 * 0x11300 0x00FF MIPS 24K events
5263 * 0x14000 0x0100 ARMv7 events
5223 * 0x20000 0x1000 Software events
5224 */
5225#define __PMC_EVENTS() \
5226 __PMC_EV_BLOCK(TSC, 0x01000) \
5227 __PMC_EV_TSC() \
5228 __PMC_EV_BLOCK(K7, 0x2000) \
5229 __PMC_EV_K7() \
5230 __PMC_EV_BLOCK(K8, 0x2080) \

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5248 __PMC_EV_BLOCK(UCF, 0x12000) \
5249 __PMC_EV_UCF() \
5250 __PMC_EV_BLOCK(UCP, 0x12080) \
5251 __PMC_EV_UCP() \
5252 __PMC_EV_BLOCK(PPC7450, 0x13000) \
5253 __PMC_EV_PPC7450() \
5254 __PMC_EV_BLOCK(PPC970, 0x13100) \
5255 __PMC_EV_PPC970() \
5264 * 0x20000 0x1000 Software events
5265 */
5266#define __PMC_EVENTS() \
5267 __PMC_EV_BLOCK(TSC, 0x01000) \
5268 __PMC_EV_TSC() \
5269 __PMC_EV_BLOCK(K7, 0x2000) \
5270 __PMC_EV_K7() \
5271 __PMC_EV_BLOCK(K8, 0x2080) \

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5289 __PMC_EV_BLOCK(UCF, 0x12000) \
5290 __PMC_EV_UCF() \
5291 __PMC_EV_BLOCK(UCP, 0x12080) \
5292 __PMC_EV_UCP() \
5293 __PMC_EV_BLOCK(PPC7450, 0x13000) \
5294 __PMC_EV_PPC7450() \
5295 __PMC_EV_BLOCK(PPC970, 0x13100) \
5296 __PMC_EV_PPC970() \
5297 __PMC_EV_BLOCK(ARMV7, 0x14000) \
5298 __PMC_EV_ARMV7() \
5256
5257#define PMC_EVENT_FIRST PMC_EV_TSC_TSC
5258#define PMC_EVENT_LAST PMC_EV_SOFT_LAST
5259
5260#endif /* _DEV_HWPMC_PMC_EVENTS_H_ */
5299
5300#define PMC_EVENT_FIRST PMC_EV_TSC_TSC
5301#define PMC_EVENT_LAST PMC_EV_SOFT_LAST
5302
5303#endif /* _DEV_HWPMC_PMC_EVENTS_H_ */