arswitchvar.h (4d846d260e2b9a3d4d0a701462568268cbfe7a5b) | arswitchvar.h (8f5dbc22e595e09a8beb81ff532df58f006b91cd) |
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1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2012 Stefan Bethke. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 18 unchanged lines hidden (view full) --- 27 * 28 * $FreeBSD$ 29 */ 30#ifndef __ARSWITCHVAR_H__ 31#define __ARSWITCHVAR_H__ 32 33typedef enum { 34 AR8X16_SWITCH_NONE, | 1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2012 Stefan Bethke. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 18 unchanged lines hidden (view full) --- 27 * 28 * $FreeBSD$ 29 */ 30#ifndef __ARSWITCHVAR_H__ 31#define __ARSWITCHVAR_H__ 32 33typedef enum { 34 AR8X16_SWITCH_NONE, |
35 AR8X16_SWITCH_AR7240, | |
36 AR8X16_SWITCH_AR8216, 37 AR8X16_SWITCH_AR8226, 38 AR8X16_SWITCH_AR8316, | 35 AR8X16_SWITCH_AR8216, 36 AR8X16_SWITCH_AR8226, 37 AR8X16_SWITCH_AR8316, |
39 AR8X16_SWITCH_AR9340, | |
40 AR8X16_SWITCH_AR8327, 41 AR8X16_SWITCH_AR8337, 42} ar8x16_switch_type; 43 44/* 45 * XXX TODO: start using this where required 46 */ 47#define AR8X16_IS_SWITCH(_sc, _type) \ --- 15 unchanged lines hidden (view full) --- 63 struct mtx sc_mtx; /* serialize access to softc */ 64 device_t sc_dev; 65 int phy4cpu; /* PHY4 is connected to the CPU */ 66 int numphys; /* PHYs we manage */ 67 int is_rgmii; /* PHY mode is RGMII (XXX which PHY?) */ 68 int is_gmii; /* PHY mode is GMII (XXX which PHY?) */ 69 int is_mii; /* PHY mode is MII (XXX which PHY?) */ 70 int page; | 38 AR8X16_SWITCH_AR8327, 39 AR8X16_SWITCH_AR8337, 40} ar8x16_switch_type; 41 42/* 43 * XXX TODO: start using this where required 44 */ 45#define AR8X16_IS_SWITCH(_sc, _type) \ --- 15 unchanged lines hidden (view full) --- 61 struct mtx sc_mtx; /* serialize access to softc */ 62 device_t sc_dev; 63 int phy4cpu; /* PHY4 is connected to the CPU */ 64 int numphys; /* PHYs we manage */ 65 int is_rgmii; /* PHY mode is RGMII (XXX which PHY?) */ 66 int is_gmii; /* PHY mode is GMII (XXX which PHY?) */ 67 int is_mii; /* PHY mode is MII (XXX which PHY?) */ 68 int page; |
71 int is_internal_switch; | |
72 int chip_ver; 73 int chip_rev; 74 int mii_lo_first; /* Send low data DWORD before high */ 75 ar8x16_switch_type sc_switchtype; 76 /* should be the max of both pre-AR8327 and AR8327 ports */ 77 char *ifname[ARSWITCH_NUM_PHYS]; 78 device_t miibus[ARSWITCH_NUM_PHYS]; 79 if_t ifp[ARSWITCH_NUM_PHYS]; --- 111 unchanged lines hidden --- | 69 int chip_ver; 70 int chip_rev; 71 int mii_lo_first; /* Send low data DWORD before high */ 72 ar8x16_switch_type sc_switchtype; 73 /* should be the max of both pre-AR8327 and AR8327 ports */ 74 char *ifname[ARSWITCH_NUM_PHYS]; 75 device_t miibus[ARSWITCH_NUM_PHYS]; 76 if_t ifp[ARSWITCH_NUM_PHYS]; --- 111 unchanged lines hidden --- |