if_ath.c (ee3219757aa57d39fee3f0339b241b70375afb1a) if_ath.c (7e97436b0ed53d1f264b8d586b0b0b24aede8c10)
1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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294 goto bad;
295 }
296 ic = ifp->if_l2com;
297
298 /* set these up early for if_printf use */
299 if_initname(ifp, device_get_name(sc->sc_dev),
300 device_get_unit(sc->sc_dev));
301
1/*-
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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294 goto bad;
295 }
296 ic = ifp->if_l2com;
297
298 /* set these up early for if_printf use */
299 if_initname(ifp, device_get_name(sc->sc_dev),
300 device_get_unit(sc->sc_dev));
301
302 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, sc->sc_eepromdata, &status);
302 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
303 sc->sc_eepromdata, &status);
303 if (ah == NULL) {
304 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
305 status);
306 error = ENXIO;
307 goto bad;
308 }
309 sc->sc_ah = ah;
310 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */

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464 sc->sc_rc = ath_rate_attach(sc);
465 if (sc->sc_rc == NULL) {
466 error = EIO;
467 goto bad2;
468 }
469
470 /* Attach DFS module */
471 if (! ath_dfs_attach(sc)) {
304 if (ah == NULL) {
305 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
306 status);
307 error = ENXIO;
308 goto bad;
309 }
310 sc->sc_ah = ah;
311 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */

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465 sc->sc_rc = ath_rate_attach(sc);
466 if (sc->sc_rc == NULL) {
467 error = EIO;
468 goto bad2;
469 }
470
471 /* Attach DFS module */
472 if (! ath_dfs_attach(sc)) {
472 device_printf(sc->sc_dev, "%s: unable to attach DFS\n", __func__);
473 device_printf(sc->sc_dev,
474 "%s: unable to attach DFS\n", __func__);
473 error = EIO;
474 goto bad2;
475 }
476
477 /* Start DFS processing tasklet */
478 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
479
480 sc->sc_blinking = 0;

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516 | IEEE80211_C_WDS /* 4-address traffic works */
517 | IEEE80211_C_MBSS /* mesh point link mode */
518 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
519 | IEEE80211_C_SHSLOT /* short slot time supported */
520 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
521 | IEEE80211_C_BGSCAN /* capable of bg scanning */
522 | IEEE80211_C_TXFRAG /* handle tx frags */
523#ifdef ATH_ENABLE_DFS
475 error = EIO;
476 goto bad2;
477 }
478
479 /* Start DFS processing tasklet */
480 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
481
482 sc->sc_blinking = 0;

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518 | IEEE80211_C_WDS /* 4-address traffic works */
519 | IEEE80211_C_MBSS /* mesh point link mode */
520 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
521 | IEEE80211_C_SHSLOT /* short slot time supported */
522 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
523 | IEEE80211_C_BGSCAN /* capable of bg scanning */
524 | IEEE80211_C_TXFRAG /* handle tx frags */
525#ifdef ATH_ENABLE_DFS
524 | IEEE80211_C_DFS /* Enable DFS radar detection */
526 | IEEE80211_C_DFS /* Enable radar detection */
525#endif
526 ;
527 /*
528 * Query the hal to figure out h/w crypto support.
529 */
530 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
531 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
532 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))

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628 /*
629 * Query HT capabilities
630 */
631 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
632 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
633 int rxs, txs;
634
635 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
527#endif
528 ;
529 /*
530 * Query the hal to figure out h/w crypto support.
531 */
532 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
533 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))

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630 /*
631 * Query HT capabilities
632 */
633 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
634 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
635 int rxs, txs;
636
637 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
636 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
637 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
638 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
639 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
640 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
638 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
639 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
640 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
641 | IEEE80211_HTCAP_MAXAMSDU_3839
642 /* max A-MSDU length */
643 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
641 ;
642
643 /*
644 * Enable short-GI for HT20 only if the hardware
645 * advertises support.
646 * Notably, anything earlier than the AR9287 doesn't.
647 */
648 if ((ath_hal_getcapability(ah,

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653 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
654 }
655
656 if (wmodes & HAL_MODE_HT40)
657 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
658 | IEEE80211_HTCAP_SHORTGI40;
659
660 /*
644 ;
645
646 /*
647 * Enable short-GI for HT20 only if the hardware
648 * advertises support.
649 * Notably, anything earlier than the AR9287 doesn't.
650 */
651 if ((ath_hal_getcapability(ah,

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656 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
657 }
658
659 if (wmodes & HAL_MODE_HT40)
660 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
661 | IEEE80211_HTCAP_SHORTGI40;
662
663 /*
661 * rx/tx stream is not currently used anywhere; it needs to be taken
662 * into account when negotiating which MCS rates it'll receive and
664 * TX/RX streams need to be taken into account when
665 * negotiating which MCS rates it'll receive and
663 * what MCS rates are available for TX.
664 */
665 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &rxs);
666 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &txs);
667
668 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
669 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
670
671 ic->ic_txstream = txs;
672 ic->ic_rxstream = rxs;
673
666 * what MCS rates are available for TX.
667 */
668 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &rxs);
669 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &txs);
670
671 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
672 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
673
674 ic->ic_txstream = txs;
675 ic->ic_rxstream = rxs;
676
674 device_printf(sc->sc_dev, "[HT] %d RX streams; %d TX streams\n", rxs, txs);
677 device_printf(sc->sc_dev,
678 "[HT] %d RX streams; %d TX streams\n", rxs, txs);
675 }
676#endif
677
678 /*
679 * Check if the hardware requires PCI register serialisation.
680 * Some of the Owl based MACs require this.
681 */
682 if (mp_ncpus > 1 &&
683 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
684 0, NULL) == HAL_OK) {
685 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
679 }
680#endif
681
682 /*
683 * Check if the hardware requires PCI register serialisation.
684 * Some of the Owl based MACs require this.
685 */
686 if (mp_ncpus > 1 &&
687 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
688 0, NULL) == HAL_OK) {
689 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
686 device_printf(sc->sc_dev, "Enabling register serialisation\n");
690 device_printf(sc->sc_dev,
691 "Enabling register serialisation\n");
687 }
688
689 /*
690 * Indicate we need the 802.11 header padded to a
691 * 32-bit boundary for 4-address and QoS frames.
692 */
693 ic->ic_flags |= IEEE80211_F_DATAPAD;
694

--- 6011 unchanged lines hidden --- 		692 }
693
694 /*
695 * Indicate we need the 802.11 header padded to a
696 * 32-bit boundary for 4-address and QoS frames.
697 */
698 ic->ic_flags |= IEEE80211_F_DATAPAD;
699

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