| mvreg.h (e11b6fa307b49a2a9ba2d0af0d80ddc103c84c10) | mvreg.h (16694521fe80f54bf8f37334fe9a54bc5c953a6a) |
|---|---|
| 1/*- | 1/*- |
| 2 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. | 2 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. |
| 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright --- 18 unchanged lines hidden (view full) --- 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 | 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright --- 18 unchanged lines hidden (view full) --- 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34#ifndef _MVREG_H_ 35#define _MVREG_H_ 36 |
| 37#define BRIDGE_IRQ_CAUSE 0x10 38#define BRIGDE_IRQ_MASK 0x14 39 | |
| 40#if defined(SOC_MV_DISCOVERY) 41#define IRQ_CAUSE_ERROR 0x0 42#define IRQ_CAUSE 0x4 43#define IRQ_CAUSE_HI 0x8 44#define IRQ_MASK_ERROR 0xC 45#define IRQ_MASK 0x10 46#define IRQ_MASK_HI 0x14 47#define IRQ_CAUSE_SELECT 0x18 48#define FIQ_MASK_ERROR 0x1C 49#define FIQ_MASK 0x20 50#define FIQ_MASK_HI 0x24 51#define FIQ_CAUSE_SELECT 0x28 | 37#if defined(SOC_MV_DISCOVERY) 38#define IRQ_CAUSE_ERROR 0x0 39#define IRQ_CAUSE 0x4 40#define IRQ_CAUSE_HI 0x8 41#define IRQ_MASK_ERROR 0xC 42#define IRQ_MASK 0x10 43#define IRQ_MASK_HI 0x14 44#define IRQ_CAUSE_SELECT 0x18 45#define FIQ_MASK_ERROR 0x1C 46#define FIQ_MASK 0x20 47#define FIQ_MASK_HI 0x24 48#define FIQ_CAUSE_SELECT 0x28 |
| 52#define ENDPOINT_IRQ_MASK_ERROR 0x2C 53#define ENDPOINT_IRQ_MASK 0x30 54#define ENDPOINT_IRQ_MASK_HI 0x34 | 49#define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C 50#define ENDPOINT_IRQ_MASK(n) 0x30 51#define ENDPOINT_IRQ_MASK_HI(n) 0x34 |
| 55#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 | 52#define ENDPOINT_IRQ_CAUSE_SELECT 0x38 |
| 56#else /* !SOC_MV_DISCOVERY */ | 53#elif defined (SOC_MV_LOKIPLUS) || defined (SOC_MV_FREY) |
| 57#define IRQ_CAUSE 0x0 58#define IRQ_MASK 0x4 59#define FIQ_MASK 0x8 | 54#define IRQ_CAUSE 0x0 55#define IRQ_MASK 0x4 56#define FIQ_MASK 0x8 |
| 60#define ENDPOINT_IRQ_MASK 0xC | 57#define ENDPOINT_IRQ_MASK(n) (0xC + (n) * 4) 58#define IRQ_CAUSE_HI (-1) /* Fake defines for unified */ 59#define IRQ_MASK_HI (-1) /* interrupt controller code */ 60#define FIQ_MASK_HI (-1) 61#define ENDPOINT_IRQ_MASK_HI(n) (-1) 62#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) 63#define IRQ_CAUSE_ERROR (-1) 64#define IRQ_MASK_ERROR (-1) 65#elif defined (SOC_MV_ARMADAXP) 66#define IRQ_CAUSE 0x18 67#define IRQ_MASK 0x30 68#else /* !SOC_MV_DISCOVERY && !SOC_MV_LOKIPLUS */ 69#define IRQ_CAUSE 0x0 70#define IRQ_MASK 0x4 71#define FIQ_MASK 0x8 72#define ENDPOINT_IRQ_MASK(n) 0xC |
| 61#define IRQ_CAUSE_HI 0x10 62#define IRQ_MASK_HI 0x14 63#define FIQ_MASK_HI 0x18 | 73#define IRQ_CAUSE_HI 0x10 74#define IRQ_MASK_HI 0x14 75#define FIQ_MASK_HI 0x18 |
| 64#define ENDPOINT_IRQ_MASK_HI 0x1C | 76#define ENDPOINT_IRQ_MASK_HI(n) 0x1C 77#define ENDPOINT_IRQ_MASK_ERROR(n) (-1) |
| 65#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 66#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 67#endif 68 | 78#define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ 79#define IRQ_MASK_ERROR (-1) /* interrupt controller code */ 80#endif 81 |
| 82#if defined(SOC_MV_FREY) 83#define BRIDGE_IRQ_CAUSE 0x118 84#define IRQ_TIMER0 0x00000002 85#define IRQ_TIMER1 0x00000004 86#define IRQ_TIMER_WD 0x00000008 87 88#define BRIDGE_IRQ_MASK 0x11c 89#define IRQ_TIMER0_MASK 0x00000002 90#define IRQ_TIMER1_MASK 0x00000004 91#define IRQ_TIMER_WD_MASK 0x00000008 92#elif defined(SOC_MV_ARMADAXP) 93#define BRIDGE_IRQ_CAUSE 0x68 94#define IRQ_TIMER0 0x00000001 95#define IRQ_TIMER1 0x00000002 96#define IRQ_TIMER_WD 0x00000004 97#else |
|
| 69#define BRIDGE_IRQ_CAUSE 0x10 70#define IRQ_CPU_SELF 0x00000001 71#define IRQ_TIMER0 0x00000002 72#define IRQ_TIMER1 0x00000004 73#define IRQ_TIMER_WD 0x00000008 74 75#define BRIDGE_IRQ_MASK 0x14 76#define IRQ_CPU_MASK 0x00000001 77#define IRQ_TIMER0_MASK 0x00000002 78#define IRQ_TIMER1_MASK 0x00000004 79#define IRQ_TIMER_WD_MASK 0x00000008 | 98#define BRIDGE_IRQ_CAUSE 0x10 99#define IRQ_CPU_SELF 0x00000001 100#define IRQ_TIMER0 0x00000002 101#define IRQ_TIMER1 0x00000004 102#define IRQ_TIMER_WD 0x00000008 103 104#define BRIDGE_IRQ_MASK 0x14 105#define IRQ_CPU_MASK 0x00000001 106#define IRQ_TIMER0_MASK 0x00000002 107#define IRQ_TIMER1_MASK 0x00000004 108#define IRQ_TIMER_WD_MASK 0x00000008 |
| 109#endif |
|
| 80 | 110 |
| 111#if defined(SOC_MV_LOKIPLUS) || defined(SOC_MV_FREY) 112#define IRQ_CPU_SELF_CLR IRQ_CPU_SELF 113#define IRQ_TIMER0_CLR IRQ_TIMER0 114#define IRQ_TIMER1_CLR IRQ_TIMER1 115#define IRQ_TIMER_WD_CLR IRQ_TIMER_WD 116#else 117#define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) 118#define IRQ_TIMER0_CLR (~IRQ_TIMER0) 119#define IRQ_TIMER1_CLR (~IRQ_TIMER1) 120#define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) 121#endif 122 |
|
| 81/* 82 * System reset 83 */ 84#define RSTOUTn_MASK 0x8 85#define WD_RST_OUT_EN 0x00000002 86#define SOFT_RST_OUT_EN 0x00000004 87#define SYSTEM_SOFT_RESET 0xc 88#define SYS_SOFT_RST 0x00000001 --- 61 unchanged lines hidden (view full) --- 150#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 151#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 152#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 153#endif 154 155/* 156 * Timers 157 */ | 123/* 124 * System reset 125 */ 126#define RSTOUTn_MASK 0x8 127#define WD_RST_OUT_EN 0x00000002 128#define SOFT_RST_OUT_EN 0x00000004 129#define SYSTEM_SOFT_RESET 0xc 130#define SYS_SOFT_RST 0x00000001 --- 61 unchanged lines hidden (view full) --- 192#define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) 193#define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) 194#define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) 195#endif 196 197/* 198 * Timers 199 */ |
| 200#define CPU_TIMERS_BASE 0x300 |
|
| 158#define CPU_TIMER_CONTROL 0x0 159#define CPU_TIMER0_EN 0x00000001 160#define CPU_TIMER0_AUTO 0x00000002 161#define CPU_TIMER1_EN 0x00000004 162#define CPU_TIMER1_AUTO 0x00000008 163#define CPU_TIMER_WD_EN 0x00000010 164#define CPU_TIMER_WD_AUTO 0x00000020 165#define CPU_TIMER0_REL 0x10 --- 11 unchanged lines hidden (view full) --- 177 178/* SATAHC registers */ 179#define SATA_CR 0x000 /* Configuration Reg. */ 180#define SATA_CR_NODMABS (1 << 8) 181#define SATA_CR_NOEDMABS (1 << 9) 182#define SATA_CR_NOPRDPBS (1 << 10) 183#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 184 | 201#define CPU_TIMER_CONTROL 0x0 202#define CPU_TIMER0_EN 0x00000001 203#define CPU_TIMER0_AUTO 0x00000002 204#define CPU_TIMER1_EN 0x00000004 205#define CPU_TIMER1_AUTO 0x00000008 206#define CPU_TIMER_WD_EN 0x00000010 207#define CPU_TIMER_WD_AUTO 0x00000020 208#define CPU_TIMER0_REL 0x10 --- 11 unchanged lines hidden (view full) --- 220 221/* SATAHC registers */ 222#define SATA_CR 0x000 /* Configuration Reg. */ 223#define SATA_CR_NODMABS (1 << 8) 224#define SATA_CR_NOEDMABS (1 << 9) 225#define SATA_CR_NOPRDPBS (1 << 10) 226#define SATA_CR_COALDIS(ch) (1 << (24 + ch)) 227 |
| 185#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ | 228/* Interrupt Coalescing Threshold Reg. */ 229#define SATA_ICTR 0x00C 230#define SATA_ICTR_MAX ((1 << 8) - 1) 231 232/* Interrupt Time Threshold Reg. */ 233#define SATA_ITTR 0x010 234#define SATA_ITTR_MAX ((1 << 24) - 1) 235 236#define SATA_ICR 0x014 /* Interrupt Cause Reg. */ |
| 186#define SATA_ICR_DMADONE(ch) (1 << (ch)) 187#define SATA_ICR_COAL (1 << 4) 188#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 189 190#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 191#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 192#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 193#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) --- 72 unchanged lines hidden (view full) --- 266#define MV_GPIO_OUT_BLINK 0x1 267#define MV_GPIO_OUT_OPEN_DRAIN 0x2 268#define MV_GPIO_OUT_OPEN_SRC 0x4 269 270#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 271#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 272#define IRQ2GPIO(irq) ((irq) - NIRQ) 273 | 237#define SATA_ICR_DMADONE(ch) (1 << (ch)) 238#define SATA_ICR_COAL (1 << 4) 239#define SATA_ICR_DEV(ch) (1 << (8 + ch)) 240 241#define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ 242#define SATA_MICR_ERR(ch) (1 << (2 * ch)) 243#define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) 244#define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) --- 72 unchanged lines hidden (view full) --- 317#define MV_GPIO_OUT_BLINK 0x1 318#define MV_GPIO_OUT_OPEN_DRAIN 0x2 319#define MV_GPIO_OUT_OPEN_SRC 0x4 320 321#define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) 322#define GPIO2IRQ(gpio) ((gpio) + NIRQ) 323#define IRQ2GPIO(irq) ((irq) - NIRQ) 324 |
| 274/* 275 * MPP 276 */ 277#if defined(SOC_MV_ORION) 278#define MPP_CONTROL0 0x00 279#define MPP_CONTROL1 0x04 280#define MPP_CONTROL2 0x50 281#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) 282#define MPP_CONTROL0 0x00 283#define MPP_CONTROL1 0x04 284#define MPP_CONTROL2 0x08 285#define MPP_CONTROL3 0x0C 286#define MPP_CONTROL4 0x10 287#define MPP_CONTROL5 0x14 288#define MPP_CONTROL6 0x18 289#else 290#error SOC_MV_XX not defined 291#endif 292 293#if defined(SOC_MV_ORION) | 325#if defined(SOC_MV_ORION) || defined(SOC_MV_LOKIPLUS) |
| 294#define SAMPLE_AT_RESET 0x10 295#elif defined(SOC_MV_KIRKWOOD) 296#define SAMPLE_AT_RESET 0x30 297#elif defined(SOC_MV_DISCOVERY) 298#define SAMPLE_AT_RESET_LO 0x30 299#define SAMPLE_AT_RESET_HI 0x34 | 326#define SAMPLE_AT_RESET 0x10 327#elif defined(SOC_MV_KIRKWOOD) 328#define SAMPLE_AT_RESET 0x30 329#elif defined(SOC_MV_DISCOVERY) 330#define SAMPLE_AT_RESET_LO 0x30 331#define SAMPLE_AT_RESET_HI 0x34 |
| 300#else 301#error SOC_MV_XX not defined | 332#elif defined(SOC_MV_DOVE) 333#define SAMPLE_AT_RESET_LO 0x14 334#define SAMPLE_AT_RESET_HI 0x18 335#elif defined(SOC_MV_FREY) 336#define SAMPLE_AT_RESET 0x100 |
| 302#endif 303 304/* 305 * Clocks 306 */ 307#if defined(SOC_MV_ORION) 308#define TCLK_MASK 0x00000300 309#define TCLK_SHIFT 0x08 310#elif defined(SOC_MV_DISCOVERY) 311#define TCLK_MASK 0x00000180 312#define TCLK_SHIFT 0x07 | 337#endif 338 339/* 340 * Clocks 341 */ 342#if defined(SOC_MV_ORION) 343#define TCLK_MASK 0x00000300 344#define TCLK_SHIFT 0x08 345#elif defined(SOC_MV_DISCOVERY) 346#define TCLK_MASK 0x00000180 347#define TCLK_SHIFT 0x07 |
| 348#elif defined(SOC_MV_LOKIPLUS) 349#define TCLK_MASK 0x0000F000 350#define TCLK_SHIFT 0x0C |
|
| 313#endif 314 315#define TCLK_100MHZ 100000000 316#define TCLK_125MHZ 125000000 317#define TCLK_133MHZ 133333333 318#define TCLK_150MHZ 150000000 319#define TCLK_166MHZ 166666667 320#define TCLK_200MHZ 200000000 | 351#endif 352 353#define TCLK_100MHZ 100000000 354#define TCLK_125MHZ 125000000 355#define TCLK_133MHZ 133333333 356#define TCLK_150MHZ 150000000 357#define TCLK_166MHZ 166666667 358#define TCLK_200MHZ 200000000 |
| 359#define TCLK_250MHZ 250000000 360#define TCLK_300MHZ 300000000 361#define TCLK_667MHZ 667000000 |
|
| 321 322/* | 362 363/* |
| 364 * CPU Cache Configuration 365 */ 366 367#define CPU_CONFIG 0x00000000 368#define CPU_CONFIG_IC_PREF 0x00010000 369#define CPU_CONFIG_DC_PREF 0x00020000 370#define CPU_CONTROL 0x00000004 371#define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ 372#define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ 373#define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ 374#define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ 375 376/* 377 * PCI Express port control (CPU Control registers) 378 */ 379#define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) 380 381/* 382 * Vendor ID 383 */ 384#define PCI_VENDORID_MRVL 0x11AB 385#define PCI_VENDORID_MRVL2 0x1B4B 386 387/* |
|
| 323 * Chip ID 324 */ 325#define MV_DEV_88F5181 0x5181 326#define MV_DEV_88F5182 0x5182 327#define MV_DEV_88F5281 0x5281 328#define MV_DEV_88F6281 0x6281 | 388 * Chip ID 389 */ 390#define MV_DEV_88F5181 0x5181 391#define MV_DEV_88F5182 0x5182 392#define MV_DEV_88F5281 0x5281 393#define MV_DEV_88F6281 0x6281 |
| 394#define MV_DEV_88F6781 0x6781 |
|
| 329#define MV_DEV_88F6282 0x6282 330#define MV_DEV_MV78100_Z0 0x6381 331#define MV_DEV_MV78100 0x7810 | 395#define MV_DEV_88F6282 0x6282 396#define MV_DEV_MV78100_Z0 0x6381 397#define MV_DEV_MV78100 0x7810 |
| 398#define MV_DEV_MV78130 0x7813 399#define MV_DEV_MV78160 0x7816 400#define MV_DEV_MV78230 0x7823 401#define MV_DEV_MV78260 0x7826 402#define MV_DEV_MV78460 0x7846 403#define MV_DEV_88RC8180 0x8180 404#define MV_DEV_88RC9480 0x9480 405#define MV_DEV_88RC9580 0x9580 |
|
| 332 | 406 |
| 407#define MV_DEV_FAMILY_MASK 0xff00 408#define MV_DEV_DISCOVERY 0x7800 409 410/* 411 * Doorbell register control 412 */ 413#define MV_DRBL_PCIE_TO_CPU 0 414#define MV_DRBL_CPU_TO_PCIE 1 415 416#if defined(SOC_MV_FREY) 417#define MV_DRBL_CAUSE(d,u) (0x60 + 0x20 * (d) + 0x8 * (u)) 418#define MV_DRBL_MASK(d,u) (0x60 + 0x20 * (d) + 0x8 * (u) + 0x4) 419#define MV_DRBL_MSG(m,d,u) (0x8 * (u) + 0x20 * (d) + 0x4 * (m)) 420#else 421#define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) 422#define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) 423#define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) 424#endif |
|
| 333#endif /* _MVREG_H_ */ | 425#endif /* _MVREG_H_ */ |