| sysreg.h (b626f5a73a48f44a31a200291b141e1da408a2ff) | sysreg.h (595f8a5905b062aedcd455b703cd63ca44f23f18) |
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| 1/*- 2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3 * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 28 unchanged lines hidden (view full) --- 37 */ 38 39#ifndef MACHINE_SYSREG_H 40#define MACHINE_SYSREG_H 41 42#include <machine/acle-compat.h> 43 44/* | 1/*- 2 * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com> 3 * Copyright 2014 Michal Meloun <meloun@miracle.cz> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 28 unchanged lines hidden (view full) --- 37 */ 38 39#ifndef MACHINE_SYSREG_H 40#define MACHINE_SYSREG_H 41 42#include <machine/acle-compat.h> 43 44/* |
| 45 * CP14 registers 46 */ 47#if __ARM_ARCH >= 6 48 49#define CP14_DBGDIDR(rr) p14, 0, rr, c0, c0, 0 /* Debug ID Register */ 50#define CP14_DBGDSCRext_V6(rr) p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */ 51#define CP14_DBGDSCRext_V7(rr) p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */ 52#define CP14_DBGVCR(rr) p14, 0, rr, c0, c7, 0 /* Vector Catch Register */ 53#define CP14_DBGOSLAR(rr) p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */ 54#define CP14_DBGOSLSR(rr) p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */ 55#define CP14_DBGOSDLR(rr) p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */ 56#define CP14_DBGPRSR(rr) p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */ 57 58#define CP14_DBGDSCRint(rr) CP14_DBGDSCRext_V6(rr) /* Debug Status and Ctrl internal view */ 59 60#endif 61 62/* |
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| 45 * CP15 C0 registers 46 */ 47#define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ 48#define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ 49#define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ 50#define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ 51#define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ 52#define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ --- 237 unchanged lines hidden --- | 63 * CP15 C0 registers 64 */ 65#define CP15_MIDR(rr) p15, 0, rr, c0, c0, 0 /* Main ID Register */ 66#define CP15_CTR(rr) p15, 0, rr, c0, c0, 1 /* Cache Type Register */ 67#define CP15_TCMTR(rr) p15, 0, rr, c0, c0, 2 /* TCM Type Register */ 68#define CP15_TLBTR(rr) p15, 0, rr, c0, c0, 3 /* TLB Type Register */ 69#define CP15_MPIDR(rr) p15, 0, rr, c0, c0, 5 /* Multiprocessor Affinity Register */ 70#define CP15_REVIDR(rr) p15, 0, rr, c0, c0, 6 /* Revision ID Register */ --- 237 unchanged lines hidden --- |