xref: /titanic_53/usr/src/uts/i86pc/io/rootnex.c (revision 8a552b2db9c23aa11e42a38ff4a3a9558e186b8d)
17c478bd9Sstevel@tonic-gate /*
27c478bd9Sstevel@tonic-gate  * CDDL HEADER START
37c478bd9Sstevel@tonic-gate  *
47c478bd9Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
57c478bd9Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
67c478bd9Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
77c478bd9Sstevel@tonic-gate  * with the License.
87c478bd9Sstevel@tonic-gate  *
97c478bd9Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
107c478bd9Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
117c478bd9Sstevel@tonic-gate  * See the License for the specific language governing permissions
127c478bd9Sstevel@tonic-gate  * and limitations under the License.
137c478bd9Sstevel@tonic-gate  *
147c478bd9Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
157c478bd9Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
167c478bd9Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
177c478bd9Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
187c478bd9Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
197c478bd9Sstevel@tonic-gate  *
207c478bd9Sstevel@tonic-gate  * CDDL HEADER END
217c478bd9Sstevel@tonic-gate  */
227c478bd9Sstevel@tonic-gate /*
23*8a552b2dScth  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
247c478bd9Sstevel@tonic-gate  * Use is subject to license terms.
257c478bd9Sstevel@tonic-gate  */
267c478bd9Sstevel@tonic-gate 
277c478bd9Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
287c478bd9Sstevel@tonic-gate 
297c478bd9Sstevel@tonic-gate /*
3012f080e7Smrj  * x86 root nexus driver
317c478bd9Sstevel@tonic-gate  */
327c478bd9Sstevel@tonic-gate 
337c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h>
347c478bd9Sstevel@tonic-gate #include <sys/conf.h>
357c478bd9Sstevel@tonic-gate #include <sys/autoconf.h>
367c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h>
377c478bd9Sstevel@tonic-gate #include <sys/debug.h>
387c478bd9Sstevel@tonic-gate #include <sys/psw.h>
397c478bd9Sstevel@tonic-gate #include <sys/ddidmareq.h>
407c478bd9Sstevel@tonic-gate #include <sys/promif.h>
417c478bd9Sstevel@tonic-gate #include <sys/devops.h>
427c478bd9Sstevel@tonic-gate #include <sys/kmem.h>
437c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h>
447c478bd9Sstevel@tonic-gate #include <vm/seg.h>
457c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h>
467c478bd9Sstevel@tonic-gate #include <vm/seg_dev.h>
477c478bd9Sstevel@tonic-gate #include <sys/vmem.h>
487c478bd9Sstevel@tonic-gate #include <sys/mman.h>
497c478bd9Sstevel@tonic-gate #include <vm/hat.h>
507c478bd9Sstevel@tonic-gate #include <vm/as.h>
517c478bd9Sstevel@tonic-gate #include <vm/page.h>
527c478bd9Sstevel@tonic-gate #include <sys/avintr.h>
537c478bd9Sstevel@tonic-gate #include <sys/errno.h>
547c478bd9Sstevel@tonic-gate #include <sys/modctl.h>
557c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h>
567c478bd9Sstevel@tonic-gate #include <sys/sunddi.h>
577c478bd9Sstevel@tonic-gate #include <sys/sunndi.h>
587a364d25Sschwartz #include <sys/mach_intr.h>
597c478bd9Sstevel@tonic-gate #include <sys/psm.h>
607c478bd9Sstevel@tonic-gate #include <sys/ontrap.h>
6112f080e7Smrj #include <sys/atomic.h>
6212f080e7Smrj #include <sys/sdt.h>
6312f080e7Smrj #include <sys/rootnex.h>
6412f080e7Smrj #include <vm/hat_i86.h>
657c478bd9Sstevel@tonic-gate 
667c478bd9Sstevel@tonic-gate 
6712f080e7Smrj /*
6812f080e7Smrj  * enable/disable extra checking of function parameters. Useful for debugging
6912f080e7Smrj  * drivers.
7012f080e7Smrj  */
7112f080e7Smrj #ifdef	DEBUG
7212f080e7Smrj int rootnex_alloc_check_parms = 1;
7312f080e7Smrj int rootnex_bind_check_parms = 1;
7412f080e7Smrj int rootnex_bind_check_inuse = 1;
7512f080e7Smrj int rootnex_unbind_verify_buffer = 0;
7612f080e7Smrj int rootnex_sync_check_parms = 1;
7712f080e7Smrj #else
7812f080e7Smrj int rootnex_alloc_check_parms = 0;
7912f080e7Smrj int rootnex_bind_check_parms = 0;
8012f080e7Smrj int rootnex_bind_check_inuse = 0;
8112f080e7Smrj int rootnex_unbind_verify_buffer = 0;
8212f080e7Smrj int rootnex_sync_check_parms = 0;
8312f080e7Smrj #endif
847c478bd9Sstevel@tonic-gate 
8512f080e7Smrj /* Semi-temporary patchables to phase in bug fixes, test drivers, etc. */
867c478bd9Sstevel@tonic-gate int rootnex_bind_fail = 1;
877c478bd9Sstevel@tonic-gate int rootnex_bind_warn = 1;
887c478bd9Sstevel@tonic-gate uint8_t *rootnex_warn_list;
897c478bd9Sstevel@tonic-gate /* bitmasks for rootnex_warn_list. Up to 8 different warnings with uint8_t */
907c478bd9Sstevel@tonic-gate #define	ROOTNEX_BIND_WARNING	(0x1 << 0)
917c478bd9Sstevel@tonic-gate 
927c478bd9Sstevel@tonic-gate /*
9312f080e7Smrj  * revert back to old broken behavior of always sync'ing entire copy buffer.
9412f080e7Smrj  * This is useful if be have a buggy driver which doesn't correctly pass in
9512f080e7Smrj  * the offset and size into ddi_dma_sync().
967c478bd9Sstevel@tonic-gate  */
9712f080e7Smrj int rootnex_sync_ignore_params = 0;
987c478bd9Sstevel@tonic-gate 
997c478bd9Sstevel@tonic-gate /*
10012f080e7Smrj  * maximum size that we will allow for a copy buffer. Can be patched on the
10112f080e7Smrj  * fly
1027c478bd9Sstevel@tonic-gate  */
10312f080e7Smrj size_t rootnex_max_copybuf_size = 0x100000;
1047c478bd9Sstevel@tonic-gate 
1057c478bd9Sstevel@tonic-gate /*
10612f080e7Smrj  * For the 64-bit kernel, pre-alloc enough cookies for a 256K buffer plus 1
10712f080e7Smrj  * page for alignment. For the 32-bit kernel, pre-alloc enough cookies for a
10812f080e7Smrj  * 64K buffer plus 1 page for alignment (we have less kernel space in a 32-bit
10912f080e7Smrj  * kernel). Allocate enough windows to handle a 256K buffer w/ at least 65
11012f080e7Smrj  * sgllen DMA engine, and enough copybuf buffer state pages to handle 2 pages
11112f080e7Smrj  * (< 8K). We will still need to allocate the copy buffer during bind though
11212f080e7Smrj  * (if we need one). These can only be modified in /etc/system before rootnex
11312f080e7Smrj  * attach.
1147c478bd9Sstevel@tonic-gate  */
11512f080e7Smrj #if defined(__amd64)
11612f080e7Smrj int rootnex_prealloc_cookies = 65;
11712f080e7Smrj int rootnex_prealloc_windows = 4;
11812f080e7Smrj int rootnex_prealloc_copybuf = 2;
11912f080e7Smrj #else
12012f080e7Smrj int rootnex_prealloc_cookies = 33;
12112f080e7Smrj int rootnex_prealloc_windows = 4;
12212f080e7Smrj int rootnex_prealloc_copybuf = 2;
12312f080e7Smrj #endif
1247c478bd9Sstevel@tonic-gate 
12512f080e7Smrj /* driver global state */
12612f080e7Smrj static rootnex_state_t *rootnex_state;
12712f080e7Smrj 
12812f080e7Smrj /* shortcut to rootnex counters */
12912f080e7Smrj static uint64_t *rootnex_cnt;
1307c478bd9Sstevel@tonic-gate 
1317c478bd9Sstevel@tonic-gate /*
13212f080e7Smrj  * XXX - does x86 even need these or are they left over from the SPARC days?
1337c478bd9Sstevel@tonic-gate  */
13412f080e7Smrj /* statically defined integer/boolean properties for the root node */
13512f080e7Smrj static rootnex_intprop_t rootnex_intprp[] = {
13612f080e7Smrj 	{ "PAGESIZE",			PAGESIZE },
13712f080e7Smrj 	{ "MMU_PAGESIZE",		MMU_PAGESIZE },
13812f080e7Smrj 	{ "MMU_PAGEOFFSET",		MMU_PAGEOFFSET },
13912f080e7Smrj 	{ DDI_RELATIVE_ADDRESSING,	1 },
14012f080e7Smrj };
14112f080e7Smrj #define	NROOT_INTPROPS	(sizeof (rootnex_intprp) / sizeof (rootnex_intprop_t))
1427c478bd9Sstevel@tonic-gate 
1437c478bd9Sstevel@tonic-gate 
14412f080e7Smrj static struct cb_ops rootnex_cb_ops = {
14512f080e7Smrj 	nodev,		/* open */
14612f080e7Smrj 	nodev,		/* close */
14712f080e7Smrj 	nodev,		/* strategy */
14812f080e7Smrj 	nodev,		/* print */
14912f080e7Smrj 	nodev,		/* dump */
15012f080e7Smrj 	nodev,		/* read */
15112f080e7Smrj 	nodev,		/* write */
15212f080e7Smrj 	nodev,		/* ioctl */
15312f080e7Smrj 	nodev,		/* devmap */
15412f080e7Smrj 	nodev,		/* mmap */
15512f080e7Smrj 	nodev,		/* segmap */
15612f080e7Smrj 	nochpoll,	/* chpoll */
15712f080e7Smrj 	ddi_prop_op,	/* cb_prop_op */
15812f080e7Smrj 	NULL,		/* struct streamtab */
15912f080e7Smrj 	D_NEW | D_MP | D_HOTPLUG, /* compatibility flags */
16012f080e7Smrj 	CB_REV,		/* Rev */
16112f080e7Smrj 	nodev,		/* cb_aread */
16212f080e7Smrj 	nodev		/* cb_awrite */
16312f080e7Smrj };
1647c478bd9Sstevel@tonic-gate 
16512f080e7Smrj static int rootnex_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
1667c478bd9Sstevel@tonic-gate     off_t offset, off_t len, caddr_t *vaddrp);
16712f080e7Smrj static int rootnex_map_fault(dev_info_t *dip, dev_info_t *rdip,
1687c478bd9Sstevel@tonic-gate     struct hat *hat, struct seg *seg, caddr_t addr,
1697c478bd9Sstevel@tonic-gate     struct devpage *dp, pfn_t pfn, uint_t prot, uint_t lock);
17012f080e7Smrj static int rootnex_dma_map(dev_info_t *dip, dev_info_t *rdip,
1717c478bd9Sstevel@tonic-gate     struct ddi_dma_req *dmareq, ddi_dma_handle_t *handlep);
17212f080e7Smrj static int rootnex_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
17312f080e7Smrj     ddi_dma_attr_t *attr, int (*waitfp)(caddr_t), caddr_t arg,
17412f080e7Smrj     ddi_dma_handle_t *handlep);
17512f080e7Smrj static int rootnex_dma_freehdl(dev_info_t *dip, dev_info_t *rdip,
17612f080e7Smrj     ddi_dma_handle_t handle);
17712f080e7Smrj static int rootnex_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
17812f080e7Smrj     ddi_dma_handle_t handle, struct ddi_dma_req *dmareq,
17912f080e7Smrj     ddi_dma_cookie_t *cookiep, uint_t *ccountp);
18012f080e7Smrj static int rootnex_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip,
18112f080e7Smrj     ddi_dma_handle_t handle);
18212f080e7Smrj static int rootnex_dma_sync(dev_info_t *dip, dev_info_t *rdip,
18312f080e7Smrj     ddi_dma_handle_t handle, off_t off, size_t len, uint_t cache_flags);
18412f080e7Smrj static int rootnex_dma_win(dev_info_t *dip, dev_info_t *rdip,
18512f080e7Smrj     ddi_dma_handle_t handle, uint_t win, off_t *offp, size_t *lenp,
18612f080e7Smrj     ddi_dma_cookie_t *cookiep, uint_t *ccountp);
18712f080e7Smrj static int rootnex_dma_mctl(dev_info_t *dip, dev_info_t *rdip,
1887c478bd9Sstevel@tonic-gate     ddi_dma_handle_t handle, enum ddi_dma_ctlops request,
1897c478bd9Sstevel@tonic-gate     off_t *offp, size_t *lenp, caddr_t *objp, uint_t cache_flags);
19012f080e7Smrj static int rootnex_ctlops(dev_info_t *dip, dev_info_t *rdip,
19112f080e7Smrj     ddi_ctl_enum_t ctlop, void *arg, void *result);
19212f080e7Smrj static int rootnex_intr_ops(dev_info_t *pdip, dev_info_t *rdip,
19312f080e7Smrj     ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result);
1947c478bd9Sstevel@tonic-gate 
1957c478bd9Sstevel@tonic-gate 
1967c478bd9Sstevel@tonic-gate static struct bus_ops rootnex_bus_ops = {
1977c478bd9Sstevel@tonic-gate 	BUSO_REV,
1987c478bd9Sstevel@tonic-gate 	rootnex_map,
1997c478bd9Sstevel@tonic-gate 	NULL,
2007c478bd9Sstevel@tonic-gate 	NULL,
2017c478bd9Sstevel@tonic-gate 	NULL,
2027c478bd9Sstevel@tonic-gate 	rootnex_map_fault,
2037c478bd9Sstevel@tonic-gate 	rootnex_dma_map,
2047c478bd9Sstevel@tonic-gate 	rootnex_dma_allochdl,
2057c478bd9Sstevel@tonic-gate 	rootnex_dma_freehdl,
2067c478bd9Sstevel@tonic-gate 	rootnex_dma_bindhdl,
2077c478bd9Sstevel@tonic-gate 	rootnex_dma_unbindhdl,
20812f080e7Smrj 	rootnex_dma_sync,
2097c478bd9Sstevel@tonic-gate 	rootnex_dma_win,
2107c478bd9Sstevel@tonic-gate 	rootnex_dma_mctl,
2117c478bd9Sstevel@tonic-gate 	rootnex_ctlops,
2127c478bd9Sstevel@tonic-gate 	ddi_bus_prop_op,
2137c478bd9Sstevel@tonic-gate 	i_ddi_rootnex_get_eventcookie,
2147c478bd9Sstevel@tonic-gate 	i_ddi_rootnex_add_eventcall,
2157c478bd9Sstevel@tonic-gate 	i_ddi_rootnex_remove_eventcall,
2167c478bd9Sstevel@tonic-gate 	i_ddi_rootnex_post_event,
2177c478bd9Sstevel@tonic-gate 	0,			/* bus_intr_ctl */
2187c478bd9Sstevel@tonic-gate 	0,			/* bus_config */
2197c478bd9Sstevel@tonic-gate 	0,			/* bus_unconfig */
2207c478bd9Sstevel@tonic-gate 	NULL,			/* bus_fm_init */
2217c478bd9Sstevel@tonic-gate 	NULL,			/* bus_fm_fini */
2227c478bd9Sstevel@tonic-gate 	NULL,			/* bus_fm_access_enter */
2237c478bd9Sstevel@tonic-gate 	NULL,			/* bus_fm_access_exit */
2247c478bd9Sstevel@tonic-gate 	NULL,			/* bus_powr */
2257c478bd9Sstevel@tonic-gate 	rootnex_intr_ops	/* bus_intr_op */
2267c478bd9Sstevel@tonic-gate };
2277c478bd9Sstevel@tonic-gate 
22812f080e7Smrj static int rootnex_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
22912f080e7Smrj static int rootnex_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
2307c478bd9Sstevel@tonic-gate 
2317c478bd9Sstevel@tonic-gate static struct dev_ops rootnex_ops = {
2327c478bd9Sstevel@tonic-gate 	DEVO_REV,
23312f080e7Smrj 	0,
23412f080e7Smrj 	ddi_no_info,
2357c478bd9Sstevel@tonic-gate 	nulldev,
23612f080e7Smrj 	nulldev,
2377c478bd9Sstevel@tonic-gate 	rootnex_attach,
23812f080e7Smrj 	rootnex_detach,
23912f080e7Smrj 	nulldev,
24012f080e7Smrj 	&rootnex_cb_ops,
2417c478bd9Sstevel@tonic-gate 	&rootnex_bus_ops
2427c478bd9Sstevel@tonic-gate };
2437c478bd9Sstevel@tonic-gate 
24412f080e7Smrj static struct modldrv rootnex_modldrv = {
24512f080e7Smrj 	&mod_driverops,
2467c478bd9Sstevel@tonic-gate 	"i86pc root nexus %I%",
24712f080e7Smrj 	&rootnex_ops
2487c478bd9Sstevel@tonic-gate };
2497c478bd9Sstevel@tonic-gate 
25012f080e7Smrj static struct modlinkage rootnex_modlinkage = {
25112f080e7Smrj 	MODREV_1,
25212f080e7Smrj 	(void *)&rootnex_modldrv,
25312f080e7Smrj 	NULL
2547c478bd9Sstevel@tonic-gate };
2557c478bd9Sstevel@tonic-gate 
2567c478bd9Sstevel@tonic-gate 
25712f080e7Smrj /*
25812f080e7Smrj  *  extern hacks
25912f080e7Smrj  */
26012f080e7Smrj extern struct seg_ops segdev_ops;
26112f080e7Smrj extern int ignore_hardware_nodes;	/* force flag from ddi_impl.c */
26212f080e7Smrj #ifdef	DDI_MAP_DEBUG
26312f080e7Smrj extern int ddi_map_debug_flag;
26412f080e7Smrj #define	ddi_map_debug	if (ddi_map_debug_flag) prom_printf
26512f080e7Smrj #endif
26612f080e7Smrj #define	ptob64(x)	(((uint64_t)(x)) << MMU_PAGESHIFT)
26712f080e7Smrj extern void i86_pp_map(page_t *pp, caddr_t kaddr);
26812f080e7Smrj extern void i86_va_map(caddr_t vaddr, struct as *asp, caddr_t kaddr);
26912f080e7Smrj extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *,
27012f080e7Smrj     psm_intr_op_t, int *);
27112f080e7Smrj extern int impl_ddi_sunbus_initchild(dev_info_t *dip);
27212f080e7Smrj extern void impl_ddi_sunbus_removechild(dev_info_t *dip);
27312f080e7Smrj /*
27412f080e7Smrj  * Use device arena to use for device control register mappings.
27512f080e7Smrj  * Various kernel memory walkers (debugger, dtrace) need to know
27612f080e7Smrj  * to avoid this address range to prevent undesired device activity.
27712f080e7Smrj  */
27812f080e7Smrj extern void *device_arena_alloc(size_t size, int vm_flag);
27912f080e7Smrj extern void device_arena_free(void * vaddr, size_t size);
28012f080e7Smrj 
28112f080e7Smrj 
28212f080e7Smrj /*
28312f080e7Smrj  *  Internal functions
28412f080e7Smrj  */
28512f080e7Smrj static int rootnex_dma_init();
28612f080e7Smrj static void rootnex_add_props(dev_info_t *);
28712f080e7Smrj static int rootnex_ctl_reportdev(dev_info_t *dip);
28812f080e7Smrj static struct intrspec *rootnex_get_ispec(dev_info_t *rdip, int inum);
28912f080e7Smrj static int rootnex_ctlops_poke(peekpoke_ctlops_t *in_args);
29012f080e7Smrj static int rootnex_ctlops_peek(peekpoke_ctlops_t *in_args, void *result);
29112f080e7Smrj static int rootnex_map_regspec(ddi_map_req_t *mp, caddr_t *vaddrp);
29212f080e7Smrj static int rootnex_unmap_regspec(ddi_map_req_t *mp, caddr_t *vaddrp);
29312f080e7Smrj static int rootnex_map_handle(ddi_map_req_t *mp);
29412f080e7Smrj static void rootnex_clean_dmahdl(ddi_dma_impl_t *hp);
29512f080e7Smrj static int rootnex_valid_alloc_parms(ddi_dma_attr_t *attr, uint_t maxsegsize);
29612f080e7Smrj static int rootnex_valid_bind_parms(ddi_dma_req_t *dmareq,
29712f080e7Smrj     ddi_dma_attr_t *attr);
29812f080e7Smrj static void rootnex_get_sgl(ddi_dma_obj_t *dmar_object, ddi_dma_cookie_t *sgl,
29912f080e7Smrj     rootnex_sglinfo_t *sglinfo);
30012f080e7Smrj static int rootnex_bind_slowpath(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq,
30112f080e7Smrj     rootnex_dma_t *dma, ddi_dma_attr_t *attr, int kmflag);
30212f080e7Smrj static int rootnex_setup_copybuf(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq,
30312f080e7Smrj     rootnex_dma_t *dma, ddi_dma_attr_t *attr);
30412f080e7Smrj static void rootnex_teardown_copybuf(rootnex_dma_t *dma);
30512f080e7Smrj static int rootnex_setup_windows(ddi_dma_impl_t *hp, rootnex_dma_t *dma,
30612f080e7Smrj     ddi_dma_attr_t *attr, int kmflag);
30712f080e7Smrj static void rootnex_teardown_windows(rootnex_dma_t *dma);
30812f080e7Smrj static void rootnex_init_win(ddi_dma_impl_t *hp, rootnex_dma_t *dma,
30912f080e7Smrj     rootnex_window_t *window, ddi_dma_cookie_t *cookie, off_t cur_offset);
31012f080e7Smrj static void rootnex_setup_cookie(ddi_dma_obj_t *dmar_object,
31112f080e7Smrj     rootnex_dma_t *dma, ddi_dma_cookie_t *cookie, off_t cur_offset,
31212f080e7Smrj     size_t *copybuf_used, page_t **cur_pp);
31312f080e7Smrj static int rootnex_sgllen_window_boundary(ddi_dma_impl_t *hp,
31412f080e7Smrj     rootnex_dma_t *dma, rootnex_window_t **windowp, ddi_dma_cookie_t *cookie,
31512f080e7Smrj     ddi_dma_attr_t *attr, off_t cur_offset);
31612f080e7Smrj static int rootnex_copybuf_window_boundary(ddi_dma_impl_t *hp,
31712f080e7Smrj     rootnex_dma_t *dma, rootnex_window_t **windowp,
31812f080e7Smrj     ddi_dma_cookie_t *cookie, off_t cur_offset, size_t *copybuf_used);
31912f080e7Smrj static int rootnex_maxxfer_window_boundary(ddi_dma_impl_t *hp,
32012f080e7Smrj     rootnex_dma_t *dma, rootnex_window_t **windowp, ddi_dma_cookie_t *cookie);
32112f080e7Smrj static int rootnex_valid_sync_parms(ddi_dma_impl_t *hp, rootnex_window_t *win,
32212f080e7Smrj     off_t offset, size_t size, uint_t cache_flags);
32312f080e7Smrj static int rootnex_verify_buffer(rootnex_dma_t *dma);
32412f080e7Smrj 
32512f080e7Smrj 
32612f080e7Smrj /*
32712f080e7Smrj  * _init()
32812f080e7Smrj  *
32912f080e7Smrj  */
3307c478bd9Sstevel@tonic-gate int
3317c478bd9Sstevel@tonic-gate _init(void)
3327c478bd9Sstevel@tonic-gate {
33312f080e7Smrj 
33412f080e7Smrj 	rootnex_state = NULL;
33512f080e7Smrj 	return (mod_install(&rootnex_modlinkage));
3367c478bd9Sstevel@tonic-gate }
3377c478bd9Sstevel@tonic-gate 
33812f080e7Smrj 
33912f080e7Smrj /*
34012f080e7Smrj  * _info()
34112f080e7Smrj  *
34212f080e7Smrj  */
34312f080e7Smrj int
34412f080e7Smrj _info(struct modinfo *modinfop)
34512f080e7Smrj {
34612f080e7Smrj 	return (mod_info(&rootnex_modlinkage, modinfop));
34712f080e7Smrj }
34812f080e7Smrj 
34912f080e7Smrj 
35012f080e7Smrj /*
35112f080e7Smrj  * _fini()
35212f080e7Smrj  *
35312f080e7Smrj  */
3547c478bd9Sstevel@tonic-gate int
3557c478bd9Sstevel@tonic-gate _fini(void)
3567c478bd9Sstevel@tonic-gate {
3577c478bd9Sstevel@tonic-gate 	return (EBUSY);
3587c478bd9Sstevel@tonic-gate }
3597c478bd9Sstevel@tonic-gate 
36012f080e7Smrj 
36112f080e7Smrj /*
36212f080e7Smrj  * rootnex_attach()
36312f080e7Smrj  *
36412f080e7Smrj  */
36512f080e7Smrj static int
36612f080e7Smrj rootnex_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
3677c478bd9Sstevel@tonic-gate {
36812f080e7Smrj 	int e;
36912f080e7Smrj 
37012f080e7Smrj 
37112f080e7Smrj 	switch (cmd) {
37212f080e7Smrj 	case DDI_ATTACH:
37312f080e7Smrj 		break;
37412f080e7Smrj 	case DDI_RESUME:
37512f080e7Smrj 		return (DDI_SUCCESS);
37612f080e7Smrj 	default:
37712f080e7Smrj 		return (DDI_FAILURE);
3787c478bd9Sstevel@tonic-gate 	}
3797c478bd9Sstevel@tonic-gate 
3807c478bd9Sstevel@tonic-gate 	/*
38112f080e7Smrj 	 * We should only have one instance of rootnex. Save it away since we
38212f080e7Smrj 	 * don't have an easy way to get it back later.
3837c478bd9Sstevel@tonic-gate 	 */
38412f080e7Smrj 	ASSERT(rootnex_state == NULL);
38512f080e7Smrj 	rootnex_state = kmem_zalloc(sizeof (rootnex_state_t), KM_SLEEP);
3867c478bd9Sstevel@tonic-gate 
38712f080e7Smrj 	rootnex_state->r_dip = dip;
38812f080e7Smrj 	rootnex_state->r_reserved_msg_printed = B_FALSE;
38912f080e7Smrj 	rootnex_cnt = &rootnex_state->r_counters[0];
3907c478bd9Sstevel@tonic-gate 
39112f080e7Smrj 	mutex_init(&rootnex_state->r_peekpoke_mutex, NULL, MUTEX_SPIN,
39212f080e7Smrj 	    (void *)ipltospl(15));
39312f080e7Smrj 
39412f080e7Smrj 	/* initialize DMA related state */
39512f080e7Smrj 	e = rootnex_dma_init();
39612f080e7Smrj 	if (e != DDI_SUCCESS) {
39712f080e7Smrj 		mutex_destroy(&rootnex_state->r_peekpoke_mutex);
39812f080e7Smrj 		kmem_free(rootnex_state, sizeof (rootnex_state_t));
39912f080e7Smrj 		return (DDI_FAILURE);
40012f080e7Smrj 	}
40112f080e7Smrj 
40212f080e7Smrj 	/* Add static root node properties */
40312f080e7Smrj 	rootnex_add_props(dip);
40412f080e7Smrj 
40512f080e7Smrj 	/* since we can't call ddi_report_dev() */
40612f080e7Smrj 	cmn_err(CE_CONT, "?root nexus = %s\n", ddi_get_name(dip));
40712f080e7Smrj 
40812f080e7Smrj 	/* Initialize rootnex event handle */
40912f080e7Smrj 	i_ddi_rootnex_init_events(dip);
41012f080e7Smrj 
41112f080e7Smrj 	return (DDI_SUCCESS);
41212f080e7Smrj }
41312f080e7Smrj 
41412f080e7Smrj 
41512f080e7Smrj /*
41612f080e7Smrj  * rootnex_detach()
41712f080e7Smrj  *
41812f080e7Smrj  */
4197c478bd9Sstevel@tonic-gate /*ARGSUSED*/
4207c478bd9Sstevel@tonic-gate static int
42112f080e7Smrj rootnex_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
4227c478bd9Sstevel@tonic-gate {
42312f080e7Smrj 	switch (cmd) {
42412f080e7Smrj 	case DDI_SUSPEND:
42512f080e7Smrj 		break;
42612f080e7Smrj 	default:
42712f080e7Smrj 		return (DDI_FAILURE);
42812f080e7Smrj 	}
4297c478bd9Sstevel@tonic-gate 
43012f080e7Smrj 	return (DDI_SUCCESS);
43112f080e7Smrj }
4327c478bd9Sstevel@tonic-gate 
4337c478bd9Sstevel@tonic-gate 
43412f080e7Smrj /*
43512f080e7Smrj  * rootnex_dma_init()
43612f080e7Smrj  *
43712f080e7Smrj  */
43812f080e7Smrj /*ARGSUSED*/
43912f080e7Smrj static int
44012f080e7Smrj rootnex_dma_init()
44112f080e7Smrj {
44212f080e7Smrj 	size_t bufsize;
44312f080e7Smrj 
44412f080e7Smrj 
44512f080e7Smrj 	/*
44612f080e7Smrj 	 * size of our cookie/window/copybuf state needed in dma bind that we
44712f080e7Smrj 	 * pre-alloc in dma_alloc_handle
44812f080e7Smrj 	 */
44912f080e7Smrj 	rootnex_state->r_prealloc_cookies = rootnex_prealloc_cookies;
45012f080e7Smrj 	rootnex_state->r_prealloc_size =
45112f080e7Smrj 	    (rootnex_state->r_prealloc_cookies * sizeof (ddi_dma_cookie_t)) +
45212f080e7Smrj 	    (rootnex_prealloc_windows * sizeof (rootnex_window_t)) +
45312f080e7Smrj 	    (rootnex_prealloc_copybuf * sizeof (rootnex_pgmap_t));
45412f080e7Smrj 
45512f080e7Smrj 	/*
45612f080e7Smrj 	 * setup DDI DMA handle kmem cache, align each handle on 64 bytes,
45712f080e7Smrj 	 * allocate 16 extra bytes for struct pointer alignment
45812f080e7Smrj 	 * (p->dmai_private & dma->dp_prealloc_buffer)
45912f080e7Smrj 	 */
46012f080e7Smrj 	bufsize = sizeof (ddi_dma_impl_t) + sizeof (rootnex_dma_t) +
46112f080e7Smrj 	    rootnex_state->r_prealloc_size + 0x10;
46212f080e7Smrj 	rootnex_state->r_dmahdl_cache = kmem_cache_create("rootnex_dmahdl",
46312f080e7Smrj 	    bufsize, 64, NULL, NULL, NULL, NULL, NULL, 0);
46412f080e7Smrj 	if (rootnex_state->r_dmahdl_cache == NULL) {
46512f080e7Smrj 		return (DDI_FAILURE);
46612f080e7Smrj 	}
4677c478bd9Sstevel@tonic-gate 
4687c478bd9Sstevel@tonic-gate 	/*
4697c478bd9Sstevel@tonic-gate 	 * allocate array to track which major numbers we have printed warnings
4707c478bd9Sstevel@tonic-gate 	 * for.
4717c478bd9Sstevel@tonic-gate 	 */
4727c478bd9Sstevel@tonic-gate 	rootnex_warn_list = kmem_zalloc(devcnt * sizeof (*rootnex_warn_list),
4737c478bd9Sstevel@tonic-gate 	    KM_SLEEP);
4747c478bd9Sstevel@tonic-gate 
4757c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
4767c478bd9Sstevel@tonic-gate }
4777c478bd9Sstevel@tonic-gate 
4787c478bd9Sstevel@tonic-gate 
4797c478bd9Sstevel@tonic-gate /*
48012f080e7Smrj  * rootnex_add_props()
48112f080e7Smrj  *
4827c478bd9Sstevel@tonic-gate  */
4837c478bd9Sstevel@tonic-gate static void
48412f080e7Smrj rootnex_add_props(dev_info_t *dip)
4857c478bd9Sstevel@tonic-gate {
48612f080e7Smrj 	rootnex_intprop_t *rpp;
4877c478bd9Sstevel@tonic-gate 	int i;
4887c478bd9Sstevel@tonic-gate 
48912f080e7Smrj 	/* Add static integer/boolean properties to the root node */
49012f080e7Smrj 	rpp = rootnex_intprp;
49112f080e7Smrj 	for (i = 0; i < NROOT_INTPROPS; i++) {
49212f080e7Smrj 		(void) e_ddi_prop_update_int(DDI_DEV_T_NONE, dip,
49312f080e7Smrj 		    rpp[i].prop_name, rpp[i].prop_value);
49412f080e7Smrj 	}
4957c478bd9Sstevel@tonic-gate }
4967c478bd9Sstevel@tonic-gate 
49712f080e7Smrj 
49812f080e7Smrj 
4997c478bd9Sstevel@tonic-gate /*
50012f080e7Smrj  * *************************
50112f080e7Smrj  *  ctlops related routines
50212f080e7Smrj  * *************************
50312f080e7Smrj  */
50412f080e7Smrj 
50512f080e7Smrj /*
50612f080e7Smrj  * rootnex_ctlops()
5077c478bd9Sstevel@tonic-gate  *
5087c478bd9Sstevel@tonic-gate  */
509a195726fSgovinda /*ARGSUSED*/
5107c478bd9Sstevel@tonic-gate static int
51112f080e7Smrj rootnex_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop,
51212f080e7Smrj     void *arg, void *result)
5137c478bd9Sstevel@tonic-gate {
51412f080e7Smrj 	int n, *ptr;
51512f080e7Smrj 	struct ddi_parent_private_data *pdp;
5167c478bd9Sstevel@tonic-gate 
51712f080e7Smrj 	switch (ctlop) {
51812f080e7Smrj 	case DDI_CTLOPS_DMAPMAPC:
5197c478bd9Sstevel@tonic-gate 		/*
52012f080e7Smrj 		 * Return 'partial' to indicate that dma mapping
52112f080e7Smrj 		 * has to be done in the main MMU.
5227c478bd9Sstevel@tonic-gate 		 */
52312f080e7Smrj 		return (DDI_DMA_PARTIAL);
5247c478bd9Sstevel@tonic-gate 
52512f080e7Smrj 	case DDI_CTLOPS_BTOP:
5267c478bd9Sstevel@tonic-gate 		/*
52712f080e7Smrj 		 * Convert byte count input to physical page units.
52812f080e7Smrj 		 * (byte counts that are not a page-size multiple
52912f080e7Smrj 		 * are rounded down)
5307c478bd9Sstevel@tonic-gate 		 */
53112f080e7Smrj 		*(ulong_t *)result = btop(*(ulong_t *)arg);
5327c478bd9Sstevel@tonic-gate 		return (DDI_SUCCESS);
5337c478bd9Sstevel@tonic-gate 
53412f080e7Smrj 	case DDI_CTLOPS_PTOB:
5357c478bd9Sstevel@tonic-gate 		/*
53612f080e7Smrj 		 * Convert size in physical pages to bytes
5377c478bd9Sstevel@tonic-gate 		 */
53812f080e7Smrj 		*(ulong_t *)result = ptob(*(ulong_t *)arg);
5397c478bd9Sstevel@tonic-gate 		return (DDI_SUCCESS);
5407c478bd9Sstevel@tonic-gate 
54112f080e7Smrj 	case DDI_CTLOPS_BTOPR:
5427c478bd9Sstevel@tonic-gate 		/*
54312f080e7Smrj 		 * Convert byte count input to physical page units
54412f080e7Smrj 		 * (byte counts that are not a page-size multiple
54512f080e7Smrj 		 * are rounded up)
5467c478bd9Sstevel@tonic-gate 		 */
54712f080e7Smrj 		*(ulong_t *)result = btopr(*(ulong_t *)arg);
54812f080e7Smrj 		return (DDI_SUCCESS);
54912f080e7Smrj 
55012f080e7Smrj 	case DDI_CTLOPS_POKE:
55112f080e7Smrj 		return (rootnex_ctlops_poke((peekpoke_ctlops_t *)arg));
55212f080e7Smrj 
55312f080e7Smrj 	case DDI_CTLOPS_PEEK:
55412f080e7Smrj 		return (rootnex_ctlops_peek((peekpoke_ctlops_t *)arg, result));
55512f080e7Smrj 
55612f080e7Smrj 	case DDI_CTLOPS_INITCHILD:
55712f080e7Smrj 		return (impl_ddi_sunbus_initchild(arg));
55812f080e7Smrj 
55912f080e7Smrj 	case DDI_CTLOPS_UNINITCHILD:
56012f080e7Smrj 		impl_ddi_sunbus_removechild(arg);
56112f080e7Smrj 		return (DDI_SUCCESS);
56212f080e7Smrj 
56312f080e7Smrj 	case DDI_CTLOPS_REPORTDEV:
56412f080e7Smrj 		return (rootnex_ctl_reportdev(rdip));
56512f080e7Smrj 
56612f080e7Smrj 	case DDI_CTLOPS_IOMIN:
5677c478bd9Sstevel@tonic-gate 		/*
56812f080e7Smrj 		 * Nothing to do here but reflect back..
5697c478bd9Sstevel@tonic-gate 		 */
5707c478bd9Sstevel@tonic-gate 		return (DDI_SUCCESS);
5717c478bd9Sstevel@tonic-gate 
57212f080e7Smrj 	case DDI_CTLOPS_REGSIZE:
57312f080e7Smrj 	case DDI_CTLOPS_NREGS:
57412f080e7Smrj 		break;
5757c478bd9Sstevel@tonic-gate 
57612f080e7Smrj 	case DDI_CTLOPS_SIDDEV:
57712f080e7Smrj 		if (ndi_dev_is_prom_node(rdip))
5787c478bd9Sstevel@tonic-gate 			return (DDI_SUCCESS);
57912f080e7Smrj 		if (ndi_dev_is_persistent_node(rdip))
58012f080e7Smrj 			return (DDI_SUCCESS);
5817c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
5827c478bd9Sstevel@tonic-gate 
58312f080e7Smrj 	case DDI_CTLOPS_POWER:
58412f080e7Smrj 		return ((*pm_platform_power)((power_req_t *)arg));
58512f080e7Smrj 
586a195726fSgovinda 	case DDI_CTLOPS_RESERVED0: /* Was DDI_CTLOPS_NINTRS, obsolete */
58712f080e7Smrj 	case DDI_CTLOPS_RESERVED1: /* Was DDI_CTLOPS_POKE_INIT, obsolete */
58812f080e7Smrj 	case DDI_CTLOPS_RESERVED2: /* Was DDI_CTLOPS_POKE_FLUSH, obsolete */
58912f080e7Smrj 	case DDI_CTLOPS_RESERVED3: /* Was DDI_CTLOPS_POKE_FINI, obsolete */
590a195726fSgovinda 	case DDI_CTLOPS_RESERVED4: /* Was DDI_CTLOPS_INTR_HILEVEL, obsolete */
591a195726fSgovinda 	case DDI_CTLOPS_RESERVED5: /* Was DDI_CTLOPS_XLATE_INTRS, obsolete */
59212f080e7Smrj 		if (!rootnex_state->r_reserved_msg_printed) {
59312f080e7Smrj 			rootnex_state->r_reserved_msg_printed = B_TRUE;
59412f080e7Smrj 			cmn_err(CE_WARN, "Failing ddi_ctlops call(s) for "
59512f080e7Smrj 			    "1 or more reserved/obsolete operations.");
5967c478bd9Sstevel@tonic-gate 		}
59712f080e7Smrj 		return (DDI_FAILURE);
5987c478bd9Sstevel@tonic-gate 
5997c478bd9Sstevel@tonic-gate 	default:
6007c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
6017c478bd9Sstevel@tonic-gate 	}
60212f080e7Smrj 	/*
60312f080e7Smrj 	 * The rest are for "hardware" properties
60412f080e7Smrj 	 */
60512f080e7Smrj 	if ((pdp = ddi_get_parent_data(rdip)) == NULL)
60612f080e7Smrj 		return (DDI_FAILURE);
6077c478bd9Sstevel@tonic-gate 
60812f080e7Smrj 	if (ctlop == DDI_CTLOPS_NREGS) {
60912f080e7Smrj 		ptr = (int *)result;
61012f080e7Smrj 		*ptr = pdp->par_nreg;
61112f080e7Smrj 	} else {
61212f080e7Smrj 		off_t *size = (off_t *)result;
6137c478bd9Sstevel@tonic-gate 
61412f080e7Smrj 		ptr = (int *)arg;
61512f080e7Smrj 		n = *ptr;
61612f080e7Smrj 		if (n >= pdp->par_nreg) {
61712f080e7Smrj 			return (DDI_FAILURE);
61812f080e7Smrj 		}
61912f080e7Smrj 		*size = (off_t)pdp->par_reg[n].regspec_size;
62012f080e7Smrj 	}
6217c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
6227c478bd9Sstevel@tonic-gate }
6237c478bd9Sstevel@tonic-gate 
62412f080e7Smrj 
62512f080e7Smrj /*
62612f080e7Smrj  * rootnex_ctl_reportdev()
62712f080e7Smrj  *
62812f080e7Smrj  */
6297c478bd9Sstevel@tonic-gate static int
63012f080e7Smrj rootnex_ctl_reportdev(dev_info_t *dev)
63112f080e7Smrj {
63212f080e7Smrj 	int i, n, len, f_len = 0;
63312f080e7Smrj 	char *buf;
63412f080e7Smrj 
63512f080e7Smrj 	buf = kmem_alloc(REPORTDEV_BUFSIZE, KM_SLEEP);
63612f080e7Smrj 	f_len += snprintf(buf, REPORTDEV_BUFSIZE,
63712f080e7Smrj 	    "%s%d at root", ddi_driver_name(dev), ddi_get_instance(dev));
63812f080e7Smrj 	len = strlen(buf);
63912f080e7Smrj 
64012f080e7Smrj 	for (i = 0; i < sparc_pd_getnreg(dev); i++) {
64112f080e7Smrj 
64212f080e7Smrj 		struct regspec *rp = sparc_pd_getreg(dev, i);
64312f080e7Smrj 
64412f080e7Smrj 		if (i == 0)
64512f080e7Smrj 			f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len,
64612f080e7Smrj 			    ": ");
64712f080e7Smrj 		else
64812f080e7Smrj 			f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len,
64912f080e7Smrj 			    " and ");
65012f080e7Smrj 		len = strlen(buf);
65112f080e7Smrj 
65212f080e7Smrj 		switch (rp->regspec_bustype) {
65312f080e7Smrj 
65412f080e7Smrj 		case BTEISA:
65512f080e7Smrj 			f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len,
65612f080e7Smrj 			    "%s 0x%x", DEVI_EISA_NEXNAME, rp->regspec_addr);
65712f080e7Smrj 			break;
65812f080e7Smrj 
65912f080e7Smrj 		case BTISA:
66012f080e7Smrj 			f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len,
66112f080e7Smrj 			    "%s 0x%x", DEVI_ISA_NEXNAME, rp->regspec_addr);
66212f080e7Smrj 			break;
66312f080e7Smrj 
66412f080e7Smrj 		default:
66512f080e7Smrj 			f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len,
66612f080e7Smrj 			    "space %x offset %x",
66712f080e7Smrj 			    rp->regspec_bustype, rp->regspec_addr);
66812f080e7Smrj 			break;
66912f080e7Smrj 		}
67012f080e7Smrj 		len = strlen(buf);
67112f080e7Smrj 	}
67212f080e7Smrj 	for (i = 0, n = sparc_pd_getnintr(dev); i < n; i++) {
67312f080e7Smrj 		int pri;
67412f080e7Smrj 
67512f080e7Smrj 		if (i != 0) {
67612f080e7Smrj 			f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len,
67712f080e7Smrj 			    ",");
67812f080e7Smrj 			len = strlen(buf);
67912f080e7Smrj 		}
68012f080e7Smrj 		pri = INT_IPL(sparc_pd_getintr(dev, i)->intrspec_pri);
68112f080e7Smrj 		f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len,
68212f080e7Smrj 		    " sparc ipl %d", pri);
68312f080e7Smrj 		len = strlen(buf);
68412f080e7Smrj 	}
68512f080e7Smrj #ifdef DEBUG
68612f080e7Smrj 	if (f_len + 1 >= REPORTDEV_BUFSIZE) {
68712f080e7Smrj 		cmn_err(CE_NOTE, "next message is truncated: "
68812f080e7Smrj 		    "printed length 1024, real length %d", f_len);
68912f080e7Smrj 	}
69012f080e7Smrj #endif /* DEBUG */
69112f080e7Smrj 	cmn_err(CE_CONT, "?%s\n", buf);
69212f080e7Smrj 	kmem_free(buf, REPORTDEV_BUFSIZE);
69312f080e7Smrj 	return (DDI_SUCCESS);
69412f080e7Smrj }
69512f080e7Smrj 
69612f080e7Smrj 
69712f080e7Smrj /*
69812f080e7Smrj  * rootnex_ctlops_poke()
69912f080e7Smrj  *
70012f080e7Smrj  */
70112f080e7Smrj static int
70212f080e7Smrj rootnex_ctlops_poke(peekpoke_ctlops_t *in_args)
70312f080e7Smrj {
70412f080e7Smrj 	int err = DDI_SUCCESS;
70512f080e7Smrj 	on_trap_data_t otd;
70612f080e7Smrj 
70712f080e7Smrj 	/* Cautious access not supported. */
70812f080e7Smrj 	if (in_args->handle != NULL)
70912f080e7Smrj 		return (DDI_FAILURE);
71012f080e7Smrj 
71112f080e7Smrj 	mutex_enter(&rootnex_state->r_peekpoke_mutex);
71212f080e7Smrj 
71312f080e7Smrj 	/* Set up protected environment. */
71412f080e7Smrj 	if (!on_trap(&otd, OT_DATA_ACCESS)) {
71512f080e7Smrj 		switch (in_args->size) {
71612f080e7Smrj 		case sizeof (uint8_t):
71712f080e7Smrj 			*(uint8_t *)in_args->dev_addr = *(uint8_t *)
71812f080e7Smrj 			    in_args->host_addr;
71912f080e7Smrj 			break;
72012f080e7Smrj 
72112f080e7Smrj 		case sizeof (uint16_t):
72212f080e7Smrj 			*(uint16_t *)in_args->dev_addr =
72312f080e7Smrj 			    *(uint16_t *)in_args->host_addr;
72412f080e7Smrj 			break;
72512f080e7Smrj 
72612f080e7Smrj 		case sizeof (uint32_t):
72712f080e7Smrj 			*(uint32_t *)in_args->dev_addr =
72812f080e7Smrj 			    *(uint32_t *)in_args->host_addr;
72912f080e7Smrj 			break;
73012f080e7Smrj 
73112f080e7Smrj 		case sizeof (uint64_t):
73212f080e7Smrj 			*(uint64_t *)in_args->dev_addr =
73312f080e7Smrj 			    *(uint64_t *)in_args->host_addr;
73412f080e7Smrj 			break;
73512f080e7Smrj 
73612f080e7Smrj 		default:
73712f080e7Smrj 			err = DDI_FAILURE;
73812f080e7Smrj 			break;
73912f080e7Smrj 		}
74012f080e7Smrj 	} else
74112f080e7Smrj 		err = DDI_FAILURE;
74212f080e7Smrj 
74312f080e7Smrj 	/* Take down protected environment. */
74412f080e7Smrj 	no_trap();
74512f080e7Smrj 	mutex_exit(&rootnex_state->r_peekpoke_mutex);
74612f080e7Smrj 
74712f080e7Smrj 	return (err);
74812f080e7Smrj }
74912f080e7Smrj 
75012f080e7Smrj 
75112f080e7Smrj /*
75212f080e7Smrj  * rootnex_ctlops_peek()
75312f080e7Smrj  *
75412f080e7Smrj  */
75512f080e7Smrj static int
75612f080e7Smrj rootnex_ctlops_peek(peekpoke_ctlops_t *in_args, void *result)
75712f080e7Smrj {
75812f080e7Smrj 	int err = DDI_SUCCESS;
75912f080e7Smrj 	on_trap_data_t otd;
76012f080e7Smrj 
76112f080e7Smrj 	/* Cautious access not supported. */
76212f080e7Smrj 	if (in_args->handle != NULL)
76312f080e7Smrj 		return (DDI_FAILURE);
76412f080e7Smrj 
76512f080e7Smrj 	mutex_enter(&rootnex_state->r_peekpoke_mutex);
76612f080e7Smrj 
76712f080e7Smrj 	if (!on_trap(&otd, OT_DATA_ACCESS)) {
76812f080e7Smrj 		switch (in_args->size) {
76912f080e7Smrj 		case sizeof (uint8_t):
77012f080e7Smrj 			*(uint8_t *)in_args->host_addr =
77112f080e7Smrj 			    *(uint8_t *)in_args->dev_addr;
77212f080e7Smrj 			break;
77312f080e7Smrj 
77412f080e7Smrj 		case sizeof (uint16_t):
77512f080e7Smrj 			*(uint16_t *)in_args->host_addr =
77612f080e7Smrj 			    *(uint16_t *)in_args->dev_addr;
77712f080e7Smrj 			break;
77812f080e7Smrj 
77912f080e7Smrj 		case sizeof (uint32_t):
78012f080e7Smrj 			*(uint32_t *)in_args->host_addr =
78112f080e7Smrj 			    *(uint32_t *)in_args->dev_addr;
78212f080e7Smrj 			break;
78312f080e7Smrj 
78412f080e7Smrj 		case sizeof (uint64_t):
78512f080e7Smrj 			*(uint64_t *)in_args->host_addr =
78612f080e7Smrj 			    *(uint64_t *)in_args->dev_addr;
78712f080e7Smrj 			break;
78812f080e7Smrj 
78912f080e7Smrj 		default:
79012f080e7Smrj 			err = DDI_FAILURE;
79112f080e7Smrj 			break;
79212f080e7Smrj 		}
79312f080e7Smrj 		result = (void *)in_args->host_addr;
79412f080e7Smrj 	} else
79512f080e7Smrj 		err = DDI_FAILURE;
79612f080e7Smrj 
79712f080e7Smrj 	no_trap();
79812f080e7Smrj 	mutex_exit(&rootnex_state->r_peekpoke_mutex);
79912f080e7Smrj 
80012f080e7Smrj 	return (err);
80112f080e7Smrj }
80212f080e7Smrj 
80312f080e7Smrj 
80412f080e7Smrj 
80512f080e7Smrj /*
80612f080e7Smrj  * ******************
80712f080e7Smrj  *  map related code
80812f080e7Smrj  * ******************
80912f080e7Smrj  */
81012f080e7Smrj 
81112f080e7Smrj /*
81212f080e7Smrj  * rootnex_map()
81312f080e7Smrj  *
81412f080e7Smrj  */
81512f080e7Smrj static int
81612f080e7Smrj rootnex_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, off_t offset,
81712f080e7Smrj     off_t len, caddr_t *vaddrp)
8187c478bd9Sstevel@tonic-gate {
8197c478bd9Sstevel@tonic-gate 	struct regspec *rp, tmp_reg;
8207c478bd9Sstevel@tonic-gate 	ddi_map_req_t mr = *mp;		/* Get private copy of request */
8217c478bd9Sstevel@tonic-gate 	int error;
8227c478bd9Sstevel@tonic-gate 
8237c478bd9Sstevel@tonic-gate 	mp = &mr;
8247c478bd9Sstevel@tonic-gate 
8257c478bd9Sstevel@tonic-gate 	switch (mp->map_op)  {
8267c478bd9Sstevel@tonic-gate 	case DDI_MO_MAP_LOCKED:
8277c478bd9Sstevel@tonic-gate 	case DDI_MO_UNMAP:
8287c478bd9Sstevel@tonic-gate 	case DDI_MO_MAP_HANDLE:
8297c478bd9Sstevel@tonic-gate 		break;
8307c478bd9Sstevel@tonic-gate 	default:
8317c478bd9Sstevel@tonic-gate #ifdef	DDI_MAP_DEBUG
8327c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "rootnex_map: unimplemented map op %d.",
8337c478bd9Sstevel@tonic-gate 		    mp->map_op);
8347c478bd9Sstevel@tonic-gate #endif	/* DDI_MAP_DEBUG */
8357c478bd9Sstevel@tonic-gate 		return (DDI_ME_UNIMPLEMENTED);
8367c478bd9Sstevel@tonic-gate 	}
8377c478bd9Sstevel@tonic-gate 
8387c478bd9Sstevel@tonic-gate 	if (mp->map_flags & DDI_MF_USER_MAPPING)  {
8397c478bd9Sstevel@tonic-gate #ifdef	DDI_MAP_DEBUG
8407c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "rootnex_map: unimplemented map type: user.");
8417c478bd9Sstevel@tonic-gate #endif	/* DDI_MAP_DEBUG */
8427c478bd9Sstevel@tonic-gate 		return (DDI_ME_UNIMPLEMENTED);
8437c478bd9Sstevel@tonic-gate 	}
8447c478bd9Sstevel@tonic-gate 
8457c478bd9Sstevel@tonic-gate 	/*
8467c478bd9Sstevel@tonic-gate 	 * First, if given an rnumber, convert it to a regspec...
8477c478bd9Sstevel@tonic-gate 	 * (Presumably, this is on behalf of a child of the root node?)
8487c478bd9Sstevel@tonic-gate 	 */
8497c478bd9Sstevel@tonic-gate 
8507c478bd9Sstevel@tonic-gate 	if (mp->map_type == DDI_MT_RNUMBER)  {
8517c478bd9Sstevel@tonic-gate 
8527c478bd9Sstevel@tonic-gate 		int rnumber = mp->map_obj.rnumber;
8537c478bd9Sstevel@tonic-gate #ifdef	DDI_MAP_DEBUG
8547c478bd9Sstevel@tonic-gate 		static char *out_of_range =
8557c478bd9Sstevel@tonic-gate 		    "rootnex_map: Out of range rnumber <%d>, device <%s>";
8567c478bd9Sstevel@tonic-gate #endif	/* DDI_MAP_DEBUG */
8577c478bd9Sstevel@tonic-gate 
8587c478bd9Sstevel@tonic-gate 		rp = i_ddi_rnumber_to_regspec(rdip, rnumber);
8597c478bd9Sstevel@tonic-gate 		if (rp == NULL)  {
8607c478bd9Sstevel@tonic-gate #ifdef	DDI_MAP_DEBUG
8617c478bd9Sstevel@tonic-gate 			cmn_err(CE_WARN, out_of_range, rnumber,
8627c478bd9Sstevel@tonic-gate 			    ddi_get_name(rdip));
8637c478bd9Sstevel@tonic-gate #endif	/* DDI_MAP_DEBUG */
8647c478bd9Sstevel@tonic-gate 			return (DDI_ME_RNUMBER_RANGE);
8657c478bd9Sstevel@tonic-gate 		}
8667c478bd9Sstevel@tonic-gate 
8677c478bd9Sstevel@tonic-gate 		/*
8687c478bd9Sstevel@tonic-gate 		 * Convert the given ddi_map_req_t from rnumber to regspec...
8697c478bd9Sstevel@tonic-gate 		 */
8707c478bd9Sstevel@tonic-gate 
8717c478bd9Sstevel@tonic-gate 		mp->map_type = DDI_MT_REGSPEC;
8727c478bd9Sstevel@tonic-gate 		mp->map_obj.rp = rp;
8737c478bd9Sstevel@tonic-gate 	}
8747c478bd9Sstevel@tonic-gate 
8757c478bd9Sstevel@tonic-gate 	/*
8767c478bd9Sstevel@tonic-gate 	 * Adjust offset and length correspnding to called values...
8777c478bd9Sstevel@tonic-gate 	 * XXX: A non-zero length means override the one in the regspec
8787c478bd9Sstevel@tonic-gate 	 * XXX: (regardless of what's in the parent's range?)
8797c478bd9Sstevel@tonic-gate 	 */
8807c478bd9Sstevel@tonic-gate 
8817c478bd9Sstevel@tonic-gate 	tmp_reg = *(mp->map_obj.rp);		/* Preserve underlying data */
8827c478bd9Sstevel@tonic-gate 	rp = mp->map_obj.rp = &tmp_reg;		/* Use tmp_reg in request */
8837c478bd9Sstevel@tonic-gate 
8847c478bd9Sstevel@tonic-gate #ifdef	DDI_MAP_DEBUG
8857c478bd9Sstevel@tonic-gate 	cmn_err(CE_CONT,
8867c478bd9Sstevel@tonic-gate 		"rootnex: <%s,%s> <0x%x, 0x%x, 0x%d>"
8877c478bd9Sstevel@tonic-gate 		" offset %d len %d handle 0x%x\n",
8887c478bd9Sstevel@tonic-gate 		ddi_get_name(dip), ddi_get_name(rdip),
8897c478bd9Sstevel@tonic-gate 		rp->regspec_bustype, rp->regspec_addr, rp->regspec_size,
8907c478bd9Sstevel@tonic-gate 		offset, len, mp->map_handlep);
8917c478bd9Sstevel@tonic-gate #endif	/* DDI_MAP_DEBUG */
8927c478bd9Sstevel@tonic-gate 
8937c478bd9Sstevel@tonic-gate 	/*
8947c478bd9Sstevel@tonic-gate 	 * I/O or memory mapping:
8957c478bd9Sstevel@tonic-gate 	 *
8967c478bd9Sstevel@tonic-gate 	 *	<bustype=0, addr=x, len=x>: memory
8977c478bd9Sstevel@tonic-gate 	 *	<bustype=1, addr=x, len=x>: i/o
8987c478bd9Sstevel@tonic-gate 	 *	<bustype>1, addr=0, len=x>: x86-compatibility i/o
8997c478bd9Sstevel@tonic-gate 	 */
9007c478bd9Sstevel@tonic-gate 
9017c478bd9Sstevel@tonic-gate 	if (rp->regspec_bustype > 1 && rp->regspec_addr != 0) {
9027c478bd9Sstevel@tonic-gate 		cmn_err(CE_WARN, "<%s,%s> invalid register spec"
9037c478bd9Sstevel@tonic-gate 		    " <0x%x, 0x%x, 0x%x>", ddi_get_name(dip),
9047c478bd9Sstevel@tonic-gate 		    ddi_get_name(rdip), rp->regspec_bustype,
9057c478bd9Sstevel@tonic-gate 		    rp->regspec_addr, rp->regspec_size);
9067c478bd9Sstevel@tonic-gate 		return (DDI_ME_INVAL);
9077c478bd9Sstevel@tonic-gate 	}
9087c478bd9Sstevel@tonic-gate 
9097c478bd9Sstevel@tonic-gate 	if (rp->regspec_bustype > 1 && rp->regspec_addr == 0) {
9107c478bd9Sstevel@tonic-gate 		/*
9117c478bd9Sstevel@tonic-gate 		 * compatibility i/o mapping
9127c478bd9Sstevel@tonic-gate 		 */
9137c478bd9Sstevel@tonic-gate 		rp->regspec_bustype += (uint_t)offset;
9147c478bd9Sstevel@tonic-gate 	} else {
9157c478bd9Sstevel@tonic-gate 		/*
9167c478bd9Sstevel@tonic-gate 		 * Normal memory or i/o mapping
9177c478bd9Sstevel@tonic-gate 		 */
9187c478bd9Sstevel@tonic-gate 		rp->regspec_addr += (uint_t)offset;
9197c478bd9Sstevel@tonic-gate 	}
9207c478bd9Sstevel@tonic-gate 
9217c478bd9Sstevel@tonic-gate 	if (len != 0)
9227c478bd9Sstevel@tonic-gate 		rp->regspec_size = (uint_t)len;
9237c478bd9Sstevel@tonic-gate 
9247c478bd9Sstevel@tonic-gate #ifdef	DDI_MAP_DEBUG
9257c478bd9Sstevel@tonic-gate 	cmn_err(CE_CONT,
9267c478bd9Sstevel@tonic-gate 		"             <%s,%s> <0x%x, 0x%x, 0x%d>"
9277c478bd9Sstevel@tonic-gate 		" offset %d len %d handle 0x%x\n",
9287c478bd9Sstevel@tonic-gate 		ddi_get_name(dip), ddi_get_name(rdip),
9297c478bd9Sstevel@tonic-gate 		rp->regspec_bustype, rp->regspec_addr, rp->regspec_size,
9307c478bd9Sstevel@tonic-gate 		offset, len, mp->map_handlep);
9317c478bd9Sstevel@tonic-gate #endif	/* DDI_MAP_DEBUG */
9327c478bd9Sstevel@tonic-gate 
9337c478bd9Sstevel@tonic-gate 	/*
9347c478bd9Sstevel@tonic-gate 	 * Apply any parent ranges at this level, if applicable.
9357c478bd9Sstevel@tonic-gate 	 * (This is where nexus specific regspec translation takes place.
9367c478bd9Sstevel@tonic-gate 	 * Use of this function is implicit agreement that translation is
9377c478bd9Sstevel@tonic-gate 	 * provided via ddi_apply_range.)
9387c478bd9Sstevel@tonic-gate 	 */
9397c478bd9Sstevel@tonic-gate 
9407c478bd9Sstevel@tonic-gate #ifdef	DDI_MAP_DEBUG
9417c478bd9Sstevel@tonic-gate 	ddi_map_debug("applying range of parent <%s> to child <%s>...\n",
9427c478bd9Sstevel@tonic-gate 	    ddi_get_name(dip), ddi_get_name(rdip));
9437c478bd9Sstevel@tonic-gate #endif	/* DDI_MAP_DEBUG */
9447c478bd9Sstevel@tonic-gate 
9457c478bd9Sstevel@tonic-gate 	if ((error = i_ddi_apply_range(dip, rdip, mp->map_obj.rp)) != 0)
9467c478bd9Sstevel@tonic-gate 		return (error);
9477c478bd9Sstevel@tonic-gate 
9487c478bd9Sstevel@tonic-gate 	switch (mp->map_op)  {
9497c478bd9Sstevel@tonic-gate 	case DDI_MO_MAP_LOCKED:
9507c478bd9Sstevel@tonic-gate 
9517c478bd9Sstevel@tonic-gate 		/*
9527c478bd9Sstevel@tonic-gate 		 * Set up the locked down kernel mapping to the regspec...
9537c478bd9Sstevel@tonic-gate 		 */
9547c478bd9Sstevel@tonic-gate 
9557c478bd9Sstevel@tonic-gate 		return (rootnex_map_regspec(mp, vaddrp));
9567c478bd9Sstevel@tonic-gate 
9577c478bd9Sstevel@tonic-gate 	case DDI_MO_UNMAP:
9587c478bd9Sstevel@tonic-gate 
9597c478bd9Sstevel@tonic-gate 		/*
9607c478bd9Sstevel@tonic-gate 		 * Release mapping...
9617c478bd9Sstevel@tonic-gate 		 */
9627c478bd9Sstevel@tonic-gate 
9637c478bd9Sstevel@tonic-gate 		return (rootnex_unmap_regspec(mp, vaddrp));
9647c478bd9Sstevel@tonic-gate 
9657c478bd9Sstevel@tonic-gate 	case DDI_MO_MAP_HANDLE:
9667c478bd9Sstevel@tonic-gate 
9677c478bd9Sstevel@tonic-gate 		return (rootnex_map_handle(mp));
9687c478bd9Sstevel@tonic-gate 
9697c478bd9Sstevel@tonic-gate 	default:
9707c478bd9Sstevel@tonic-gate 		return (DDI_ME_UNIMPLEMENTED);
9717c478bd9Sstevel@tonic-gate 	}
9727c478bd9Sstevel@tonic-gate }
9737c478bd9Sstevel@tonic-gate 
9747c478bd9Sstevel@tonic-gate 
9757c478bd9Sstevel@tonic-gate /*
97612f080e7Smrj  * rootnex_map_fault()
9777c478bd9Sstevel@tonic-gate  *
9787c478bd9Sstevel@tonic-gate  *	fault in mappings for requestors
9797c478bd9Sstevel@tonic-gate  */
9807c478bd9Sstevel@tonic-gate /*ARGSUSED*/
9817c478bd9Sstevel@tonic-gate static int
98212f080e7Smrj rootnex_map_fault(dev_info_t *dip, dev_info_t *rdip, struct hat *hat,
98312f080e7Smrj     struct seg *seg, caddr_t addr, struct devpage *dp, pfn_t pfn, uint_t prot,
98412f080e7Smrj     uint_t lock)
9857c478bd9Sstevel@tonic-gate {
9867c478bd9Sstevel@tonic-gate 
9877c478bd9Sstevel@tonic-gate #ifdef	DDI_MAP_DEBUG
9887c478bd9Sstevel@tonic-gate 	ddi_map_debug("rootnex_map_fault: address <%x> pfn <%x>", addr, pfn);
9897c478bd9Sstevel@tonic-gate 	ddi_map_debug(" Seg <%s>\n",
9907c478bd9Sstevel@tonic-gate 	    seg->s_ops == &segdev_ops ? "segdev" :
9917c478bd9Sstevel@tonic-gate 	    seg == &kvseg ? "segkmem" : "NONE!");
9927c478bd9Sstevel@tonic-gate #endif	/* DDI_MAP_DEBUG */
9937c478bd9Sstevel@tonic-gate 
9947c478bd9Sstevel@tonic-gate 	/*
9957c478bd9Sstevel@tonic-gate 	 * This is all terribly broken, but it is a start
9967c478bd9Sstevel@tonic-gate 	 *
9977c478bd9Sstevel@tonic-gate 	 * XXX	Note that this test means that segdev_ops
9987c478bd9Sstevel@tonic-gate 	 *	must be exported from seg_dev.c.
9997c478bd9Sstevel@tonic-gate 	 * XXX	What about devices with their own segment drivers?
10007c478bd9Sstevel@tonic-gate 	 */
10017c478bd9Sstevel@tonic-gate 	if (seg->s_ops == &segdev_ops) {
10027c478bd9Sstevel@tonic-gate 		struct segdev_data *sdp =
10037c478bd9Sstevel@tonic-gate 			(struct segdev_data *)seg->s_data;
10047c478bd9Sstevel@tonic-gate 
10057c478bd9Sstevel@tonic-gate 		if (hat == NULL) {
10067c478bd9Sstevel@tonic-gate 			/*
10077c478bd9Sstevel@tonic-gate 			 * This is one plausible interpretation of
10087c478bd9Sstevel@tonic-gate 			 * a null hat i.e. use the first hat on the
10097c478bd9Sstevel@tonic-gate 			 * address space hat list which by convention is
10107c478bd9Sstevel@tonic-gate 			 * the hat of the system MMU.  At alternative
10117c478bd9Sstevel@tonic-gate 			 * would be to panic .. this might well be better ..
10127c478bd9Sstevel@tonic-gate 			 */
10137c478bd9Sstevel@tonic-gate 			ASSERT(AS_READ_HELD(seg->s_as, &seg->s_as->a_lock));
10147c478bd9Sstevel@tonic-gate 			hat = seg->s_as->a_hat;
10157c478bd9Sstevel@tonic-gate 			cmn_err(CE_NOTE, "rootnex_map_fault: nil hat");
10167c478bd9Sstevel@tonic-gate 		}
10177c478bd9Sstevel@tonic-gate 		hat_devload(hat, addr, MMU_PAGESIZE, pfn, prot | sdp->hat_attr,
10187c478bd9Sstevel@tonic-gate 		    (lock ? HAT_LOAD_LOCK : HAT_LOAD));
10197c478bd9Sstevel@tonic-gate 	} else if (seg == &kvseg && dp == NULL) {
10207c478bd9Sstevel@tonic-gate 		hat_devload(kas.a_hat, addr, MMU_PAGESIZE, pfn, prot,
10217c478bd9Sstevel@tonic-gate 		    HAT_LOAD_LOCK);
10227c478bd9Sstevel@tonic-gate 	} else
10237c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
10247c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
10257c478bd9Sstevel@tonic-gate }
10267c478bd9Sstevel@tonic-gate 
10277c478bd9Sstevel@tonic-gate 
10287c478bd9Sstevel@tonic-gate /*
102912f080e7Smrj  * rootnex_map_regspec()
103012f080e7Smrj  *     we don't support mapping of I/O cards above 4Gb
10317c478bd9Sstevel@tonic-gate  */
10327c478bd9Sstevel@tonic-gate static int
103312f080e7Smrj rootnex_map_regspec(ddi_map_req_t *mp, caddr_t *vaddrp)
10347c478bd9Sstevel@tonic-gate {
103512f080e7Smrj 	ulong_t base;
103612f080e7Smrj 	void *cvaddr;
103712f080e7Smrj 	uint_t npages, pgoffset;
103812f080e7Smrj 	struct regspec *rp;
103912f080e7Smrj 	ddi_acc_hdl_t *hp;
104012f080e7Smrj 	ddi_acc_impl_t *ap;
104112f080e7Smrj 	uint_t	hat_acc_flags;
10427c478bd9Sstevel@tonic-gate 
104312f080e7Smrj 	rp = mp->map_obj.rp;
104412f080e7Smrj 	hp = mp->map_handlep;
104512f080e7Smrj 
104612f080e7Smrj #ifdef	DDI_MAP_DEBUG
104712f080e7Smrj 	ddi_map_debug(
104812f080e7Smrj 	    "rootnex_map_regspec: <0x%x 0x%x 0x%x> handle 0x%x\n",
104912f080e7Smrj 	    rp->regspec_bustype, rp->regspec_addr,
105012f080e7Smrj 	    rp->regspec_size, mp->map_handlep);
105112f080e7Smrj #endif	/* DDI_MAP_DEBUG */
10527c478bd9Sstevel@tonic-gate 
10537c478bd9Sstevel@tonic-gate 	/*
105412f080e7Smrj 	 * I/O or memory mapping
105512f080e7Smrj 	 *
105612f080e7Smrj 	 *	<bustype=0, addr=x, len=x>: memory
105712f080e7Smrj 	 *	<bustype=1, addr=x, len=x>: i/o
105812f080e7Smrj 	 *	<bustype>1, addr=0, len=x>: x86-compatibility i/o
10597c478bd9Sstevel@tonic-gate 	 */
106012f080e7Smrj 
106112f080e7Smrj 	if (rp->regspec_bustype > 1 && rp->regspec_addr != 0) {
106212f080e7Smrj 		cmn_err(CE_WARN, "rootnex: invalid register spec"
106312f080e7Smrj 		    " <0x%x, 0x%x, 0x%x>", rp->regspec_bustype,
106412f080e7Smrj 		    rp->regspec_addr, rp->regspec_size);
106512f080e7Smrj 		return (DDI_FAILURE);
10667c478bd9Sstevel@tonic-gate 	}
106712f080e7Smrj 
106812f080e7Smrj 	if (rp->regspec_bustype != 0) {
10697c478bd9Sstevel@tonic-gate 		/*
107012f080e7Smrj 		 * I/O space - needs a handle.
10717c478bd9Sstevel@tonic-gate 		 */
10727c478bd9Sstevel@tonic-gate 		if (hp == NULL) {
107312f080e7Smrj 			return (DDI_FAILURE);
10747c478bd9Sstevel@tonic-gate 		}
107512f080e7Smrj 		ap = (ddi_acc_impl_t *)hp->ah_platform_private;
107612f080e7Smrj 		ap->ahi_acc_attr |= DDI_ACCATTR_IO_SPACE;
107712f080e7Smrj 		impl_acc_hdl_init(hp);
10787c478bd9Sstevel@tonic-gate 
107912f080e7Smrj 		if (mp->map_flags & DDI_MF_DEVICE_MAPPING) {
108012f080e7Smrj #ifdef  DDI_MAP_DEBUG
108112f080e7Smrj 			ddi_map_debug("rootnex_map_regspec: mmap() \
108212f080e7Smrj to I/O space is not supported.\n");
108312f080e7Smrj #endif  /* DDI_MAP_DEBUG */
108412f080e7Smrj 			return (DDI_ME_INVAL);
10857c478bd9Sstevel@tonic-gate 		} else {
10867c478bd9Sstevel@tonic-gate 			/*
108712f080e7Smrj 			 * 1275-compliant vs. compatibility i/o mapping
10887c478bd9Sstevel@tonic-gate 			 */
108912f080e7Smrj 			*vaddrp =
109012f080e7Smrj 			    (rp->regspec_bustype > 1 && rp->regspec_addr == 0) ?
109112f080e7Smrj 				((caddr_t)(uintptr_t)rp->regspec_bustype) :
109212f080e7Smrj 				((caddr_t)(uintptr_t)rp->regspec_addr);
10937c478bd9Sstevel@tonic-gate 		}
10947c478bd9Sstevel@tonic-gate 
109512f080e7Smrj #ifdef	DDI_MAP_DEBUG
109612f080e7Smrj 		ddi_map_debug(
109712f080e7Smrj 	    "rootnex_map_regspec: \"Mapping\" %d bytes I/O space at 0x%x\n",
109812f080e7Smrj 		    rp->regspec_size, *vaddrp);
109912f080e7Smrj #endif	/* DDI_MAP_DEBUG */
110012f080e7Smrj 		return (DDI_SUCCESS);
11017c478bd9Sstevel@tonic-gate 	}
11027c478bd9Sstevel@tonic-gate 
11037c478bd9Sstevel@tonic-gate 	/*
110412f080e7Smrj 	 * Memory space
110512f080e7Smrj 	 */
110612f080e7Smrj 
110712f080e7Smrj 	if (hp != NULL) {
110812f080e7Smrj 		/*
110912f080e7Smrj 		 * hat layer ignores
111012f080e7Smrj 		 * hp->ah_acc.devacc_attr_endian_flags.
111112f080e7Smrj 		 */
111212f080e7Smrj 		switch (hp->ah_acc.devacc_attr_dataorder) {
111312f080e7Smrj 		case DDI_STRICTORDER_ACC:
111412f080e7Smrj 			hat_acc_flags = HAT_STRICTORDER;
111512f080e7Smrj 			break;
111612f080e7Smrj 		case DDI_UNORDERED_OK_ACC:
111712f080e7Smrj 			hat_acc_flags = HAT_UNORDERED_OK;
111812f080e7Smrj 			break;
111912f080e7Smrj 		case DDI_MERGING_OK_ACC:
112012f080e7Smrj 			hat_acc_flags = HAT_MERGING_OK;
112112f080e7Smrj 			break;
112212f080e7Smrj 		case DDI_LOADCACHING_OK_ACC:
112312f080e7Smrj 			hat_acc_flags = HAT_LOADCACHING_OK;
112412f080e7Smrj 			break;
112512f080e7Smrj 		case DDI_STORECACHING_OK_ACC:
112612f080e7Smrj 			hat_acc_flags = HAT_STORECACHING_OK;
112712f080e7Smrj 			break;
112812f080e7Smrj 		}
112912f080e7Smrj 		ap = (ddi_acc_impl_t *)hp->ah_platform_private;
113012f080e7Smrj 		ap->ahi_acc_attr |= DDI_ACCATTR_CPU_VADDR;
113112f080e7Smrj 		impl_acc_hdl_init(hp);
113212f080e7Smrj 		hp->ah_hat_flags = hat_acc_flags;
113312f080e7Smrj 	} else {
113412f080e7Smrj 		hat_acc_flags = HAT_STRICTORDER;
113512f080e7Smrj 	}
113612f080e7Smrj 
113712f080e7Smrj 	base = (ulong_t)rp->regspec_addr & (~MMU_PAGEOFFSET); /* base addr */
113812f080e7Smrj 	pgoffset = (ulong_t)rp->regspec_addr & MMU_PAGEOFFSET; /* offset */
113912f080e7Smrj 
114012f080e7Smrj 	if (rp->regspec_size == 0) {
114112f080e7Smrj #ifdef  DDI_MAP_DEBUG
114212f080e7Smrj 		ddi_map_debug("rootnex_map_regspec: zero regspec_size\n");
114312f080e7Smrj #endif  /* DDI_MAP_DEBUG */
114412f080e7Smrj 		return (DDI_ME_INVAL);
114512f080e7Smrj 	}
114612f080e7Smrj 
114712f080e7Smrj 	if (mp->map_flags & DDI_MF_DEVICE_MAPPING) {
114812f080e7Smrj 		*vaddrp = (caddr_t)mmu_btop(base);
114912f080e7Smrj 	} else {
115012f080e7Smrj 		npages = mmu_btopr(rp->regspec_size + pgoffset);
115112f080e7Smrj 
115212f080e7Smrj #ifdef	DDI_MAP_DEBUG
115312f080e7Smrj 		ddi_map_debug("rootnex_map_regspec: Mapping %d pages \
115412f080e7Smrj physical %x ",
115512f080e7Smrj 		    npages, base);
115612f080e7Smrj #endif	/* DDI_MAP_DEBUG */
115712f080e7Smrj 
115812f080e7Smrj 		cvaddr = device_arena_alloc(ptob(npages), VM_NOSLEEP);
115912f080e7Smrj 		if (cvaddr == NULL)
116012f080e7Smrj 			return (DDI_ME_NORESOURCES);
116112f080e7Smrj 
116212f080e7Smrj 		/*
116312f080e7Smrj 		 * Now map in the pages we've allocated...
116412f080e7Smrj 		 */
116512f080e7Smrj 		hat_devload(kas.a_hat, cvaddr, mmu_ptob(npages), mmu_btop(base),
116612f080e7Smrj 		    mp->map_prot | hat_acc_flags, HAT_LOAD_LOCK);
116712f080e7Smrj 		*vaddrp = (caddr_t)cvaddr + pgoffset;
116812f080e7Smrj 	}
116912f080e7Smrj 
117012f080e7Smrj #ifdef	DDI_MAP_DEBUG
117112f080e7Smrj 	ddi_map_debug("at virtual 0x%x\n", *vaddrp);
117212f080e7Smrj #endif	/* DDI_MAP_DEBUG */
117312f080e7Smrj 	return (DDI_SUCCESS);
117412f080e7Smrj }
117512f080e7Smrj 
117612f080e7Smrj 
117712f080e7Smrj /*
117812f080e7Smrj  * rootnex_unmap_regspec()
11797c478bd9Sstevel@tonic-gate  *
11807c478bd9Sstevel@tonic-gate  */
11817c478bd9Sstevel@tonic-gate static int
118212f080e7Smrj rootnex_unmap_regspec(ddi_map_req_t *mp, caddr_t *vaddrp)
11837c478bd9Sstevel@tonic-gate {
118412f080e7Smrj 	caddr_t addr = (caddr_t)*vaddrp;
118512f080e7Smrj 	uint_t npages, pgoffset;
118612f080e7Smrj 	struct regspec *rp;
11877c478bd9Sstevel@tonic-gate 
118812f080e7Smrj 	if (mp->map_flags & DDI_MF_DEVICE_MAPPING)
118912f080e7Smrj 		return (0);
11907c478bd9Sstevel@tonic-gate 
119112f080e7Smrj 	rp = mp->map_obj.rp;
11927c478bd9Sstevel@tonic-gate 
119312f080e7Smrj 	if (rp->regspec_size == 0) {
119412f080e7Smrj #ifdef  DDI_MAP_DEBUG
119512f080e7Smrj 		ddi_map_debug("rootnex_unmap_regspec: zero regspec_size\n");
119612f080e7Smrj #endif  /* DDI_MAP_DEBUG */
119712f080e7Smrj 		return (DDI_ME_INVAL);
11987c478bd9Sstevel@tonic-gate 	}
11997c478bd9Sstevel@tonic-gate 
12007c478bd9Sstevel@tonic-gate 	/*
120112f080e7Smrj 	 * I/O or memory mapping:
12027c478bd9Sstevel@tonic-gate 	 *
120312f080e7Smrj 	 *	<bustype=0, addr=x, len=x>: memory
120412f080e7Smrj 	 *	<bustype=1, addr=x, len=x>: i/o
120512f080e7Smrj 	 *	<bustype>1, addr=0, len=x>: x86-compatibility i/o
12067c478bd9Sstevel@tonic-gate 	 */
120712f080e7Smrj 	if (rp->regspec_bustype != 0) {
12087c478bd9Sstevel@tonic-gate 		/*
120912f080e7Smrj 		 * This is I/O space, which requires no particular
121012f080e7Smrj 		 * processing on unmap since it isn't mapped in the
121112f080e7Smrj 		 * first place.
12127c478bd9Sstevel@tonic-gate 		 */
12137c478bd9Sstevel@tonic-gate 		return (DDI_SUCCESS);
12147c478bd9Sstevel@tonic-gate 	}
12157c478bd9Sstevel@tonic-gate 
12167c478bd9Sstevel@tonic-gate 	/*
121712f080e7Smrj 	 * Memory space
12187c478bd9Sstevel@tonic-gate 	 */
121912f080e7Smrj 	pgoffset = (uintptr_t)addr & MMU_PAGEOFFSET;
122012f080e7Smrj 	npages = mmu_btopr(rp->regspec_size + pgoffset);
122112f080e7Smrj 	hat_unload(kas.a_hat, addr - pgoffset, ptob(npages), HAT_UNLOAD_UNLOCK);
122212f080e7Smrj 	device_arena_free(addr - pgoffset, ptob(npages));
12237c478bd9Sstevel@tonic-gate 
12247c478bd9Sstevel@tonic-gate 	/*
122512f080e7Smrj 	 * Destroy the pointer - the mapping has logically gone
12267c478bd9Sstevel@tonic-gate 	 */
122712f080e7Smrj 	*vaddrp = NULL;
12287c478bd9Sstevel@tonic-gate 
12297c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
12307c478bd9Sstevel@tonic-gate }
12317c478bd9Sstevel@tonic-gate 
123212f080e7Smrj 
123312f080e7Smrj /*
123412f080e7Smrj  * rootnex_map_handle()
123512f080e7Smrj  *
123612f080e7Smrj  */
12377c478bd9Sstevel@tonic-gate static int
123812f080e7Smrj rootnex_map_handle(ddi_map_req_t *mp)
12397c478bd9Sstevel@tonic-gate {
124012f080e7Smrj 	ddi_acc_hdl_t *hp;
124112f080e7Smrj 	ulong_t base;
124212f080e7Smrj 	uint_t pgoffset;
124312f080e7Smrj 	struct regspec *rp;
12447c478bd9Sstevel@tonic-gate 
124512f080e7Smrj 	rp = mp->map_obj.rp;
12467c478bd9Sstevel@tonic-gate 
124712f080e7Smrj #ifdef	DDI_MAP_DEBUG
124812f080e7Smrj 	ddi_map_debug(
124912f080e7Smrj 	    "rootnex_map_handle: <0x%x 0x%x 0x%x> handle 0x%x\n",
125012f080e7Smrj 	    rp->regspec_bustype, rp->regspec_addr,
125112f080e7Smrj 	    rp->regspec_size, mp->map_handlep);
125212f080e7Smrj #endif	/* DDI_MAP_DEBUG */
12537c478bd9Sstevel@tonic-gate 
12547c478bd9Sstevel@tonic-gate 	/*
125512f080e7Smrj 	 * I/O or memory mapping:
125612f080e7Smrj 	 *
125712f080e7Smrj 	 *	<bustype=0, addr=x, len=x>: memory
125812f080e7Smrj 	 *	<bustype=1, addr=x, len=x>: i/o
125912f080e7Smrj 	 *	<bustype>1, addr=0, len=x>: x86-compatibility i/o
12607c478bd9Sstevel@tonic-gate 	 */
126112f080e7Smrj 	if (rp->regspec_bustype != 0) {
126212f080e7Smrj 		/*
126312f080e7Smrj 		 * This refers to I/O space, and we don't support "mapping"
126412f080e7Smrj 		 * I/O space to a user.
126512f080e7Smrj 		 */
12667c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
12677c478bd9Sstevel@tonic-gate 	}
12687c478bd9Sstevel@tonic-gate 
12697c478bd9Sstevel@tonic-gate 	/*
127012f080e7Smrj 	 * Set up the hat_flags for the mapping.
12717c478bd9Sstevel@tonic-gate 	 */
127212f080e7Smrj 	hp = mp->map_handlep;
12737c478bd9Sstevel@tonic-gate 
127412f080e7Smrj 	switch (hp->ah_acc.devacc_attr_endian_flags) {
127512f080e7Smrj 	case DDI_NEVERSWAP_ACC:
127612f080e7Smrj 		hp->ah_hat_flags = HAT_NEVERSWAP | HAT_STRICTORDER;
12777c478bd9Sstevel@tonic-gate 		break;
127812f080e7Smrj 	case DDI_STRUCTURE_LE_ACC:
127912f080e7Smrj 		hp->ah_hat_flags = HAT_STRUCTURE_LE;
12807c478bd9Sstevel@tonic-gate 		break;
128112f080e7Smrj 	case DDI_STRUCTURE_BE_ACC:
12827c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
12837c478bd9Sstevel@tonic-gate 	default:
128412f080e7Smrj 		return (DDI_REGS_ACC_CONFLICT);
12857c478bd9Sstevel@tonic-gate 	}
12867c478bd9Sstevel@tonic-gate 
128712f080e7Smrj 	switch (hp->ah_acc.devacc_attr_dataorder) {
128812f080e7Smrj 	case DDI_STRICTORDER_ACC:
12897c478bd9Sstevel@tonic-gate 		break;
129012f080e7Smrj 	case DDI_UNORDERED_OK_ACC:
129112f080e7Smrj 		hp->ah_hat_flags |= HAT_UNORDERED_OK;
12927c478bd9Sstevel@tonic-gate 		break;
129312f080e7Smrj 	case DDI_MERGING_OK_ACC:
129412f080e7Smrj 		hp->ah_hat_flags |= HAT_MERGING_OK;
12957c478bd9Sstevel@tonic-gate 		break;
129612f080e7Smrj 	case DDI_LOADCACHING_OK_ACC:
129712f080e7Smrj 		hp->ah_hat_flags |= HAT_LOADCACHING_OK;
129812f080e7Smrj 		break;
129912f080e7Smrj 	case DDI_STORECACHING_OK_ACC:
130012f080e7Smrj 		hp->ah_hat_flags |= HAT_STORECACHING_OK;
130112f080e7Smrj 		break;
13027c478bd9Sstevel@tonic-gate 	default:
13037c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
13047c478bd9Sstevel@tonic-gate 	}
13057c478bd9Sstevel@tonic-gate 
130612f080e7Smrj 	base = (ulong_t)rp->regspec_addr & (~MMU_PAGEOFFSET); /* base addr */
130712f080e7Smrj 	pgoffset = (ulong_t)rp->regspec_addr & MMU_PAGEOFFSET; /* offset */
13087c478bd9Sstevel@tonic-gate 
130912f080e7Smrj 	if (rp->regspec_size == 0)
131012f080e7Smrj 		return (DDI_ME_INVAL);
13117c478bd9Sstevel@tonic-gate 
131212f080e7Smrj 	hp->ah_pfn = mmu_btop(base);
131312f080e7Smrj 	hp->ah_pnum = mmu_btopr(rp->regspec_size + pgoffset);
13147c478bd9Sstevel@tonic-gate 
13157c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
13167c478bd9Sstevel@tonic-gate }
13177c478bd9Sstevel@tonic-gate 
131812f080e7Smrj 
131912f080e7Smrj 
13207c478bd9Sstevel@tonic-gate /*
132112f080e7Smrj  * ************************
132212f080e7Smrj  *  interrupt related code
132312f080e7Smrj  * ************************
13247c478bd9Sstevel@tonic-gate  */
13257c478bd9Sstevel@tonic-gate 
13267c478bd9Sstevel@tonic-gate /*
132712f080e7Smrj  * rootnex_intr_ops()
13287c478bd9Sstevel@tonic-gate  *	bus_intr_op() function for interrupt support
13297c478bd9Sstevel@tonic-gate  */
13307c478bd9Sstevel@tonic-gate /* ARGSUSED */
13317c478bd9Sstevel@tonic-gate static int
13327c478bd9Sstevel@tonic-gate rootnex_intr_ops(dev_info_t *pdip, dev_info_t *rdip, ddi_intr_op_t intr_op,
13337c478bd9Sstevel@tonic-gate     ddi_intr_handle_impl_t *hdlp, void *result)
13347c478bd9Sstevel@tonic-gate {
13357c478bd9Sstevel@tonic-gate 	struct intrspec			*ispec;
13367c478bd9Sstevel@tonic-gate 	struct ddi_parent_private_data	*pdp;
13377c478bd9Sstevel@tonic-gate 
13387c478bd9Sstevel@tonic-gate 	DDI_INTR_NEXDBG((CE_CONT,
13397c478bd9Sstevel@tonic-gate 	    "rootnex_intr_ops: pdip = %p, rdip = %p, intr_op = %x, hdlp = %p\n",
13407c478bd9Sstevel@tonic-gate 	    (void *)pdip, (void *)rdip, intr_op, (void *)hdlp));
13417c478bd9Sstevel@tonic-gate 
13427c478bd9Sstevel@tonic-gate 	/* Process the interrupt operation */
13437c478bd9Sstevel@tonic-gate 	switch (intr_op) {
13447c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETCAP:
13457c478bd9Sstevel@tonic-gate 		/* First check with pcplusmp */
13467c478bd9Sstevel@tonic-gate 		if (psm_intr_ops == NULL)
13477c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
13487c478bd9Sstevel@tonic-gate 
13497c478bd9Sstevel@tonic-gate 		if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_GET_CAP, result)) {
13507c478bd9Sstevel@tonic-gate 			*(int *)result = 0;
13517c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
13527c478bd9Sstevel@tonic-gate 		}
13537c478bd9Sstevel@tonic-gate 		break;
13547c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETCAP:
13557c478bd9Sstevel@tonic-gate 		if (psm_intr_ops == NULL)
13567c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
13577c478bd9Sstevel@tonic-gate 
13587c478bd9Sstevel@tonic-gate 		if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_CAP, result))
13597c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
13607c478bd9Sstevel@tonic-gate 		break;
13617c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ALLOC:
13627c478bd9Sstevel@tonic-gate 		if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)
13637c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
13647c478bd9Sstevel@tonic-gate 		hdlp->ih_pri = ispec->intrspec_pri;
13657c478bd9Sstevel@tonic-gate 		*(int *)result = hdlp->ih_scratch1;
13667c478bd9Sstevel@tonic-gate 		break;
13677c478bd9Sstevel@tonic-gate 	case DDI_INTROP_FREE:
13687c478bd9Sstevel@tonic-gate 		pdp = ddi_get_parent_data(rdip);
13697c478bd9Sstevel@tonic-gate 		/*
13707c478bd9Sstevel@tonic-gate 		 * Special case for 'pcic' driver' only.
13717c478bd9Sstevel@tonic-gate 		 * If an intrspec was created for it, clean it up here
13727c478bd9Sstevel@tonic-gate 		 * See detailed comments on this in the function
13737c478bd9Sstevel@tonic-gate 		 * rootnex_get_ispec().
13747c478bd9Sstevel@tonic-gate 		 */
13757c478bd9Sstevel@tonic-gate 		if (pdp->par_intr && strcmp(ddi_get_name(rdip), "pcic") == 0) {
13767c478bd9Sstevel@tonic-gate 			kmem_free(pdp->par_intr, sizeof (struct intrspec) *
13777c478bd9Sstevel@tonic-gate 			    pdp->par_nintr);
13787c478bd9Sstevel@tonic-gate 			/*
13797c478bd9Sstevel@tonic-gate 			 * Set it to zero; so that
13807c478bd9Sstevel@tonic-gate 			 * DDI framework doesn't free it again
13817c478bd9Sstevel@tonic-gate 			 */
13827c478bd9Sstevel@tonic-gate 			pdp->par_intr = NULL;
13837c478bd9Sstevel@tonic-gate 			pdp->par_nintr = 0;
13847c478bd9Sstevel@tonic-gate 		}
13857c478bd9Sstevel@tonic-gate 		break;
13867c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETPRI:
13877c478bd9Sstevel@tonic-gate 		if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)
13887c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
13897c478bd9Sstevel@tonic-gate 		*(int *)result = ispec->intrspec_pri;
13907c478bd9Sstevel@tonic-gate 		break;
13917c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETPRI:
13927c478bd9Sstevel@tonic-gate 		/* Validate the interrupt priority passed to us */
13937c478bd9Sstevel@tonic-gate 		if (*(int *)result > LOCK_LEVEL)
13947c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
13957c478bd9Sstevel@tonic-gate 
13967c478bd9Sstevel@tonic-gate 		/* Ensure that PSM is all initialized and ispec is ok */
13977c478bd9Sstevel@tonic-gate 		if ((psm_intr_ops == NULL) ||
13987c478bd9Sstevel@tonic-gate 		    ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL))
13997c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14007c478bd9Sstevel@tonic-gate 
14017c478bd9Sstevel@tonic-gate 		/* Change the priority */
14027c478bd9Sstevel@tonic-gate 		if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_PRI, result) ==
14037c478bd9Sstevel@tonic-gate 		    PSM_FAILURE)
14047c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14057c478bd9Sstevel@tonic-gate 
14067c478bd9Sstevel@tonic-gate 		/* update the ispec with the new priority */
14077c478bd9Sstevel@tonic-gate 		ispec->intrspec_pri =  *(int *)result;
14087c478bd9Sstevel@tonic-gate 		break;
14097c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ADDISR:
14107c478bd9Sstevel@tonic-gate 		if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)
14117c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14127c478bd9Sstevel@tonic-gate 		ispec->intrspec_func = hdlp->ih_cb_func;
14137c478bd9Sstevel@tonic-gate 		break;
14147c478bd9Sstevel@tonic-gate 	case DDI_INTROP_REMISR:
14157c478bd9Sstevel@tonic-gate 		if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)
14167c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14177c478bd9Sstevel@tonic-gate 		ispec->intrspec_func = (uint_t (*)()) 0;
14187c478bd9Sstevel@tonic-gate 		break;
14197c478bd9Sstevel@tonic-gate 	case DDI_INTROP_ENABLE:
14207c478bd9Sstevel@tonic-gate 		if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)
14217c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14227c478bd9Sstevel@tonic-gate 
14237c478bd9Sstevel@tonic-gate 		/* Call psmi to translate irq with the dip */
14247c478bd9Sstevel@tonic-gate 		if (psm_intr_ops == NULL)
14257c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14267c478bd9Sstevel@tonic-gate 
14277a364d25Sschwartz 		((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec;
14287c478bd9Sstevel@tonic-gate 		(void) (*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_XLATE_VECTOR,
14297c478bd9Sstevel@tonic-gate 		    (int *)&hdlp->ih_vector);
14307c478bd9Sstevel@tonic-gate 
14317c478bd9Sstevel@tonic-gate 		/* Add the interrupt handler */
14327c478bd9Sstevel@tonic-gate 		if (!add_avintr((void *)hdlp, ispec->intrspec_pri,
14337c478bd9Sstevel@tonic-gate 		    hdlp->ih_cb_func, DEVI(rdip)->devi_name, hdlp->ih_vector,
14347a364d25Sschwartz 		    hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, NULL, rdip))
14357c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14367c478bd9Sstevel@tonic-gate 		break;
14377c478bd9Sstevel@tonic-gate 	case DDI_INTROP_DISABLE:
14387c478bd9Sstevel@tonic-gate 		if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)
14397c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14407c478bd9Sstevel@tonic-gate 
14417c478bd9Sstevel@tonic-gate 		/* Call psm_ops() to translate irq with the dip */
14427c478bd9Sstevel@tonic-gate 		if (psm_intr_ops == NULL)
14437c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14447c478bd9Sstevel@tonic-gate 
14457a364d25Sschwartz 		((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec;
14467c478bd9Sstevel@tonic-gate 		(void) (*psm_intr_ops)(rdip, hdlp,
14477c478bd9Sstevel@tonic-gate 		    PSM_INTR_OP_XLATE_VECTOR, (int *)&hdlp->ih_vector);
14487c478bd9Sstevel@tonic-gate 
14497c478bd9Sstevel@tonic-gate 		/* Remove the interrupt handler */
14507c478bd9Sstevel@tonic-gate 		rem_avintr((void *)hdlp, ispec->intrspec_pri,
14517c478bd9Sstevel@tonic-gate 		    hdlp->ih_cb_func, hdlp->ih_vector);
14527c478bd9Sstevel@tonic-gate 		break;
14537c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SETMASK:
14547c478bd9Sstevel@tonic-gate 		if (psm_intr_ops == NULL)
14557c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14567c478bd9Sstevel@tonic-gate 
14577c478bd9Sstevel@tonic-gate 		if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_MASK, NULL))
14587c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14597c478bd9Sstevel@tonic-gate 		break;
14607c478bd9Sstevel@tonic-gate 	case DDI_INTROP_CLRMASK:
14617c478bd9Sstevel@tonic-gate 		if (psm_intr_ops == NULL)
14627c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14637c478bd9Sstevel@tonic-gate 
14647c478bd9Sstevel@tonic-gate 		if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_CLEAR_MASK, NULL))
14657c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14667c478bd9Sstevel@tonic-gate 		break;
14677c478bd9Sstevel@tonic-gate 	case DDI_INTROP_GETPENDING:
14687c478bd9Sstevel@tonic-gate 		if (psm_intr_ops == NULL)
14697c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14707c478bd9Sstevel@tonic-gate 
14717c478bd9Sstevel@tonic-gate 		if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_GET_PENDING,
14727c478bd9Sstevel@tonic-gate 		    result)) {
14737c478bd9Sstevel@tonic-gate 			*(int *)result = 0;
14747c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14757c478bd9Sstevel@tonic-gate 		}
14767c478bd9Sstevel@tonic-gate 		break;
14777c478bd9Sstevel@tonic-gate 	case DDI_INTROP_NINTRS:
14787c478bd9Sstevel@tonic-gate 		if ((pdp = ddi_get_parent_data(rdip)) == NULL)
14797c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
14807c478bd9Sstevel@tonic-gate 		*(int *)result = pdp->par_nintr;
14817c478bd9Sstevel@tonic-gate 		if (pdp->par_nintr == 0) {
14827c478bd9Sstevel@tonic-gate 			/*
14837c478bd9Sstevel@tonic-gate 			 * Special case for 'pcic' driver' only. This driver
14847c478bd9Sstevel@tonic-gate 			 * driver is a child of 'isa' and 'rootnex' drivers.
14857c478bd9Sstevel@tonic-gate 			 *
14867c478bd9Sstevel@tonic-gate 			 * See detailed comments on this in the function
14877c478bd9Sstevel@tonic-gate 			 * rootnex_get_ispec().
14887c478bd9Sstevel@tonic-gate 			 *
14897c478bd9Sstevel@tonic-gate 			 * Children of 'pcic' send 'NINITR' request all the
14907c478bd9Sstevel@tonic-gate 			 * way to rootnex driver. But, the 'pdp->par_nintr'
14917c478bd9Sstevel@tonic-gate 			 * field may not initialized. So, we fake it here
14927c478bd9Sstevel@tonic-gate 			 * to return 1 (a la what PCMCIA nexus does).
14937c478bd9Sstevel@tonic-gate 			 */
14947c478bd9Sstevel@tonic-gate 			if (strcmp(ddi_get_name(rdip), "pcic") == 0)
14957c478bd9Sstevel@tonic-gate 				*(int *)result = 1;
14967c478bd9Sstevel@tonic-gate 		}
14977c478bd9Sstevel@tonic-gate 		break;
14987c478bd9Sstevel@tonic-gate 	case DDI_INTROP_SUPPORTED_TYPES:
14997c478bd9Sstevel@tonic-gate 		*(int *)result = 0;
15007c478bd9Sstevel@tonic-gate 		*(int *)result |= DDI_INTR_TYPE_FIXED;	/* Always ... */
15017c478bd9Sstevel@tonic-gate 		break;
15027c478bd9Sstevel@tonic-gate 	case DDI_INTROP_NAVAIL:
15037c478bd9Sstevel@tonic-gate 		if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)
15047c478bd9Sstevel@tonic-gate 			return (DDI_FAILURE);
15057c478bd9Sstevel@tonic-gate 
15067c478bd9Sstevel@tonic-gate 		if (psm_intr_ops == NULL) {
15077c478bd9Sstevel@tonic-gate 			*(int *)result = 1;
15087c478bd9Sstevel@tonic-gate 			break;
15097c478bd9Sstevel@tonic-gate 		}
15107c478bd9Sstevel@tonic-gate 
15117c478bd9Sstevel@tonic-gate 		/* Priority in the handle not initialized yet */
15127c478bd9Sstevel@tonic-gate 		hdlp->ih_pri = ispec->intrspec_pri;
15137c478bd9Sstevel@tonic-gate 		(void) (*psm_intr_ops)(rdip, hdlp,
15147c478bd9Sstevel@tonic-gate 		    PSM_INTR_OP_NAVAIL_VECTORS, result);
15157c478bd9Sstevel@tonic-gate 		break;
15167c478bd9Sstevel@tonic-gate 	default:
15177c478bd9Sstevel@tonic-gate 		return (DDI_FAILURE);
15187c478bd9Sstevel@tonic-gate 	}
15197c478bd9Sstevel@tonic-gate 
15207c478bd9Sstevel@tonic-gate 	return (DDI_SUCCESS);
15217c478bd9Sstevel@tonic-gate }
15227c478bd9Sstevel@tonic-gate 
15237c478bd9Sstevel@tonic-gate 
15247c478bd9Sstevel@tonic-gate /*
152512f080e7Smrj  * rootnex_get_ispec()
152612f080e7Smrj  *	convert an interrupt number to an interrupt specification.
152712f080e7Smrj  *	The interrupt number determines which interrupt spec will be
152812f080e7Smrj  *	returned if more than one exists.
152912f080e7Smrj  *
153012f080e7Smrj  *	Look into the parent private data area of the 'rdip' to find out
153112f080e7Smrj  *	the interrupt specification.  First check to make sure there is
153212f080e7Smrj  *	one that matchs "inumber" and then return a pointer to it.
153312f080e7Smrj  *
153412f080e7Smrj  *	Return NULL if one could not be found.
153512f080e7Smrj  *
153612f080e7Smrj  *	NOTE: This is needed for rootnex_intr_ops()
15377c478bd9Sstevel@tonic-gate  */
153812f080e7Smrj static struct intrspec *
153912f080e7Smrj rootnex_get_ispec(dev_info_t *rdip, int inum)
15407c478bd9Sstevel@tonic-gate {
154112f080e7Smrj 	struct ddi_parent_private_data *pdp = ddi_get_parent_data(rdip);
15427c478bd9Sstevel@tonic-gate 
15437c478bd9Sstevel@tonic-gate 	/*
154412f080e7Smrj 	 * Special case handling for drivers that provide their own
154512f080e7Smrj 	 * intrspec structures instead of relying on the DDI framework.
154612f080e7Smrj 	 *
154712f080e7Smrj 	 * A broken hardware driver in ON could potentially provide its
154812f080e7Smrj 	 * own intrspec structure, instead of relying on the hardware.
154912f080e7Smrj 	 * If these drivers are children of 'rootnex' then we need to
155012f080e7Smrj 	 * continue to provide backward compatibility to them here.
155112f080e7Smrj 	 *
155212f080e7Smrj 	 * Following check is a special case for 'pcic' driver which
155312f080e7Smrj 	 * was found to have broken hardwre andby provides its own intrspec.
155412f080e7Smrj 	 *
155512f080e7Smrj 	 * Verbatim comments from this driver are shown here:
155612f080e7Smrj 	 * "Don't use the ddi_add_intr since we don't have a
155712f080e7Smrj 	 * default intrspec in all cases."
155812f080e7Smrj 	 *
155912f080e7Smrj 	 * Since an 'ispec' may not be always created for it,
156012f080e7Smrj 	 * check for that and create one if so.
156112f080e7Smrj 	 *
156212f080e7Smrj 	 * NOTE: Currently 'pcic' is the only driver found to do this.
15637c478bd9Sstevel@tonic-gate 	 */
156412f080e7Smrj 	if (!pdp->par_intr && strcmp(ddi_get_name(rdip), "pcic") == 0) {
156512f080e7Smrj 		pdp->par_nintr = 1;
156612f080e7Smrj 		pdp->par_intr = kmem_zalloc(sizeof (struct intrspec) *
156712f080e7Smrj 		    pdp->par_nintr, KM_SLEEP);
156812f080e7Smrj 	}
156912f080e7Smrj 
157012f080e7Smrj 	/* Validate the interrupt number */
157112f080e7Smrj 	if (inum >= pdp->par_nintr)
157212f080e7Smrj 		return (NULL);
157312f080e7Smrj 
157412f080e7Smrj 	/* Get the interrupt structure pointer and return that */
157512f080e7Smrj 	return ((struct intrspec *)&pdp->par_intr[inum]);
157612f080e7Smrj }
157712f080e7Smrj 
157812f080e7Smrj 
157912f080e7Smrj /*
158012f080e7Smrj  * ******************
158112f080e7Smrj  *  dma related code
158212f080e7Smrj  * ******************
158312f080e7Smrj  */
158412f080e7Smrj 
158512f080e7Smrj /*
158612f080e7Smrj  * rootnex_dma_allochdl()
158712f080e7Smrj  *    called from ddi_dma_alloc_handle().
158812f080e7Smrj  */
158912f080e7Smrj /*ARGSUSED*/
159012f080e7Smrj static int
159112f080e7Smrj rootnex_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attr,
159212f080e7Smrj     int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep)
159312f080e7Smrj {
159412f080e7Smrj 	uint64_t maxsegmentsize_ll;
159512f080e7Smrj 	uint_t maxsegmentsize;
159612f080e7Smrj 	ddi_dma_impl_t *hp;
159712f080e7Smrj 	rootnex_dma_t *dma;
159812f080e7Smrj 	uint64_t count_max;
159912f080e7Smrj 	uint64_t seg;
160012f080e7Smrj 	int kmflag;
160112f080e7Smrj 	int e;
160212f080e7Smrj 
160312f080e7Smrj 
160412f080e7Smrj 	/* convert our sleep flags */
160512f080e7Smrj 	if (waitfp == DDI_DMA_SLEEP) {
160612f080e7Smrj 		kmflag = KM_SLEEP;
160712f080e7Smrj 	} else {
160812f080e7Smrj 		kmflag = KM_NOSLEEP;
160912f080e7Smrj 	}
161012f080e7Smrj 
161112f080e7Smrj 	/*
161212f080e7Smrj 	 * We try to do only one memory allocation here. We'll do a little
161312f080e7Smrj 	 * pointer manipulation later. If the bind ends up taking more than
161412f080e7Smrj 	 * our prealloc's space, we'll have to allocate more memory in the
161512f080e7Smrj 	 * bind operation. Not great, but much better than before and the
161612f080e7Smrj 	 * best we can do with the current bind interfaces.
161712f080e7Smrj 	 */
161812f080e7Smrj 	hp = kmem_cache_alloc(rootnex_state->r_dmahdl_cache, kmflag);
161912f080e7Smrj 	if (hp == NULL) {
162012f080e7Smrj 		if (waitfp != DDI_DMA_DONTWAIT) {
162112f080e7Smrj 			ddi_set_callback(waitfp, arg,
162212f080e7Smrj 			    &rootnex_state->r_dvma_call_list_id);
162312f080e7Smrj 		}
162412f080e7Smrj 		return (DDI_DMA_NORESOURCES);
162512f080e7Smrj 	}
162612f080e7Smrj 
162712f080e7Smrj 	/* Do our pointer manipulation now, align the structures */
162812f080e7Smrj 	hp->dmai_private = (void *)(((uintptr_t)hp +
162912f080e7Smrj 	    (uintptr_t)sizeof (ddi_dma_impl_t) + 0x7) & ~0x7);
163012f080e7Smrj 	dma = (rootnex_dma_t *)hp->dmai_private;
163112f080e7Smrj 	dma->dp_prealloc_buffer = (uchar_t *)(((uintptr_t)dma +
163212f080e7Smrj 	    sizeof (rootnex_dma_t) + 0x7) & ~0x7);
163312f080e7Smrj 
163412f080e7Smrj 	/* setup the handle */
163512f080e7Smrj 	rootnex_clean_dmahdl(hp);
163612f080e7Smrj 	dma->dp_dip = rdip;
163712f080e7Smrj 	dma->dp_sglinfo.si_min_addr = attr->dma_attr_addr_lo;
163812f080e7Smrj 	dma->dp_sglinfo.si_max_addr = attr->dma_attr_addr_hi;
163912f080e7Smrj 	hp->dmai_minxfer = attr->dma_attr_minxfer;
164012f080e7Smrj 	hp->dmai_burstsizes = attr->dma_attr_burstsizes;
164112f080e7Smrj 	hp->dmai_rdip = rdip;
164212f080e7Smrj 	hp->dmai_attr = *attr;
164312f080e7Smrj 
164412f080e7Smrj 	/* we don't need to worry about the SPL since we do a tryenter */
164512f080e7Smrj 	mutex_init(&dma->dp_mutex, NULL, MUTEX_DRIVER, NULL);
164612f080e7Smrj 
164712f080e7Smrj 	/*
164812f080e7Smrj 	 * Figure out our maximum segment size. If the segment size is greater
164912f080e7Smrj 	 * than 4G, we will limit it to (4G - 1) since the max size of a dma
165012f080e7Smrj 	 * object (ddi_dma_obj_t.dmao_size) is 32 bits. dma_attr_seg and
165112f080e7Smrj 	 * dma_attr_count_max are size-1 type values.
165212f080e7Smrj 	 *
165312f080e7Smrj 	 * Maximum segment size is the largest physically contiguous chunk of
165412f080e7Smrj 	 * memory that we can return from a bind (i.e. the maximum size of a
165512f080e7Smrj 	 * single cookie).
165612f080e7Smrj 	 */
165712f080e7Smrj 
165812f080e7Smrj 	/* handle the rollover cases */
165912f080e7Smrj 	seg = attr->dma_attr_seg + 1;
166012f080e7Smrj 	if (seg < attr->dma_attr_seg) {
166112f080e7Smrj 		seg = attr->dma_attr_seg;
166212f080e7Smrj 	}
166312f080e7Smrj 	count_max = attr->dma_attr_count_max + 1;
166412f080e7Smrj 	if (count_max < attr->dma_attr_count_max) {
166512f080e7Smrj 		count_max = attr->dma_attr_count_max;
166612f080e7Smrj 	}
166712f080e7Smrj 
166812f080e7Smrj 	/*
166912f080e7Smrj 	 * granularity may or may not be a power of two. If it isn't, we can't
167012f080e7Smrj 	 * use a simple mask.
167112f080e7Smrj 	 */
167212f080e7Smrj 	if (attr->dma_attr_granular & (attr->dma_attr_granular - 1)) {
167312f080e7Smrj 		dma->dp_granularity_power_2 = B_FALSE;
167412f080e7Smrj 	} else {
167512f080e7Smrj 		dma->dp_granularity_power_2 = B_TRUE;
167612f080e7Smrj 	}
167712f080e7Smrj 
167812f080e7Smrj 	/*
167912f080e7Smrj 	 * maxxfer should be a whole multiple of granularity. If we're going to
168012f080e7Smrj 	 * break up a window because we're greater than maxxfer, we might as
168112f080e7Smrj 	 * well make sure it's maxxfer is a whole multiple so we don't have to
168212f080e7Smrj 	 * worry about triming the window later on for this case.
168312f080e7Smrj 	 */
168412f080e7Smrj 	if (attr->dma_attr_granular > 1) {
168512f080e7Smrj 		if (dma->dp_granularity_power_2) {
168612f080e7Smrj 			dma->dp_maxxfer = attr->dma_attr_maxxfer -
168712f080e7Smrj 			    (attr->dma_attr_maxxfer &
168812f080e7Smrj 			    (attr->dma_attr_granular - 1));
168912f080e7Smrj 		} else {
169012f080e7Smrj 			dma->dp_maxxfer = attr->dma_attr_maxxfer -
169112f080e7Smrj 			    (attr->dma_attr_maxxfer % attr->dma_attr_granular);
169212f080e7Smrj 		}
169312f080e7Smrj 	} else {
169412f080e7Smrj 		dma->dp_maxxfer = attr->dma_attr_maxxfer;
169512f080e7Smrj 	}
169612f080e7Smrj 
169712f080e7Smrj 	maxsegmentsize_ll = MIN(seg, dma->dp_maxxfer);
169812f080e7Smrj 	maxsegmentsize_ll = MIN(maxsegmentsize_ll, count_max);
169912f080e7Smrj 	if (maxsegmentsize_ll == 0 || (maxsegmentsize_ll > 0xFFFFFFFF)) {
170012f080e7Smrj 		maxsegmentsize = 0xFFFFFFFF;
170112f080e7Smrj 	} else {
170212f080e7Smrj 		maxsegmentsize = maxsegmentsize_ll;
170312f080e7Smrj 	}
170412f080e7Smrj 	dma->dp_sglinfo.si_max_cookie_size = maxsegmentsize;
170512f080e7Smrj 	dma->dp_sglinfo.si_segmask = attr->dma_attr_seg;
170612f080e7Smrj 
170712f080e7Smrj 	/* check the ddi_dma_attr arg to make sure it makes a little sense */
170812f080e7Smrj 	if (rootnex_alloc_check_parms) {
170912f080e7Smrj 		e = rootnex_valid_alloc_parms(attr, maxsegmentsize);
171012f080e7Smrj 		if (e != DDI_SUCCESS) {
171112f080e7Smrj 			ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ALLOC_FAIL]);
171212f080e7Smrj 			(void) rootnex_dma_freehdl(dip, rdip,
171312f080e7Smrj 			    (ddi_dma_handle_t)hp);
171412f080e7Smrj 			return (e);
171512f080e7Smrj 		}
171612f080e7Smrj 	}
171712f080e7Smrj 
171812f080e7Smrj 	*handlep = (ddi_dma_handle_t)hp;
171912f080e7Smrj 
172012f080e7Smrj 	ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]);
172112f080e7Smrj 	DTRACE_PROBE1(rootnex__alloc__handle, uint64_t,
172212f080e7Smrj 	    rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]);
172312f080e7Smrj 
172412f080e7Smrj 	return (DDI_SUCCESS);
172512f080e7Smrj }
172612f080e7Smrj 
172712f080e7Smrj 
172812f080e7Smrj /*
172912f080e7Smrj  * rootnex_dma_freehdl()
173012f080e7Smrj  *    called from ddi_dma_free_handle().
173112f080e7Smrj  */
173212f080e7Smrj /*ARGSUSED*/
173312f080e7Smrj static int
173412f080e7Smrj rootnex_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle)
173512f080e7Smrj {
173612f080e7Smrj 	ddi_dma_impl_t *hp;
173712f080e7Smrj 	rootnex_dma_t *dma;
173812f080e7Smrj 
173912f080e7Smrj 
174012f080e7Smrj 	hp = (ddi_dma_impl_t *)handle;
174112f080e7Smrj 	dma = (rootnex_dma_t *)hp->dmai_private;
174212f080e7Smrj 
174312f080e7Smrj 	/* unbind should have been called first */
174412f080e7Smrj 	ASSERT(!dma->dp_inuse);
174512f080e7Smrj 
174612f080e7Smrj 	mutex_destroy(&dma->dp_mutex);
174712f080e7Smrj 	kmem_cache_free(rootnex_state->r_dmahdl_cache, hp);
174812f080e7Smrj 
174912f080e7Smrj 	ROOTNEX_PROF_DEC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]);
175012f080e7Smrj 	DTRACE_PROBE1(rootnex__free__handle, uint64_t,
175112f080e7Smrj 	    rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]);
175212f080e7Smrj 
175312f080e7Smrj 	if (rootnex_state->r_dvma_call_list_id)
175412f080e7Smrj 		ddi_run_callback(&rootnex_state->r_dvma_call_list_id);
175512f080e7Smrj 
175612f080e7Smrj 	return (DDI_SUCCESS);
175712f080e7Smrj }
175812f080e7Smrj 
175912f080e7Smrj 
176012f080e7Smrj /*
176112f080e7Smrj  * rootnex_dma_bindhdl()
176212f080e7Smrj  *    called from ddi_dma_addr_bind_handle() and ddi_dma_buf_bind_handle().
176312f080e7Smrj  */
176412f080e7Smrj /*ARGSUSED*/
176512f080e7Smrj static int
176612f080e7Smrj rootnex_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
176712f080e7Smrj     struct ddi_dma_req *dmareq, ddi_dma_cookie_t *cookiep, uint_t *ccountp)
176812f080e7Smrj {
176912f080e7Smrj 	rootnex_sglinfo_t *sinfo;
177012f080e7Smrj 	ddi_dma_attr_t *attr;
177112f080e7Smrj 	ddi_dma_impl_t *hp;
177212f080e7Smrj 	rootnex_dma_t *dma;
177312f080e7Smrj 	int kmflag;
177412f080e7Smrj 	int e;
177512f080e7Smrj 
177612f080e7Smrj 
177712f080e7Smrj 	hp = (ddi_dma_impl_t *)handle;
177812f080e7Smrj 	dma = (rootnex_dma_t *)hp->dmai_private;
177912f080e7Smrj 	sinfo = &dma->dp_sglinfo;
178012f080e7Smrj 	attr = &hp->dmai_attr;
178112f080e7Smrj 
178212f080e7Smrj 	hp->dmai_rflags = dmareq->dmar_flags & DMP_DDIFLAGS;
178312f080e7Smrj 
178412f080e7Smrj 	/*
178512f080e7Smrj 	 * This is useful for debugging a driver. Not as useful in a production
178612f080e7Smrj 	 * system. The only time this will fail is if you have a driver bug.
178712f080e7Smrj 	 */
178812f080e7Smrj 	if (rootnex_bind_check_inuse) {
178912f080e7Smrj 		/*
179012f080e7Smrj 		 * No one else should ever have this lock unless someone else
179112f080e7Smrj 		 * is trying to use this handle. So contention on the lock
179212f080e7Smrj 		 * is the same as inuse being set.
179312f080e7Smrj 		 */
179412f080e7Smrj 		e = mutex_tryenter(&dma->dp_mutex);
179512f080e7Smrj 		if (e == 0) {
179612f080e7Smrj 			ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]);
179712f080e7Smrj 			return (DDI_DMA_INUSE);
179812f080e7Smrj 		}
179912f080e7Smrj 		if (dma->dp_inuse) {
180012f080e7Smrj 			mutex_exit(&dma->dp_mutex);
180112f080e7Smrj 			ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]);
180212f080e7Smrj 			return (DDI_DMA_INUSE);
180312f080e7Smrj 		}
180412f080e7Smrj 		dma->dp_inuse = B_TRUE;
180512f080e7Smrj 		mutex_exit(&dma->dp_mutex);
180612f080e7Smrj 	}
180712f080e7Smrj 
180812f080e7Smrj 	/* check the ddi_dma_attr arg to make sure it makes a little sense */
180912f080e7Smrj 	if (rootnex_bind_check_parms) {
181012f080e7Smrj 		e = rootnex_valid_bind_parms(dmareq, attr);
181112f080e7Smrj 		if (e != DDI_SUCCESS) {
181212f080e7Smrj 			ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]);
181312f080e7Smrj 			rootnex_clean_dmahdl(hp);
181412f080e7Smrj 			return (e);
181512f080e7Smrj 		}
181612f080e7Smrj 	}
181712f080e7Smrj 
181812f080e7Smrj 	/* save away the original bind info */
181912f080e7Smrj 	dma->dp_dma = dmareq->dmar_object;
182012f080e7Smrj 
182112f080e7Smrj 	/*
182212f080e7Smrj 	 * Figure out a rough estimate of what maximum number of pages this
182312f080e7Smrj 	 * buffer could use (a high estimate of course).
182412f080e7Smrj 	 */
182512f080e7Smrj 	sinfo->si_max_pages = mmu_btopr(dma->dp_dma.dmao_size) + 1;
182612f080e7Smrj 
182712f080e7Smrj 	/*
182812f080e7Smrj 	 * We'll use the pre-allocated cookies for any bind that will *always*
182912f080e7Smrj 	 * fit (more important to be consistent, we don't want to create
183012f080e7Smrj 	 * additional degenerate cases).
183112f080e7Smrj 	 */
183212f080e7Smrj 	if (sinfo->si_max_pages <= rootnex_state->r_prealloc_cookies) {
183312f080e7Smrj 		dma->dp_cookies = (ddi_dma_cookie_t *)dma->dp_prealloc_buffer;
183412f080e7Smrj 		dma->dp_need_to_free_cookie = B_FALSE;
183512f080e7Smrj 		DTRACE_PROBE2(rootnex__bind__prealloc, dev_info_t *, rdip,
183612f080e7Smrj 		    uint_t, sinfo->si_max_pages);
183712f080e7Smrj 
183812f080e7Smrj 	/*
183912f080e7Smrj 	 * For anything larger than that, we'll go ahead and allocate the
184012f080e7Smrj 	 * maximum number of pages we expect to see. Hopefuly, we won't be
184112f080e7Smrj 	 * seeing this path in the fast path for high performance devices very
184212f080e7Smrj 	 * frequently.
184312f080e7Smrj 	 *
184412f080e7Smrj 	 * a ddi bind interface that allowed the driver to provide storage to
184512f080e7Smrj 	 * the bind interface would speed this case up.
184612f080e7Smrj 	 */
184712f080e7Smrj 	} else {
184812f080e7Smrj 		/* convert the sleep flags */
184912f080e7Smrj 		if (dmareq->dmar_fp == DDI_DMA_SLEEP) {
185012f080e7Smrj 			kmflag =  KM_SLEEP;
185112f080e7Smrj 		} else {
185212f080e7Smrj 			kmflag =  KM_NOSLEEP;
185312f080e7Smrj 		}
185412f080e7Smrj 
185512f080e7Smrj 		/*
185612f080e7Smrj 		 * Save away how much memory we allocated. If we're doing a
185712f080e7Smrj 		 * nosleep, the alloc could fail...
185812f080e7Smrj 		 */
185912f080e7Smrj 		dma->dp_cookie_size = sinfo->si_max_pages *
186012f080e7Smrj 		    sizeof (ddi_dma_cookie_t);
186112f080e7Smrj 		dma->dp_cookies = kmem_alloc(dma->dp_cookie_size, kmflag);
186212f080e7Smrj 		if (dma->dp_cookies == NULL) {
186312f080e7Smrj 			ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]);
186412f080e7Smrj 			rootnex_clean_dmahdl(hp);
186512f080e7Smrj 			return (DDI_DMA_NORESOURCES);
186612f080e7Smrj 		}
186712f080e7Smrj 		dma->dp_need_to_free_cookie = B_TRUE;
186812f080e7Smrj 		DTRACE_PROBE2(rootnex__bind__alloc, dev_info_t *, rdip, uint_t,
186912f080e7Smrj 		    sinfo->si_max_pages);
187012f080e7Smrj 	}
187112f080e7Smrj 	hp->dmai_cookie = dma->dp_cookies;
187212f080e7Smrj 
187312f080e7Smrj 	/*
187412f080e7Smrj 	 * Get the real sgl. rootnex_get_sgl will fill in cookie array while
187512f080e7Smrj 	 * looking at the contraints in the dma structure. It will then put some
187612f080e7Smrj 	 * additional state about the sgl in the dma struct (i.e. is the sgl
187712f080e7Smrj 	 * clean, or do we need to do some munging; how many pages need to be
187812f080e7Smrj 	 * copied, etc.)
187912f080e7Smrj 	 */
188012f080e7Smrj 	rootnex_get_sgl(&dmareq->dmar_object, dma->dp_cookies,
188112f080e7Smrj 	    &dma->dp_sglinfo);
188212f080e7Smrj 	ASSERT(sinfo->si_sgl_size <= sinfo->si_max_pages);
188312f080e7Smrj 
188412f080e7Smrj 	/* if we don't need a copy buffer, we don't need to sync */
188512f080e7Smrj 	if (sinfo->si_copybuf_req == 0) {
188612f080e7Smrj 		hp->dmai_rflags |= DMP_NOSYNC;
188712f080e7Smrj 	}
188812f080e7Smrj 
188912f080e7Smrj 	/*
189012f080e7Smrj 	 * if we don't need the copybuf and we don't need to do a partial,  we
189112f080e7Smrj 	 * hit the fast path. All the high performance devices should be trying
189212f080e7Smrj 	 * to hit this path. To hit this path, a device should be able to reach
189312f080e7Smrj 	 * all of memory, shouldn't try to bind more than it can transfer, and
189412f080e7Smrj 	 * the buffer shouldn't require more cookies than the driver/device can
189512f080e7Smrj 	 * handle [sgllen]).
189612f080e7Smrj 	 */
189712f080e7Smrj 	if ((sinfo->si_copybuf_req == 0) &&
189812f080e7Smrj 	    (sinfo->si_sgl_size <= attr->dma_attr_sgllen) &&
189912f080e7Smrj 	    (dma->dp_dma.dmao_size < dma->dp_maxxfer)) {
190012f080e7Smrj 		/*
190112f080e7Smrj 		 * copy out the first cookie and ccountp, set the cookie
190212f080e7Smrj 		 * pointer to the second cookie. The first cookie is passed
190312f080e7Smrj 		 * back on the stack. Additional cookies are accessed via
190412f080e7Smrj 		 * ddi_dma_nextcookie()
190512f080e7Smrj 		 */
190612f080e7Smrj 		*cookiep = dma->dp_cookies[0];
190712f080e7Smrj 		*ccountp = sinfo->si_sgl_size;
190812f080e7Smrj 		hp->dmai_cookie++;
190912f080e7Smrj 		hp->dmai_rflags &= ~DDI_DMA_PARTIAL;
191012f080e7Smrj 		hp->dmai_nwin = 1;
191112f080e7Smrj 		ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]);
191212f080e7Smrj 		DTRACE_PROBE3(rootnex__bind__fast, dev_info_t *, rdip, uint64_t,
191312f080e7Smrj 		    rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS], uint_t,
191412f080e7Smrj 		    dma->dp_dma.dmao_size);
191512f080e7Smrj 		return (DDI_DMA_MAPPED);
191612f080e7Smrj 	}
191712f080e7Smrj 
191812f080e7Smrj 	/*
191912f080e7Smrj 	 * go to the slow path, we may need to alloc more memory, create
192012f080e7Smrj 	 * multiple windows, and munge up a sgl to make the device happy.
192112f080e7Smrj 	 */
192212f080e7Smrj 	e = rootnex_bind_slowpath(hp, dmareq, dma, attr, kmflag);
192312f080e7Smrj 	if ((e != DDI_DMA_MAPPED) && (e != DDI_DMA_PARTIAL_MAP)) {
192412f080e7Smrj 		if (dma->dp_need_to_free_cookie) {
192512f080e7Smrj 			kmem_free(dma->dp_cookies, dma->dp_cookie_size);
192612f080e7Smrj 		}
192712f080e7Smrj 		ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]);
192812f080e7Smrj 		rootnex_clean_dmahdl(hp); /* must be after free cookie */
192912f080e7Smrj 		return (e);
193012f080e7Smrj 	}
193112f080e7Smrj 
193212f080e7Smrj 	/* if the first window uses the copy buffer, sync it for the device */
193312f080e7Smrj 	if ((dma->dp_window[dma->dp_current_win].wd_dosync) &&
193412f080e7Smrj 	    (hp->dmai_rflags & DDI_DMA_WRITE)) {
193512f080e7Smrj 		(void) rootnex_dma_sync(dip, rdip, handle, 0, 0,
193612f080e7Smrj 		    DDI_DMA_SYNC_FORDEV);
193712f080e7Smrj 	}
193812f080e7Smrj 
193912f080e7Smrj 	/*
194012f080e7Smrj 	 * copy out the first cookie and ccountp, set the cookie pointer to the
194112f080e7Smrj 	 * second cookie. Make sure the partial flag is set/cleared correctly.
194212f080e7Smrj 	 * If we have a partial map (i.e. multiple windows), the number of
194312f080e7Smrj 	 * cookies we return is the number of cookies in the first window.
194412f080e7Smrj 	 */
194512f080e7Smrj 	if (e == DDI_DMA_MAPPED) {
194612f080e7Smrj 		hp->dmai_rflags &= ~DDI_DMA_PARTIAL;
194712f080e7Smrj 		*ccountp = sinfo->si_sgl_size;
194812f080e7Smrj 	} else {
194912f080e7Smrj 		hp->dmai_rflags |= DDI_DMA_PARTIAL;
195012f080e7Smrj 		*ccountp = dma->dp_window[dma->dp_current_win].wd_cookie_cnt;
195112f080e7Smrj 		ASSERT(hp->dmai_nwin <= dma->dp_max_win);
195212f080e7Smrj 	}
195312f080e7Smrj 	*cookiep = dma->dp_cookies[0];
195412f080e7Smrj 	hp->dmai_cookie++;
195512f080e7Smrj 
195612f080e7Smrj 	ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]);
195712f080e7Smrj 	DTRACE_PROBE3(rootnex__bind__slow, dev_info_t *, rdip, uint64_t,
195812f080e7Smrj 	    rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS], uint_t,
195912f080e7Smrj 	    dma->dp_dma.dmao_size);
196012f080e7Smrj 	return (e);
196112f080e7Smrj }
196212f080e7Smrj 
196312f080e7Smrj 
196412f080e7Smrj /*
196512f080e7Smrj  * rootnex_dma_unbindhdl()
196612f080e7Smrj  *    called from ddi_dma_unbind_handle()
196712f080e7Smrj  */
196812f080e7Smrj /*ARGSUSED*/
196912f080e7Smrj static int
197012f080e7Smrj rootnex_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip,
197112f080e7Smrj     ddi_dma_handle_t handle)
197212f080e7Smrj {
197312f080e7Smrj 	ddi_dma_impl_t *hp;
197412f080e7Smrj 	rootnex_dma_t *dma;
197512f080e7Smrj 	int e;
197612f080e7Smrj 
197712f080e7Smrj 
197812f080e7Smrj 	hp = (ddi_dma_impl_t *)handle;
197912f080e7Smrj 	dma = (rootnex_dma_t *)hp->dmai_private;
198012f080e7Smrj 
198112f080e7Smrj 	/* make sure the buffer wasn't free'd before calling unbind */
198212f080e7Smrj 	if (rootnex_unbind_verify_buffer) {
198312f080e7Smrj 		e = rootnex_verify_buffer(dma);
198412f080e7Smrj 		if (e != DDI_SUCCESS) {
198512f080e7Smrj 			ASSERT(0);
198612f080e7Smrj 			return (DDI_FAILURE);
198712f080e7Smrj 		}
198812f080e7Smrj 	}
198912f080e7Smrj 
199012f080e7Smrj 	/* sync the current window before unbinding the buffer */
199112f080e7Smrj 	if (dma->dp_window && dma->dp_window[dma->dp_current_win].wd_dosync &&
199212f080e7Smrj 	    (hp->dmai_rflags & DDI_DMA_READ)) {
199312f080e7Smrj 		(void) rootnex_dma_sync(dip, rdip, handle, 0, 0,
199412f080e7Smrj 		    DDI_DMA_SYNC_FORCPU);
199512f080e7Smrj 	}
199612f080e7Smrj 
199712f080e7Smrj 	/*
199812f080e7Smrj 	 * cleanup and copy buffer or window state. if we didn't use the copy
199912f080e7Smrj 	 * buffer or windows, there won't be much to do :-)
200012f080e7Smrj 	 */
200112f080e7Smrj 	rootnex_teardown_copybuf(dma);
200212f080e7Smrj 	rootnex_teardown_windows(dma);
200312f080e7Smrj 
200412f080e7Smrj 	/*
200512f080e7Smrj 	 * If we had to allocate space to for the worse case sgl (it didn't
200612f080e7Smrj 	 * fit into our pre-allocate buffer), free that up now
200712f080e7Smrj 	 */
200812f080e7Smrj 	if (dma->dp_need_to_free_cookie) {
200912f080e7Smrj 		kmem_free(dma->dp_cookies, dma->dp_cookie_size);
201012f080e7Smrj 	}
201112f080e7Smrj 
201212f080e7Smrj 	/*
201312f080e7Smrj 	 * clean up the handle so it's ready for the next bind (i.e. if the
201412f080e7Smrj 	 * handle is reused).
201512f080e7Smrj 	 */
201612f080e7Smrj 	rootnex_clean_dmahdl(hp);
201712f080e7Smrj 
201812f080e7Smrj 	if (rootnex_state->r_dvma_call_list_id)
201912f080e7Smrj 		ddi_run_callback(&rootnex_state->r_dvma_call_list_id);
202012f080e7Smrj 
202112f080e7Smrj 	ROOTNEX_PROF_DEC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]);
202212f080e7Smrj 	DTRACE_PROBE1(rootnex__unbind, uint64_t,
202312f080e7Smrj 	    rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]);
202412f080e7Smrj 
202512f080e7Smrj 	return (DDI_SUCCESS);
202612f080e7Smrj }
202712f080e7Smrj 
202812f080e7Smrj 
202912f080e7Smrj /*
203012f080e7Smrj  * rootnex_verify_buffer()
203112f080e7Smrj  *   verify buffer wasn't free'd
203212f080e7Smrj  */
203312f080e7Smrj static int
203412f080e7Smrj rootnex_verify_buffer(rootnex_dma_t *dma)
203512f080e7Smrj {
203612f080e7Smrj 	peekpoke_ctlops_t peek;
203712f080e7Smrj 	page_t **pplist;
203812f080e7Smrj 	caddr_t vaddr;
203912f080e7Smrj 	uint_t pcnt;
204012f080e7Smrj 	uint_t poff;
204112f080e7Smrj 	page_t *pp;
204212f080e7Smrj 	uint8_t b;
204312f080e7Smrj 	int i;
204412f080e7Smrj 	int e;
204512f080e7Smrj 
204612f080e7Smrj 
204712f080e7Smrj 	/* Figure out how many pages this buffer occupies */
204812f080e7Smrj 	if (dma->dp_dma.dmao_type == DMA_OTYP_PAGES) {
204912f080e7Smrj 		poff = dma->dp_dma.dmao_obj.pp_obj.pp_offset & MMU_PAGEOFFSET;
205012f080e7Smrj 	} else {
205112f080e7Smrj 		vaddr = dma->dp_dma.dmao_obj.virt_obj.v_addr;
205212f080e7Smrj 		poff = (uintptr_t)vaddr & MMU_PAGEOFFSET;
205312f080e7Smrj 	}
205412f080e7Smrj 	pcnt = mmu_btopr(dma->dp_dma.dmao_size + poff);
205512f080e7Smrj 
205612f080e7Smrj 	switch (dma->dp_dma.dmao_type) {
205712f080e7Smrj 	case DMA_OTYP_PAGES:
205812f080e7Smrj 		/*
205912f080e7Smrj 		 * for a linked list of pp's walk through them to make sure
206012f080e7Smrj 		 * they're locked and not free.
206112f080e7Smrj 		 */
206212f080e7Smrj 		pp = dma->dp_dma.dmao_obj.pp_obj.pp_pp;
206312f080e7Smrj 		for (i = 0; i < pcnt; i++) {
206412f080e7Smrj 			if (PP_ISFREE(pp) || !PAGE_LOCKED(pp)) {
206512f080e7Smrj 				return (DDI_FAILURE);
206612f080e7Smrj 			}
20677c478bd9Sstevel@tonic-gate 			pp = pp->p_next;
20687c478bd9Sstevel@tonic-gate 		}
20697c478bd9Sstevel@tonic-gate 		break;
207012f080e7Smrj 
20717c478bd9Sstevel@tonic-gate 	case DMA_OTYP_VADDR:
20727c478bd9Sstevel@tonic-gate 	case DMA_OTYP_BUFVADDR:
207312f080e7Smrj 		pplist = dma->dp_dma.dmao_obj.virt_obj.v_priv;
207412f080e7Smrj 		/*
207512f080e7Smrj 		 * for an array of pp's walk through them to make sure they're
207612f080e7Smrj 		 * not free. It's possible that they may not be locked.
207712f080e7Smrj 		 */
207812f080e7Smrj 		if (pplist) {
207912f080e7Smrj 			for (i = 0; i < pcnt; i++) {
208012f080e7Smrj 				if (PP_ISFREE(pplist[i])) {
208112f080e7Smrj 					return (DDI_FAILURE);
208212f080e7Smrj 				}
208312f080e7Smrj 			}
208412f080e7Smrj 
208512f080e7Smrj 		/* For a virtual address, try to peek at each page */
208612f080e7Smrj 		} else {
208712f080e7Smrj 			if (dma->dp_sglinfo.si_asp == &kas) {
208812f080e7Smrj 				bzero(&peek, sizeof (peekpoke_ctlops_t));
208912f080e7Smrj 				peek.host_addr = (uintptr_t)&b;
209012f080e7Smrj 				peek.size = sizeof (uint8_t);
209112f080e7Smrj 				peek.dev_addr = (uintptr_t)vaddr;
209212f080e7Smrj 				for (i = 0; i < pcnt; i++) {
209312f080e7Smrj 					e = rootnex_ctlops_peek(&peek, &b);
209412f080e7Smrj 					if (e != DDI_SUCCESS) {
209512f080e7Smrj 						return (DDI_FAILURE);
209612f080e7Smrj 					}
209712f080e7Smrj 					peek.dev_addr += MMU_PAGESIZE;
209812f080e7Smrj 				}
209912f080e7Smrj 			}
210012f080e7Smrj 		}
210112f080e7Smrj 		break;
210212f080e7Smrj 
210312f080e7Smrj 	default:
210412f080e7Smrj 		ASSERT(0);
210512f080e7Smrj 		break;
210612f080e7Smrj 	}
210712f080e7Smrj 
210812f080e7Smrj 	return (DDI_SUCCESS);
210912f080e7Smrj }
211012f080e7Smrj 
211112f080e7Smrj 
211212f080e7Smrj /*
211312f080e7Smrj  * rootnex_clean_dmahdl()
211412f080e7Smrj  *    Clean the dma handle. This should be called on a handle alloc and an
211512f080e7Smrj  *    unbind handle. Set the handle state to the default settings.
211612f080e7Smrj  */
211712f080e7Smrj static void
211812f080e7Smrj rootnex_clean_dmahdl(ddi_dma_impl_t *hp)
211912f080e7Smrj {
212012f080e7Smrj 	rootnex_dma_t *dma;
212112f080e7Smrj 
212212f080e7Smrj 
212312f080e7Smrj 	dma = (rootnex_dma_t *)hp->dmai_private;
212412f080e7Smrj 
212512f080e7Smrj 	hp->dmai_nwin = 0;
212612f080e7Smrj 	dma->dp_current_cookie = 0;
212712f080e7Smrj 	dma->dp_copybuf_size = 0;
212812f080e7Smrj 	dma->dp_window = NULL;
212912f080e7Smrj 	dma->dp_cbaddr = NULL;
213012f080e7Smrj 	dma->dp_inuse = B_FALSE;
213112f080e7Smrj 	dma->dp_need_to_free_cookie = B_FALSE;
213212f080e7Smrj 	dma->dp_need_to_free_window = B_FALSE;
213312f080e7Smrj 	dma->dp_partial_required = B_FALSE;
213412f080e7Smrj 	dma->dp_trim_required = B_FALSE;
213512f080e7Smrj 	dma->dp_sglinfo.si_copybuf_req = 0;
213612f080e7Smrj #if !defined(__amd64)
213712f080e7Smrj 	dma->dp_cb_remaping = B_FALSE;
213812f080e7Smrj 	dma->dp_kva = NULL;
213912f080e7Smrj #endif
214012f080e7Smrj 
214112f080e7Smrj 	/* FMA related initialization */
214212f080e7Smrj 	hp->dmai_fault = 0;
214312f080e7Smrj 	hp->dmai_fault_check = NULL;
214412f080e7Smrj 	hp->dmai_fault_notify = NULL;
214512f080e7Smrj 	hp->dmai_error.err_ena = 0;
214612f080e7Smrj 	hp->dmai_error.err_status = DDI_FM_OK;
214712f080e7Smrj 	hp->dmai_error.err_expected = DDI_FM_ERR_UNEXPECTED;
214812f080e7Smrj 	hp->dmai_error.err_ontrap = NULL;
214912f080e7Smrj 	hp->dmai_error.err_fep = NULL;
215012f080e7Smrj }
215112f080e7Smrj 
215212f080e7Smrj 
215312f080e7Smrj /*
215412f080e7Smrj  * rootnex_valid_alloc_parms()
215512f080e7Smrj  *    Called in ddi_dma_alloc_handle path to validate its parameters.
215612f080e7Smrj  */
215712f080e7Smrj static int
215812f080e7Smrj rootnex_valid_alloc_parms(ddi_dma_attr_t *attr, uint_t maxsegmentsize)
215912f080e7Smrj {
216012f080e7Smrj 	if ((attr->dma_attr_seg < MMU_PAGEOFFSET) ||
216112f080e7Smrj 	    (attr->dma_attr_count_max < MMU_PAGEOFFSET) ||
216212f080e7Smrj 	    (attr->dma_attr_granular > MMU_PAGESIZE) ||
216312f080e7Smrj 	    (attr->dma_attr_maxxfer < MMU_PAGESIZE)) {
216412f080e7Smrj 		return (DDI_DMA_BADATTR);
216512f080e7Smrj 	}
216612f080e7Smrj 
216712f080e7Smrj 	if (attr->dma_attr_addr_hi <= attr->dma_attr_addr_lo) {
216812f080e7Smrj 		return (DDI_DMA_BADATTR);
216912f080e7Smrj 	}
217012f080e7Smrj 
217112f080e7Smrj 	if ((attr->dma_attr_seg & MMU_PAGEOFFSET) != MMU_PAGEOFFSET ||
217212f080e7Smrj 	    MMU_PAGESIZE & (attr->dma_attr_granular - 1) ||
217312f080e7Smrj 	    attr->dma_attr_sgllen <= 0) {
217412f080e7Smrj 		return (DDI_DMA_BADATTR);
217512f080e7Smrj 	}
217612f080e7Smrj 
217712f080e7Smrj 	/* We should be able to DMA into every byte offset in a page */
217812f080e7Smrj 	if (maxsegmentsize < MMU_PAGESIZE) {
217912f080e7Smrj 		return (DDI_DMA_BADATTR);
218012f080e7Smrj 	}
218112f080e7Smrj 
218212f080e7Smrj 	return (DDI_SUCCESS);
218312f080e7Smrj }
218412f080e7Smrj 
218512f080e7Smrj 
218612f080e7Smrj /*
218712f080e7Smrj  * rootnex_valid_bind_parms()
218812f080e7Smrj  *    Called in ddi_dma_*_bind_handle path to validate its parameters.
218912f080e7Smrj  */
219012f080e7Smrj /* ARGSUSED */
219112f080e7Smrj static int
219212f080e7Smrj rootnex_valid_bind_parms(ddi_dma_req_t *dmareq, ddi_dma_attr_t *attr)
219312f080e7Smrj {
219412f080e7Smrj #if !defined(__amd64)
219512f080e7Smrj 	/*
219612f080e7Smrj 	 * we only support up to a 2G-1 transfer size on 32-bit kernels so
219712f080e7Smrj 	 * we can track the offset for the obsoleted interfaces.
219812f080e7Smrj 	 */
219912f080e7Smrj 	if (dmareq->dmar_object.dmao_size > 0x7FFFFFFF) {
220012f080e7Smrj 		return (DDI_DMA_TOOBIG);
220112f080e7Smrj 	}
220212f080e7Smrj #endif
220312f080e7Smrj 
220412f080e7Smrj 	return (DDI_SUCCESS);
220512f080e7Smrj }
220612f080e7Smrj 
220712f080e7Smrj 
220812f080e7Smrj /*
220912f080e7Smrj  * rootnex_get_sgl()
221012f080e7Smrj  *    Called in bind fastpath to get the sgl. Most of this will be replaced
221112f080e7Smrj  *    with a call to the vm layer when vm2.0 comes around...
221212f080e7Smrj  */
221312f080e7Smrj static void
221412f080e7Smrj rootnex_get_sgl(ddi_dma_obj_t *dmar_object, ddi_dma_cookie_t *sgl,
221512f080e7Smrj     rootnex_sglinfo_t *sglinfo)
221612f080e7Smrj {
221712f080e7Smrj 	ddi_dma_atyp_t buftype;
221812f080e7Smrj 	uint64_t last_page;
221912f080e7Smrj 	uint64_t offset;
222012f080e7Smrj 	uint64_t addrhi;
222112f080e7Smrj 	uint64_t addrlo;
222212f080e7Smrj 	uint64_t maxseg;
222312f080e7Smrj 	page_t **pplist;
222412f080e7Smrj 	uint64_t paddr;
222512f080e7Smrj 	uint32_t psize;
222612f080e7Smrj 	uint32_t size;
222712f080e7Smrj 	caddr_t vaddr;
222812f080e7Smrj 	uint_t pcnt;
222912f080e7Smrj 	page_t *pp;
223012f080e7Smrj 	uint_t cnt;
223112f080e7Smrj 
223212f080e7Smrj 
223312f080e7Smrj 	/* shortcuts */
223412f080e7Smrj 	pplist = dmar_object->dmao_obj.virt_obj.v_priv;
223512f080e7Smrj 	vaddr = dmar_object->dmao_obj.virt_obj.v_addr;
223612f080e7Smrj 	maxseg = sglinfo->si_max_cookie_size;
223712f080e7Smrj 	buftype = dmar_object->dmao_type;
223812f080e7Smrj 	addrhi = sglinfo->si_max_addr;
223912f080e7Smrj 	addrlo = sglinfo->si_min_addr;
224012f080e7Smrj 	size = dmar_object->dmao_size;
224112f080e7Smrj 
224212f080e7Smrj 	pcnt = 0;
224312f080e7Smrj 	cnt = 0;
224412f080e7Smrj 
224512f080e7Smrj 	/*
224612f080e7Smrj 	 * if we were passed down a linked list of pages, i.e. pointer to
224712f080e7Smrj 	 * page_t, use this to get our physical address and buf offset.
224812f080e7Smrj 	 */
224912f080e7Smrj 	if (buftype == DMA_OTYP_PAGES) {
225012f080e7Smrj 		pp = dmar_object->dmao_obj.pp_obj.pp_pp;
225112f080e7Smrj 		ASSERT(!PP_ISFREE(pp) && PAGE_LOCKED(pp));
225212f080e7Smrj 		offset =  dmar_object->dmao_obj.pp_obj.pp_offset &
225312f080e7Smrj 		    MMU_PAGEOFFSET;
225412f080e7Smrj 		paddr = ptob64(pp->p_pagenum) + offset;
225512f080e7Smrj 		psize = MIN(size, (MMU_PAGESIZE - offset));
225612f080e7Smrj 		pp = pp->p_next;
225712f080e7Smrj 		sglinfo->si_asp = NULL;
225812f080e7Smrj 
225912f080e7Smrj 	/*
226012f080e7Smrj 	 * We weren't passed down a linked list of pages, but if we were passed
226112f080e7Smrj 	 * down an array of pages, use this to get our physical address and buf
226212f080e7Smrj 	 * offset.
226312f080e7Smrj 	 */
226412f080e7Smrj 	} else if (pplist != NULL) {
226512f080e7Smrj 		ASSERT((buftype == DMA_OTYP_VADDR) ||
226612f080e7Smrj 		    (buftype == DMA_OTYP_BUFVADDR));
226712f080e7Smrj 
226812f080e7Smrj 		offset = (uintptr_t)vaddr & MMU_PAGEOFFSET;
226912f080e7Smrj 		sglinfo->si_asp = dmar_object->dmao_obj.virt_obj.v_as;
227012f080e7Smrj 		if (sglinfo->si_asp == NULL) {
227112f080e7Smrj 			sglinfo->si_asp = &kas;
227212f080e7Smrj 		}
227312f080e7Smrj 
227412f080e7Smrj 		ASSERT(!PP_ISFREE(pplist[pcnt]));
227512f080e7Smrj 		paddr = ptob64(pplist[pcnt]->p_pagenum);
227612f080e7Smrj 		paddr += offset;
227712f080e7Smrj 		psize = MIN(size, (MMU_PAGESIZE - offset));
227812f080e7Smrj 		pcnt++;
227912f080e7Smrj 
228012f080e7Smrj 	/*
228112f080e7Smrj 	 * All we have is a virtual address, we'll need to call into the VM
228212f080e7Smrj 	 * to get the physical address.
228312f080e7Smrj 	 */
228412f080e7Smrj 	} else {
228512f080e7Smrj 		ASSERT((buftype == DMA_OTYP_VADDR) ||
228612f080e7Smrj 		    (buftype == DMA_OTYP_BUFVADDR));
228712f080e7Smrj 
228812f080e7Smrj 		offset = (uintptr_t)vaddr & MMU_PAGEOFFSET;
228912f080e7Smrj 		sglinfo->si_asp = dmar_object->dmao_obj.virt_obj.v_as;
229012f080e7Smrj 		if (sglinfo->si_asp == NULL) {
229112f080e7Smrj 			sglinfo->si_asp = &kas;
229212f080e7Smrj 		}
229312f080e7Smrj 
229412f080e7Smrj 		paddr = ptob64(hat_getpfnum(sglinfo->si_asp->a_hat, vaddr));
229512f080e7Smrj 		paddr += offset;
229612f080e7Smrj 		psize = MIN(size, (MMU_PAGESIZE - offset));
229712f080e7Smrj 		vaddr += psize;
229812f080e7Smrj 	}
229912f080e7Smrj 
230012f080e7Smrj 	/*
230112f080e7Smrj 	 * Setup the first cookie with the physical address of the page and the
230212f080e7Smrj 	 * size of the page (which takes into account the initial offset into
230312f080e7Smrj 	 * the page.
230412f080e7Smrj 	 */
230512f080e7Smrj 	sgl[cnt].dmac_laddress = paddr;
230612f080e7Smrj 	sgl[cnt].dmac_size = psize;
230712f080e7Smrj 	sgl[cnt].dmac_type = 0;
230812f080e7Smrj 
230912f080e7Smrj 	/*
231012f080e7Smrj 	 * Save away the buffer offset into the page. We'll need this later in
231112f080e7Smrj 	 * the copy buffer code to help figure out the page index within the
231212f080e7Smrj 	 * buffer and the offset into the current page.
231312f080e7Smrj 	 */
231412f080e7Smrj 	sglinfo->si_buf_offset = offset;
231512f080e7Smrj 
231612f080e7Smrj 	/*
231712f080e7Smrj 	 * If the DMA engine can't reach the physical address, increase how
231812f080e7Smrj 	 * much copy buffer we need. We always increase by pagesize so we don't
231912f080e7Smrj 	 * have to worry about converting offsets. Set a flag in the cookies
232012f080e7Smrj 	 * dmac_type to indicate that it uses the copy buffer. If this isn't the
232112f080e7Smrj 	 * last cookie, go to the next cookie (since we separate each page which
232212f080e7Smrj 	 * uses the copy buffer in case the copy buffer is not physically
232312f080e7Smrj 	 * contiguous.
232412f080e7Smrj 	 */
232512f080e7Smrj 	if ((paddr < addrlo) || ((paddr + psize) > addrhi)) {
232612f080e7Smrj 		sglinfo->si_copybuf_req += MMU_PAGESIZE;
232712f080e7Smrj 		sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF;
232812f080e7Smrj 		if ((cnt + 1) < sglinfo->si_max_pages) {
232912f080e7Smrj 			cnt++;
233012f080e7Smrj 			sgl[cnt].dmac_laddress = 0;
233112f080e7Smrj 			sgl[cnt].dmac_size = 0;
233212f080e7Smrj 			sgl[cnt].dmac_type = 0;
233312f080e7Smrj 		}
233412f080e7Smrj 	}
233512f080e7Smrj 
233612f080e7Smrj 	/*
233712f080e7Smrj 	 * save this page's physical address so we can figure out if the next
233812f080e7Smrj 	 * page is physically contiguous. Keep decrementing size until we are
233912f080e7Smrj 	 * done with the buffer.
234012f080e7Smrj 	 */
234112f080e7Smrj 	last_page = paddr & MMU_PAGEMASK;
234212f080e7Smrj 	size -= psize;
234312f080e7Smrj 
234412f080e7Smrj 	while (size > 0) {
234512f080e7Smrj 		/* Get the size for this page (i.e. partial or full page) */
234612f080e7Smrj 		psize = MIN(size, MMU_PAGESIZE);
234712f080e7Smrj 
234812f080e7Smrj 		if (buftype == DMA_OTYP_PAGES) {
234912f080e7Smrj 			/* get the paddr from the page_t */
235012f080e7Smrj 			ASSERT(!PP_ISFREE(pp) && PAGE_LOCKED(pp));
235112f080e7Smrj 			paddr = ptob64(pp->p_pagenum);
235212f080e7Smrj 			pp = pp->p_next;
235312f080e7Smrj 		} else if (pplist != NULL) {
235412f080e7Smrj 			/* index into the array of page_t's to get the paddr */
235512f080e7Smrj 			ASSERT(!PP_ISFREE(pplist[pcnt]));
235612f080e7Smrj 			paddr = ptob64(pplist[pcnt]->p_pagenum);
235712f080e7Smrj 			pcnt++;
235812f080e7Smrj 		} else {
235912f080e7Smrj 			/* call into the VM to get the paddr */
236012f080e7Smrj 			paddr =  ptob64(hat_getpfnum(sglinfo->si_asp->a_hat,
236112f080e7Smrj 			    vaddr));
236212f080e7Smrj 			vaddr += psize;
236312f080e7Smrj 		}
236412f080e7Smrj 
236512f080e7Smrj 		/* check to see if this page needs the copy buffer */
236612f080e7Smrj 		if ((paddr < addrlo) || ((paddr + psize) > addrhi)) {
236712f080e7Smrj 			sglinfo->si_copybuf_req += MMU_PAGESIZE;
236812f080e7Smrj 
236912f080e7Smrj 			/*
237012f080e7Smrj 			 * if there is something in the current cookie, go to
237112f080e7Smrj 			 * the next one. We only want one page in a cookie which
237212f080e7Smrj 			 * uses the copybuf since the copybuf doesn't have to
237312f080e7Smrj 			 * be physically contiguous.
237412f080e7Smrj 			 */
237512f080e7Smrj 			if (sgl[cnt].dmac_size != 0) {
237612f080e7Smrj 				cnt++;
237712f080e7Smrj 			}
237812f080e7Smrj 			sgl[cnt].dmac_laddress = paddr;
237912f080e7Smrj 			sgl[cnt].dmac_size = psize;
238012f080e7Smrj #if defined(__amd64)
238112f080e7Smrj 			sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF;
238212f080e7Smrj #else
238312f080e7Smrj 			/*
238412f080e7Smrj 			 * save the buf offset for 32-bit kernel. used in the
238512f080e7Smrj 			 * obsoleted interfaces.
238612f080e7Smrj 			 */
238712f080e7Smrj 			sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF |
238812f080e7Smrj 			    (dmar_object->dmao_size - size);
238912f080e7Smrj #endif
239012f080e7Smrj 			/* if this isn't the last cookie, go to the next one */
239112f080e7Smrj 			if ((cnt + 1) < sglinfo->si_max_pages) {
239212f080e7Smrj 				cnt++;
239312f080e7Smrj 				sgl[cnt].dmac_laddress = 0;
239412f080e7Smrj 				sgl[cnt].dmac_size = 0;
239512f080e7Smrj 				sgl[cnt].dmac_type = 0;
239612f080e7Smrj 			}
239712f080e7Smrj 
239812f080e7Smrj 		/*
239912f080e7Smrj 		 * this page didn't need the copy buffer, if it's not physically
240012f080e7Smrj 		 * contiguous, or it would put us over a segment boundary, or it
240112f080e7Smrj 		 * puts us over the max cookie size, or the current sgl doesn't
240212f080e7Smrj 		 * have anything in it.
240312f080e7Smrj 		 */
240412f080e7Smrj 		} else if (((last_page + MMU_PAGESIZE) != paddr) ||
240512f080e7Smrj 		    !(paddr & sglinfo->si_segmask) ||
240612f080e7Smrj 		    ((sgl[cnt].dmac_size + psize) > maxseg) ||
240712f080e7Smrj 		    (sgl[cnt].dmac_size == 0)) {
240812f080e7Smrj 			/*
240912f080e7Smrj 			 * if we're not already in a new cookie, go to the next
241012f080e7Smrj 			 * cookie.
241112f080e7Smrj 			 */
241212f080e7Smrj 			if (sgl[cnt].dmac_size != 0) {
241312f080e7Smrj 				cnt++;
241412f080e7Smrj 			}
241512f080e7Smrj 
241612f080e7Smrj 			/* save the cookie information */
241712f080e7Smrj 			sgl[cnt].dmac_laddress = paddr;
241812f080e7Smrj 			sgl[cnt].dmac_size = psize;
241912f080e7Smrj #if defined(__amd64)
242012f080e7Smrj 			sgl[cnt].dmac_type = 0;
242112f080e7Smrj #else
242212f080e7Smrj 			/*
242312f080e7Smrj 			 * save the buf offset for 32-bit kernel. used in the
242412f080e7Smrj 			 * obsoleted interfaces.
242512f080e7Smrj 			 */
242612f080e7Smrj 			sgl[cnt].dmac_type = dmar_object->dmao_size - size;
242712f080e7Smrj #endif
242812f080e7Smrj 
242912f080e7Smrj 		/*
243012f080e7Smrj 		 * this page didn't need the copy buffer, it is physically
243112f080e7Smrj 		 * contiguous with the last page, and it's <= the max cookie
243212f080e7Smrj 		 * size.
243312f080e7Smrj 		 */
243412f080e7Smrj 		} else {
243512f080e7Smrj 			sgl[cnt].dmac_size += psize;
243612f080e7Smrj 
243712f080e7Smrj 			/*
243812f080e7Smrj 			 * if this exactly ==  the maximum cookie size, and
243912f080e7Smrj 			 * it isn't the last cookie, go to the next cookie.
244012f080e7Smrj 			 */
244112f080e7Smrj 			if (((sgl[cnt].dmac_size + psize) == maxseg) &&
244212f080e7Smrj 			    ((cnt + 1) < sglinfo->si_max_pages)) {
244312f080e7Smrj 				cnt++;
244412f080e7Smrj 				sgl[cnt].dmac_laddress = 0;
244512f080e7Smrj 				sgl[cnt].dmac_size = 0;
244612f080e7Smrj 				sgl[cnt].dmac_type = 0;
244712f080e7Smrj 			}
244812f080e7Smrj 		}
244912f080e7Smrj 
245012f080e7Smrj 		/*
245112f080e7Smrj 		 * save this page's physical address so we can figure out if the
245212f080e7Smrj 		 * next page is physically contiguous. Keep decrementing size
245312f080e7Smrj 		 * until we are done with the buffer.
245412f080e7Smrj 		 */
245512f080e7Smrj 		last_page = paddr;
245612f080e7Smrj 		size -= psize;
245712f080e7Smrj 	}
245812f080e7Smrj 
245912f080e7Smrj 	/* we're done, save away how many cookies the sgl has */
246012f080e7Smrj 	if (sgl[cnt].dmac_size == 0) {
246112f080e7Smrj 		ASSERT(cnt < sglinfo->si_max_pages);
246212f080e7Smrj 		sglinfo->si_sgl_size = cnt;
246312f080e7Smrj 	} else {
246412f080e7Smrj 		sglinfo->si_sgl_size = cnt + 1;
246512f080e7Smrj 	}
246612f080e7Smrj }
246712f080e7Smrj 
246812f080e7Smrj 
246912f080e7Smrj /*
247012f080e7Smrj  * rootnex_bind_slowpath()
247112f080e7Smrj  *    Call in the bind path if the calling driver can't use the sgl without
247212f080e7Smrj  *    modifying it. We either need to use the copy buffer and/or we will end up
247312f080e7Smrj  *    with a partial bind.
247412f080e7Smrj  */
247512f080e7Smrj static int
247612f080e7Smrj rootnex_bind_slowpath(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq,
247712f080e7Smrj     rootnex_dma_t *dma, ddi_dma_attr_t *attr, int kmflag)
247812f080e7Smrj {
247912f080e7Smrj 	rootnex_sglinfo_t *sinfo;
248012f080e7Smrj 	rootnex_window_t *window;
248112f080e7Smrj 	ddi_dma_cookie_t *cookie;
248212f080e7Smrj 	size_t copybuf_used;
248312f080e7Smrj 	size_t dmac_size;
248412f080e7Smrj 	boolean_t partial;
248512f080e7Smrj 	off_t cur_offset;
248612f080e7Smrj 	page_t *cur_pp;
248712f080e7Smrj 	major_t mnum;
248812f080e7Smrj 	int e;
248912f080e7Smrj 	int i;
249012f080e7Smrj 
249112f080e7Smrj 
249212f080e7Smrj 	sinfo = &dma->dp_sglinfo;
249312f080e7Smrj 	copybuf_used = 0;
249412f080e7Smrj 	partial = B_FALSE;
249512f080e7Smrj 
249612f080e7Smrj 	/*
249712f080e7Smrj 	 * If we're using the copybuf, set the copybuf state in dma struct.
249812f080e7Smrj 	 * Needs to be first since it sets the copy buffer size.
249912f080e7Smrj 	 */
250012f080e7Smrj 	if (sinfo->si_copybuf_req != 0) {
250112f080e7Smrj 		e = rootnex_setup_copybuf(hp, dmareq, dma, attr);
250212f080e7Smrj 		if (e != DDI_SUCCESS) {
250312f080e7Smrj 			return (e);
250412f080e7Smrj 		}
250512f080e7Smrj 	} else {
250612f080e7Smrj 		dma->dp_copybuf_size = 0;
250712f080e7Smrj 	}
250812f080e7Smrj 
250912f080e7Smrj 	/*
251012f080e7Smrj 	 * Figure out if we need to do a partial mapping. If so, figure out
251112f080e7Smrj 	 * if we need to trim the buffers when we munge the sgl.
251212f080e7Smrj 	 */
251312f080e7Smrj 	if ((dma->dp_copybuf_size < sinfo->si_copybuf_req) ||
251412f080e7Smrj 	    (dma->dp_dma.dmao_size > dma->dp_maxxfer) ||
251512f080e7Smrj 	    (attr->dma_attr_sgllen < sinfo->si_sgl_size)) {
251612f080e7Smrj 		dma->dp_partial_required = B_TRUE;
251712f080e7Smrj 		if (attr->dma_attr_granular != 1) {
251812f080e7Smrj 			dma->dp_trim_required = B_TRUE;
251912f080e7Smrj 		}
252012f080e7Smrj 	} else {
252112f080e7Smrj 		dma->dp_partial_required = B_FALSE;
252212f080e7Smrj 		dma->dp_trim_required = B_FALSE;
252312f080e7Smrj 	}
252412f080e7Smrj 
252512f080e7Smrj 	/* If we need to do a partial bind, make sure the driver supports it */
252612f080e7Smrj 	if (dma->dp_partial_required &&
252712f080e7Smrj 	    !(dmareq->dmar_flags & DDI_DMA_PARTIAL)) {
252812f080e7Smrj 
252912f080e7Smrj 		mnum = ddi_driver_major(dma->dp_dip);
253012f080e7Smrj 		/*
253112f080e7Smrj 		 * patchable which allows us to print one warning per major
253212f080e7Smrj 		 * number.
253312f080e7Smrj 		 */
253412f080e7Smrj 		if ((rootnex_bind_warn) &&
253512f080e7Smrj 		    ((rootnex_warn_list[mnum] & ROOTNEX_BIND_WARNING) == 0)) {
253612f080e7Smrj 			rootnex_warn_list[mnum] |= ROOTNEX_BIND_WARNING;
253712f080e7Smrj 			cmn_err(CE_WARN, "!%s: coding error detected, the "
253812f080e7Smrj 			    "driver is using ddi_dma_attr(9S) incorrectly. "
253912f080e7Smrj 			    "There is a small risk of data corruption in "
254012f080e7Smrj 			    "particular with large I/Os. The driver should be "
254112f080e7Smrj 			    "replaced with a corrected version for proper "
254212f080e7Smrj 			    "system operation. To disable this warning, add "
254312f080e7Smrj 			    "'set rootnex:rootnex_bind_warn=0' to "
254412f080e7Smrj 			    "/etc/system(4).", ddi_driver_name(dma->dp_dip));
254512f080e7Smrj 		}
254612f080e7Smrj 		return (DDI_DMA_TOOBIG);
254712f080e7Smrj 	}
254812f080e7Smrj 
254912f080e7Smrj 	/*
255012f080e7Smrj 	 * we might need multiple windows, setup state to handle them. In this
255112f080e7Smrj 	 * code path, we will have at least one window.
255212f080e7Smrj 	 */
255312f080e7Smrj 	e = rootnex_setup_windows(hp, dma, attr, kmflag);
255412f080e7Smrj 	if (e != DDI_SUCCESS) {
255512f080e7Smrj 		rootnex_teardown_copybuf(dma);
255612f080e7Smrj 		return (e);
255712f080e7Smrj 	}
255812f080e7Smrj 
255912f080e7Smrj 	window = &dma->dp_window[0];
256012f080e7Smrj 	cookie = &dma->dp_cookies[0];
256112f080e7Smrj 	cur_offset = 0;
256212f080e7Smrj 	rootnex_init_win(hp, dma, window, cookie, cur_offset);
256312f080e7Smrj 	if (dmareq->dmar_object.dmao_type == DMA_OTYP_PAGES) {
256412f080e7Smrj 		cur_pp = dmareq->dmar_object.dmao_obj.pp_obj.pp_pp;
256512f080e7Smrj 	}
256612f080e7Smrj 
256712f080e7Smrj 	/* loop though all the cookies we got back from get_sgl() */
256812f080e7Smrj 	for (i = 0; i < sinfo->si_sgl_size; i++) {
256912f080e7Smrj 		/*
257012f080e7Smrj 		 * If we're using the copy buffer, check this cookie and setup
257112f080e7Smrj 		 * its associated copy buffer state. If this cookie uses the
257212f080e7Smrj 		 * copy buffer, make sure we sync this window during dma_sync.
257312f080e7Smrj 		 */
257412f080e7Smrj 		if (dma->dp_copybuf_size > 0) {
257512f080e7Smrj 			rootnex_setup_cookie(&dmareq->dmar_object, dma, cookie,
257612f080e7Smrj 			    cur_offset, &copybuf_used, &cur_pp);
257712f080e7Smrj 			if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) {
257812f080e7Smrj 				window->wd_dosync = B_TRUE;
257912f080e7Smrj 			}
258012f080e7Smrj 		}
258112f080e7Smrj 
258212f080e7Smrj 		/*
258312f080e7Smrj 		 * save away the cookie size, since it could be modified in
258412f080e7Smrj 		 * the windowing code.
258512f080e7Smrj 		 */
258612f080e7Smrj 		dmac_size = cookie->dmac_size;
258712f080e7Smrj 
258812f080e7Smrj 		/* if we went over max copybuf size */
258912f080e7Smrj 		if (dma->dp_copybuf_size &&
259012f080e7Smrj 		    (copybuf_used > dma->dp_copybuf_size)) {
259112f080e7Smrj 			partial = B_TRUE;
259212f080e7Smrj 			e = rootnex_copybuf_window_boundary(hp, dma, &window,
259312f080e7Smrj 			    cookie, cur_offset, &copybuf_used);
259412f080e7Smrj 			if (e != DDI_SUCCESS) {
259512f080e7Smrj 				rootnex_teardown_copybuf(dma);
259612f080e7Smrj 				rootnex_teardown_windows(dma);
259712f080e7Smrj 				return (e);
259812f080e7Smrj 			}
259912f080e7Smrj 
260012f080e7Smrj 			/*
260112f080e7Smrj 			 * if the coookie uses the copy buffer, make sure the
260212f080e7Smrj 			 * new window we just moved to is set to sync.
260312f080e7Smrj 			 */
260412f080e7Smrj 			if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) {
260512f080e7Smrj 				window->wd_dosync = B_TRUE;
260612f080e7Smrj 			}
260712f080e7Smrj 			DTRACE_PROBE1(rootnex__copybuf__window, dev_info_t *,
260812f080e7Smrj 			    dma->dp_dip);
260912f080e7Smrj 
261012f080e7Smrj 		/* if the cookie cnt == max sgllen, move to the next window */
261112f080e7Smrj 		} else if (window->wd_cookie_cnt >= attr->dma_attr_sgllen) {
261212f080e7Smrj 			partial = B_TRUE;
261312f080e7Smrj 			ASSERT(window->wd_cookie_cnt == attr->dma_attr_sgllen);
261412f080e7Smrj 			e = rootnex_sgllen_window_boundary(hp, dma, &window,
261512f080e7Smrj 			    cookie, attr, cur_offset);
261612f080e7Smrj 			if (e != DDI_SUCCESS) {
261712f080e7Smrj 				rootnex_teardown_copybuf(dma);
261812f080e7Smrj 				rootnex_teardown_windows(dma);
261912f080e7Smrj 				return (e);
262012f080e7Smrj 			}
262112f080e7Smrj 
262212f080e7Smrj 			/*
262312f080e7Smrj 			 * if the coookie uses the copy buffer, make sure the
262412f080e7Smrj 			 * new window we just moved to is set to sync.
262512f080e7Smrj 			 */
262612f080e7Smrj 			if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) {
262712f080e7Smrj 				window->wd_dosync = B_TRUE;
262812f080e7Smrj 			}
262912f080e7Smrj 			DTRACE_PROBE1(rootnex__sgllen__window, dev_info_t *,
263012f080e7Smrj 			    dma->dp_dip);
263112f080e7Smrj 
263212f080e7Smrj 		/* else if we will be over maxxfer */
263312f080e7Smrj 		} else if ((window->wd_size + dmac_size) >
263412f080e7Smrj 		    dma->dp_maxxfer) {
263512f080e7Smrj 			partial = B_TRUE;
263612f080e7Smrj 			e = rootnex_maxxfer_window_boundary(hp, dma, &window,
263712f080e7Smrj 			    cookie);
263812f080e7Smrj 			if (e != DDI_SUCCESS) {
263912f080e7Smrj 				rootnex_teardown_copybuf(dma);
264012f080e7Smrj 				rootnex_teardown_windows(dma);
264112f080e7Smrj 				return (e);
264212f080e7Smrj 			}
264312f080e7Smrj 
264412f080e7Smrj 			/*
264512f080e7Smrj 			 * if the coookie uses the copy buffer, make sure the
264612f080e7Smrj 			 * new window we just moved to is set to sync.
264712f080e7Smrj 			 */
264812f080e7Smrj 			if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) {
264912f080e7Smrj 				window->wd_dosync = B_TRUE;
265012f080e7Smrj 			}
265112f080e7Smrj 			DTRACE_PROBE1(rootnex__maxxfer__window, dev_info_t *,
265212f080e7Smrj 			    dma->dp_dip);
265312f080e7Smrj 
265412f080e7Smrj 		/* else this cookie fits in the current window */
265512f080e7Smrj 		} else {
265612f080e7Smrj 			window->wd_cookie_cnt++;
265712f080e7Smrj 			window->wd_size += dmac_size;
265812f080e7Smrj 		}
265912f080e7Smrj 
266012f080e7Smrj 		/* track our offset into the buffer, go to the next cookie */
266112f080e7Smrj 		ASSERT(dmac_size <= dma->dp_dma.dmao_size);
266212f080e7Smrj 		ASSERT(cookie->dmac_size <= dmac_size);
266312f080e7Smrj 		cur_offset += dmac_size;
266412f080e7Smrj 		cookie++;
266512f080e7Smrj 	}
266612f080e7Smrj 
266712f080e7Smrj 	/* if we ended up with a zero sized window in the end, clean it up */
266812f080e7Smrj 	if (window->wd_size == 0) {
266912f080e7Smrj 		hp->dmai_nwin--;
267012f080e7Smrj 		window--;
267112f080e7Smrj 	}
267212f080e7Smrj 
267312f080e7Smrj 	ASSERT(window->wd_trim.tr_trim_last == B_FALSE);
267412f080e7Smrj 
267512f080e7Smrj 	if (!partial) {
267612f080e7Smrj 		return (DDI_DMA_MAPPED);
267712f080e7Smrj 	}
267812f080e7Smrj 
267912f080e7Smrj 	ASSERT(dma->dp_partial_required);
268012f080e7Smrj 	return (DDI_DMA_PARTIAL_MAP);
268112f080e7Smrj }
268212f080e7Smrj 
268312f080e7Smrj 
268412f080e7Smrj /*
268512f080e7Smrj  * rootnex_setup_copybuf()
268612f080e7Smrj  *    Called in bind slowpath. Figures out if we're going to use the copy
268712f080e7Smrj  *    buffer, and if we do, sets up the basic state to handle it.
268812f080e7Smrj  */
268912f080e7Smrj static int
269012f080e7Smrj rootnex_setup_copybuf(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq,
269112f080e7Smrj     rootnex_dma_t *dma, ddi_dma_attr_t *attr)
269212f080e7Smrj {
269312f080e7Smrj 	rootnex_sglinfo_t *sinfo;
269412f080e7Smrj 	ddi_dma_attr_t lattr;
269512f080e7Smrj 	size_t max_copybuf;
269612f080e7Smrj 	int cansleep;
269712f080e7Smrj 	int e;
269812f080e7Smrj #if !defined(__amd64)
269912f080e7Smrj 	int vmflag;
270012f080e7Smrj #endif
270112f080e7Smrj 
270212f080e7Smrj 
270312f080e7Smrj 	sinfo = &dma->dp_sglinfo;
270412f080e7Smrj 
270512f080e7Smrj 	/*
270612f080e7Smrj 	 * read this first so it's consistent through the routine so we can
270712f080e7Smrj 	 * patch it on the fly.
270812f080e7Smrj 	 */
270912f080e7Smrj 	max_copybuf = rootnex_max_copybuf_size & MMU_PAGEMASK;
271012f080e7Smrj 
271112f080e7Smrj 	/* We need to call into the rootnex on ddi_dma_sync() */
271212f080e7Smrj 	hp->dmai_rflags &= ~DMP_NOSYNC;
271312f080e7Smrj 
271412f080e7Smrj 	/* make sure the copybuf size <= the max size */
271512f080e7Smrj 	dma->dp_copybuf_size = MIN(sinfo->si_copybuf_req, max_copybuf);
271612f080e7Smrj 	ASSERT((dma->dp_copybuf_size & MMU_PAGEOFFSET) == 0);
271712f080e7Smrj 
271812f080e7Smrj #if !defined(__amd64)
271912f080e7Smrj 	/*
272012f080e7Smrj 	 * if we don't have kva space to copy to/from, allocate the KVA space
272112f080e7Smrj 	 * now. We only do this for the 32-bit kernel. We use seg kpm space for
272212f080e7Smrj 	 * the 64-bit kernel.
272312f080e7Smrj 	 */
272412f080e7Smrj 	if ((dmareq->dmar_object.dmao_type == DMA_OTYP_PAGES) ||
272512f080e7Smrj 	    (dmareq->dmar_object.dmao_obj.virt_obj.v_as != NULL)) {
272612f080e7Smrj 
272712f080e7Smrj 		/* convert the sleep flags */
272812f080e7Smrj 		if (dmareq->dmar_fp == DDI_DMA_SLEEP) {
272912f080e7Smrj 			vmflag = VM_SLEEP;
273012f080e7Smrj 		} else {
273112f080e7Smrj 			vmflag = VM_NOSLEEP;
273212f080e7Smrj 		}
273312f080e7Smrj 
273412f080e7Smrj 		/* allocate Kernel VA space that we can bcopy to/from */
273512f080e7Smrj 		dma->dp_kva = vmem_alloc(heap_arena, dma->dp_copybuf_size,
273612f080e7Smrj 		    vmflag);
273712f080e7Smrj 		if (dma->dp_kva == NULL) {
273812f080e7Smrj 			return (DDI_DMA_NORESOURCES);
273912f080e7Smrj 		}
274012f080e7Smrj 	}
274112f080e7Smrj #endif
274212f080e7Smrj 
274312f080e7Smrj 	/* convert the sleep flags */
274412f080e7Smrj 	if (dmareq->dmar_fp == DDI_DMA_SLEEP) {
274512f080e7Smrj 		cansleep = 1;
274612f080e7Smrj 	} else {
274712f080e7Smrj 		cansleep = 0;
274812f080e7Smrj 	}
274912f080e7Smrj 
275012f080e7Smrj 	/*
275112f080e7Smrj 	 * Allocated the actual copy buffer. This needs to fit within the DMA
275212f080e7Smrj 	 * engines limits, so we can't use kmem_alloc...
275312f080e7Smrj 	 */
275412f080e7Smrj 	lattr = *attr;
275512f080e7Smrj 	lattr.dma_attr_align = MMU_PAGESIZE;
275612f080e7Smrj 	e = i_ddi_mem_alloc(dma->dp_dip, &lattr, dma->dp_copybuf_size, cansleep,
275712f080e7Smrj 	    0, NULL, &dma->dp_cbaddr, &dma->dp_cbsize, NULL);
275812f080e7Smrj 	if (e != DDI_SUCCESS) {
275912f080e7Smrj #if !defined(__amd64)
276012f080e7Smrj 		if (dma->dp_kva != NULL) {
276112f080e7Smrj 			vmem_free(heap_arena, dma->dp_kva,
276212f080e7Smrj 			    dma->dp_copybuf_size);
276312f080e7Smrj 		}
276412f080e7Smrj #endif
276512f080e7Smrj 		return (DDI_DMA_NORESOURCES);
276612f080e7Smrj 	}
276712f080e7Smrj 
276812f080e7Smrj 	DTRACE_PROBE2(rootnex__alloc__copybuf, dev_info_t *, dma->dp_dip,
276912f080e7Smrj 	    size_t, dma->dp_copybuf_size);
277012f080e7Smrj 
277112f080e7Smrj 	return (DDI_SUCCESS);
277212f080e7Smrj }
277312f080e7Smrj 
277412f080e7Smrj 
277512f080e7Smrj /*
277612f080e7Smrj  * rootnex_setup_windows()
277712f080e7Smrj  *    Called in bind slowpath to setup the window state. We always have windows
277812f080e7Smrj  *    in the slowpath. Even if the window count = 1.
277912f080e7Smrj  */
278012f080e7Smrj static int
278112f080e7Smrj rootnex_setup_windows(ddi_dma_impl_t *hp, rootnex_dma_t *dma,
278212f080e7Smrj     ddi_dma_attr_t *attr, int kmflag)
278312f080e7Smrj {
278412f080e7Smrj 	rootnex_window_t *windowp;
278512f080e7Smrj 	rootnex_sglinfo_t *sinfo;
278612f080e7Smrj 	size_t copy_state_size;
278712f080e7Smrj 	size_t win_state_size;
278812f080e7Smrj 	size_t state_available;
278912f080e7Smrj 	size_t space_needed;
279012f080e7Smrj 	uint_t copybuf_win;
279112f080e7Smrj 	uint_t maxxfer_win;
279212f080e7Smrj 	size_t space_used;
279312f080e7Smrj 	uint_t sglwin;
279412f080e7Smrj 
279512f080e7Smrj 
279612f080e7Smrj 	sinfo = &dma->dp_sglinfo;
279712f080e7Smrj 
279812f080e7Smrj 	dma->dp_current_win = 0;
279912f080e7Smrj 	hp->dmai_nwin = 0;
280012f080e7Smrj 
280112f080e7Smrj 	/* If we don't need to do a partial, we only have one window */
280212f080e7Smrj 	if (!dma->dp_partial_required) {
280312f080e7Smrj 		dma->dp_max_win = 1;
280412f080e7Smrj 
280512f080e7Smrj 	/*
280612f080e7Smrj 	 * we need multiple windows, need to figure out the worse case number
280712f080e7Smrj 	 * of windows.
280812f080e7Smrj 	 */
28097c478bd9Sstevel@tonic-gate 	} else {
28107c478bd9Sstevel@tonic-gate 		/*
281112f080e7Smrj 		 * if we need windows because we need more copy buffer that
281212f080e7Smrj 		 * we allow, the worse case number of windows we could need
281312f080e7Smrj 		 * here would be (copybuf space required / copybuf space that
281412f080e7Smrj 		 * we have) plus one for remainder, and plus 2 to handle the
281512f080e7Smrj 		 * extra pages on the trim for the first and last pages of the
281612f080e7Smrj 		 * buffer (a page is the minimum window size so under the right
281712f080e7Smrj 		 * attr settings, you could have a window for each page).
281812f080e7Smrj 		 * The last page will only be hit here if the size is not a
281912f080e7Smrj 		 * multiple of the granularity (which theoretically shouldn't
282012f080e7Smrj 		 * be the case but never has been enforced, so we could have
282112f080e7Smrj 		 * broken things without it).
28227c478bd9Sstevel@tonic-gate 		 */
282312f080e7Smrj 		if (sinfo->si_copybuf_req > dma->dp_copybuf_size) {
282412f080e7Smrj 			ASSERT(dma->dp_copybuf_size > 0);
282512f080e7Smrj 			copybuf_win = (sinfo->si_copybuf_req /
282612f080e7Smrj 			    dma->dp_copybuf_size) + 1 + 2;
28277c478bd9Sstevel@tonic-gate 		} else {
282812f080e7Smrj 			copybuf_win = 0;
28297c478bd9Sstevel@tonic-gate 		}
283012f080e7Smrj 
283112f080e7Smrj 		/*
283212f080e7Smrj 		 * if we need windows because we have more cookies than the H/W
283312f080e7Smrj 		 * can handle, the number of windows we would need here would
283412f080e7Smrj 		 * be (cookie count / cookies count H/W supports) plus one for
283512f080e7Smrj 		 * remainder, and plus 2 to handle the extra pages on the trim
283612f080e7Smrj 		 * (see above comment about trim)
283712f080e7Smrj 		 */
283812f080e7Smrj 		if (attr->dma_attr_sgllen < sinfo->si_sgl_size) {
283912f080e7Smrj 			sglwin = ((sinfo->si_sgl_size / attr->dma_attr_sgllen)
284012f080e7Smrj 			    + 1) + 2;
28417c478bd9Sstevel@tonic-gate 		} else {
284212f080e7Smrj 			sglwin = 0;
28437c478bd9Sstevel@tonic-gate 		}
284412f080e7Smrj 
284512f080e7Smrj 		/*
284612f080e7Smrj 		 * if we need windows because we're binding more memory than the
284712f080e7Smrj 		 * H/W can transfer at once, the number of windows we would need
284812f080e7Smrj 		 * here would be (xfer count / max xfer H/W supports) plus one
284912f080e7Smrj 		 * for remainder, and plus 2 to handle the extra pages on the
285012f080e7Smrj 		 * trim (see above comment about trim)
285112f080e7Smrj 		 */
285212f080e7Smrj 		if (dma->dp_dma.dmao_size > dma->dp_maxxfer) {
285312f080e7Smrj 			maxxfer_win = (dma->dp_dma.dmao_size /
285412f080e7Smrj 			    dma->dp_maxxfer) + 1 + 2;
285512f080e7Smrj 		} else {
285612f080e7Smrj 			maxxfer_win = 0;
28577c478bd9Sstevel@tonic-gate 		}
285812f080e7Smrj 		dma->dp_max_win =  copybuf_win + sglwin + maxxfer_win;
285912f080e7Smrj 		ASSERT(dma->dp_max_win > 0);
286012f080e7Smrj 	}
286112f080e7Smrj 	win_state_size = dma->dp_max_win * sizeof (rootnex_window_t);
286212f080e7Smrj 
286312f080e7Smrj 	/*
286412f080e7Smrj 	 * Get space for window and potential copy buffer state. Before we
286512f080e7Smrj 	 * go and allocate memory, see if we can get away with using what's
286612f080e7Smrj 	 * left in the pre-allocted state or the dynamically allocated sgl.
286712f080e7Smrj 	 */
286812f080e7Smrj 	space_used = (uintptr_t)(sinfo->si_sgl_size *
286912f080e7Smrj 	    sizeof (ddi_dma_cookie_t));
287012f080e7Smrj 
287112f080e7Smrj 	/* if we dynamically allocated space for the cookies */
287212f080e7Smrj 	if (dma->dp_need_to_free_cookie) {
287312f080e7Smrj 		/* if we have more space in the pre-allocted buffer, use it */
287412f080e7Smrj 		ASSERT(space_used <= dma->dp_cookie_size);
287512f080e7Smrj 		if ((dma->dp_cookie_size - space_used) <=
287612f080e7Smrj 		    rootnex_state->r_prealloc_size) {
287712f080e7Smrj 			state_available = rootnex_state->r_prealloc_size;
287812f080e7Smrj 			windowp = (rootnex_window_t *)dma->dp_prealloc_buffer;
287912f080e7Smrj 
288012f080e7Smrj 		/*
288112f080e7Smrj 		 * else, we have more free space in the dynamically allocated
288212f080e7Smrj 		 * buffer, i.e. the buffer wasn't worse case fragmented so we
288312f080e7Smrj 		 * didn't need a lot of cookies.
288412f080e7Smrj 		 */
288512f080e7Smrj 		} else {
288612f080e7Smrj 			state_available = dma->dp_cookie_size - space_used;
288712f080e7Smrj 			windowp = (rootnex_window_t *)
288812f080e7Smrj 			    &dma->dp_cookies[sinfo->si_sgl_size];
288912f080e7Smrj 		}
289012f080e7Smrj 
289112f080e7Smrj 	/* we used the pre-alloced buffer */
289212f080e7Smrj 	} else {
289312f080e7Smrj 		ASSERT(space_used <= rootnex_state->r_prealloc_size);
289412f080e7Smrj 		state_available = rootnex_state->r_prealloc_size - space_used;
289512f080e7Smrj 		windowp = (rootnex_window_t *)
289612f080e7Smrj 		    &dma->dp_cookies[sinfo->si_sgl_size];
289712f080e7Smrj 	}
289812f080e7Smrj 
289912f080e7Smrj 	/*
290012f080e7Smrj 	 * figure out how much state we need to track the copy buffer. Add an
290112f080e7Smrj 	 * addition 8 bytes for pointer alignemnt later.
290212f080e7Smrj 	 */
290312f080e7Smrj 	if (dma->dp_copybuf_size > 0) {
290412f080e7Smrj 		copy_state_size = sinfo->si_max_pages *
290512f080e7Smrj 		    sizeof (rootnex_pgmap_t);
290612f080e7Smrj 	} else {
290712f080e7Smrj 		copy_state_size = 0;
290812f080e7Smrj 	}
290912f080e7Smrj 	/* add an additional 8 bytes for pointer alignment */
291012f080e7Smrj 	space_needed = win_state_size + copy_state_size + 0x8;
291112f080e7Smrj 
291212f080e7Smrj 	/* if we have enough space already, use it */
291312f080e7Smrj 	if (state_available >= space_needed) {
291412f080e7Smrj 		dma->dp_window = windowp;
291512f080e7Smrj 		dma->dp_need_to_free_window = B_FALSE;
291612f080e7Smrj 
291712f080e7Smrj 	/* not enough space, need to allocate more. */
291812f080e7Smrj 	} else {
291912f080e7Smrj 		dma->dp_window = kmem_alloc(space_needed, kmflag);
292012f080e7Smrj 		if (dma->dp_window == NULL) {
292112f080e7Smrj 			return (DDI_DMA_NORESOURCES);
292212f080e7Smrj 		}
292312f080e7Smrj 		dma->dp_need_to_free_window = B_TRUE;
292412f080e7Smrj 		dma->dp_window_size = space_needed;
292512f080e7Smrj 		DTRACE_PROBE2(rootnex__bind__sp__alloc, dev_info_t *,
292612f080e7Smrj 		    dma->dp_dip, size_t, space_needed);
292712f080e7Smrj 	}
292812f080e7Smrj 
292912f080e7Smrj 	/*
293012f080e7Smrj 	 * we allocate copy buffer state and window state at the same time.
293112f080e7Smrj 	 * setup our copy buffer state pointers. Make sure it's aligned.
293212f080e7Smrj 	 */
293312f080e7Smrj 	if (dma->dp_copybuf_size > 0) {
293412f080e7Smrj 		dma->dp_pgmap = (rootnex_pgmap_t *)(((uintptr_t)
293512f080e7Smrj 		    &dma->dp_window[dma->dp_max_win] + 0x7) & ~0x7);
293612f080e7Smrj 
293712f080e7Smrj #if !defined(__amd64)
293812f080e7Smrj 		/*
293912f080e7Smrj 		 * make sure all pm_mapped, pm_vaddr, and pm_pp are set to
294012f080e7Smrj 		 * false/NULL. Should be quicker to bzero vs loop and set.
294112f080e7Smrj 		 */
294212f080e7Smrj 		bzero(dma->dp_pgmap, copy_state_size);
294312f080e7Smrj #endif
294412f080e7Smrj 	} else {
294512f080e7Smrj 		dma->dp_pgmap = NULL;
294612f080e7Smrj 	}
294712f080e7Smrj 
294812f080e7Smrj 	return (DDI_SUCCESS);
294912f080e7Smrj }
295012f080e7Smrj 
295112f080e7Smrj 
295212f080e7Smrj /*
295312f080e7Smrj  * rootnex_teardown_copybuf()
295412f080e7Smrj  *    cleans up after rootnex_setup_copybuf()
295512f080e7Smrj  */
295612f080e7Smrj static void
295712f080e7Smrj rootnex_teardown_copybuf(rootnex_dma_t *dma)
295812f080e7Smrj {
295912f080e7Smrj #if !defined(__amd64)
296012f080e7Smrj 	int i;
296112f080e7Smrj 
296212f080e7Smrj 	/*
296312f080e7Smrj 	 * if we allocated kernel heap VMEM space, go through all the pages and
296412f080e7Smrj 	 * map out any of the ones that we're mapped into the kernel heap VMEM
296512f080e7Smrj 	 * arena. Then free the VMEM space.
296612f080e7Smrj 	 */
296712f080e7Smrj 	if (dma->dp_kva != NULL) {
296812f080e7Smrj 		for (i = 0; i < dma->dp_sglinfo.si_max_pages; i++) {
296912f080e7Smrj 			if (dma->dp_pgmap[i].pm_mapped) {
297012f080e7Smrj 				hat_unload(kas.a_hat, dma->dp_pgmap[i].pm_kaddr,
297112f080e7Smrj 				    MMU_PAGESIZE, HAT_UNLOAD);
297212f080e7Smrj 				dma->dp_pgmap[i].pm_mapped = B_FALSE;
297312f080e7Smrj 			}
297412f080e7Smrj 		}
297512f080e7Smrj 
297612f080e7Smrj 		vmem_free(heap_arena, dma->dp_kva, dma->dp_copybuf_size);
297712f080e7Smrj 	}
297812f080e7Smrj 
297912f080e7Smrj #endif
298012f080e7Smrj 
298112f080e7Smrj 	/* if we allocated a copy buffer, free it */
298212f080e7Smrj 	if (dma->dp_cbaddr != NULL) {
298312f080e7Smrj 		i_ddi_mem_free(dma->dp_cbaddr, 0);
298412f080e7Smrj 	}
298512f080e7Smrj }
298612f080e7Smrj 
298712f080e7Smrj 
298812f080e7Smrj /*
298912f080e7Smrj  * rootnex_teardown_windows()
299012f080e7Smrj  *    cleans up after rootnex_setup_windows()
299112f080e7Smrj  */
299212f080e7Smrj static void
299312f080e7Smrj rootnex_teardown_windows(rootnex_dma_t *dma)
299412f080e7Smrj {
299512f080e7Smrj 	/*
299612f080e7Smrj 	 * if we had to allocate window state on the last bind (because we
299712f080e7Smrj 	 * didn't have enough pre-allocated space in the handle), free it.
299812f080e7Smrj 	 */
299912f080e7Smrj 	if (dma->dp_need_to_free_window) {
300012f080e7Smrj 		kmem_free(dma->dp_window, dma->dp_window_size);
300112f080e7Smrj 	}
300212f080e7Smrj }
300312f080e7Smrj 
300412f080e7Smrj 
300512f080e7Smrj /*
300612f080e7Smrj  * rootnex_init_win()
300712f080e7Smrj  *    Called in bind slow path during creation of a new window. Initializes
300812f080e7Smrj  *    window state to default values.
300912f080e7Smrj  */
301012f080e7Smrj /*ARGSUSED*/
301112f080e7Smrj static void
301212f080e7Smrj rootnex_init_win(ddi_dma_impl_t *hp, rootnex_dma_t *dma,
301312f080e7Smrj     rootnex_window_t *window, ddi_dma_cookie_t *cookie, off_t cur_offset)
301412f080e7Smrj {
301512f080e7Smrj 	hp->dmai_nwin++;
301612f080e7Smrj 	window->wd_dosync = B_FALSE;
301712f080e7Smrj 	window->wd_offset = cur_offset;
301812f080e7Smrj 	window->wd_size = 0;
301912f080e7Smrj 	window->wd_first_cookie = cookie;
302012f080e7Smrj 	window->wd_cookie_cnt = 0;
302112f080e7Smrj 	window->wd_trim.tr_trim_first = B_FALSE;
302212f080e7Smrj 	window->wd_trim.tr_trim_last = B_FALSE;
302312f080e7Smrj 	window->wd_trim.tr_first_copybuf_win = B_FALSE;
302412f080e7Smrj 	window->wd_trim.tr_last_copybuf_win = B_FALSE;
302512f080e7Smrj #if !defined(__amd64)
302612f080e7Smrj 	window->wd_remap_copybuf = dma->dp_cb_remaping;
302712f080e7Smrj #endif
302812f080e7Smrj }
302912f080e7Smrj 
303012f080e7Smrj 
303112f080e7Smrj /*
303212f080e7Smrj  * rootnex_setup_cookie()
303312f080e7Smrj  *    Called in the bind slow path when the sgl uses the copy buffer. If any of
303412f080e7Smrj  *    the sgl uses the copy buffer, we need to go through each cookie, figure
303512f080e7Smrj  *    out if it uses the copy buffer, and if it does, save away everything we'll
303612f080e7Smrj  *    need during sync.
303712f080e7Smrj  */
303812f080e7Smrj static void
303912f080e7Smrj rootnex_setup_cookie(ddi_dma_obj_t *dmar_object, rootnex_dma_t *dma,
304012f080e7Smrj     ddi_dma_cookie_t *cookie, off_t cur_offset, size_t *copybuf_used,
304112f080e7Smrj     page_t **cur_pp)
304212f080e7Smrj {
304312f080e7Smrj 	boolean_t copybuf_sz_power_2;
304412f080e7Smrj 	rootnex_sglinfo_t *sinfo;
304512f080e7Smrj 	uint_t pidx;
304612f080e7Smrj 	uint_t pcnt;
304712f080e7Smrj 	off_t poff;
304812f080e7Smrj #if defined(__amd64)
304912f080e7Smrj 	pfn_t pfn;
305012f080e7Smrj #else
305112f080e7Smrj 	page_t **pplist;
305212f080e7Smrj #endif
305312f080e7Smrj 
305412f080e7Smrj 	sinfo = &dma->dp_sglinfo;
305512f080e7Smrj 
305612f080e7Smrj 	/*
305712f080e7Smrj 	 * Calculate the page index relative to the start of the buffer. The
305812f080e7Smrj 	 * index to the current page for our buffer is the offset into the
305912f080e7Smrj 	 * first page of the buffer plus our current offset into the buffer
306012f080e7Smrj 	 * itself, shifted of course...
306112f080e7Smrj 	 */
306212f080e7Smrj 	pidx = (sinfo->si_buf_offset + cur_offset) >> MMU_PAGESHIFT;
306312f080e7Smrj 	ASSERT(pidx < sinfo->si_max_pages);
306412f080e7Smrj 
306512f080e7Smrj 	/* if this cookie uses the copy buffer */
306612f080e7Smrj 	if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) {
306712f080e7Smrj 		/*
306812f080e7Smrj 		 * NOTE: we know that since this cookie uses the copy buffer, it
306912f080e7Smrj 		 * is <= MMU_PAGESIZE.
307012f080e7Smrj 		 */
307112f080e7Smrj 
307212f080e7Smrj 		/*
307312f080e7Smrj 		 * get the offset into the page. For the 64-bit kernel, get the
307412f080e7Smrj 		 * pfn which we'll use with seg kpm.
307512f080e7Smrj 		 */
307612f080e7Smrj 		poff = cookie->_dmu._dmac_ll & MMU_PAGEOFFSET;
307712f080e7Smrj #if defined(__amd64)
307812f080e7Smrj 		pfn = cookie->_dmu._dmac_ll >> MMU_PAGESHIFT;
307912f080e7Smrj #endif
308012f080e7Smrj 
308112f080e7Smrj 		/* figure out if the copybuf size is a power of 2 */
308212f080e7Smrj 		if (dma->dp_copybuf_size & (dma->dp_copybuf_size - 1)) {
308312f080e7Smrj 			copybuf_sz_power_2 = B_FALSE;
308412f080e7Smrj 		} else {
308512f080e7Smrj 			copybuf_sz_power_2 = B_TRUE;
308612f080e7Smrj 		}
308712f080e7Smrj 
308812f080e7Smrj 		/* This page uses the copy buffer */
308912f080e7Smrj 		dma->dp_pgmap[pidx].pm_uses_copybuf = B_TRUE;
309012f080e7Smrj 
309112f080e7Smrj 		/*
309212f080e7Smrj 		 * save the copy buffer KVA that we'll use with this page.
309312f080e7Smrj 		 * if we still fit within the copybuf, it's a simple add.
309412f080e7Smrj 		 * otherwise, we need to wrap over using & or % accordingly.
309512f080e7Smrj 		 */
309612f080e7Smrj 		if ((*copybuf_used + MMU_PAGESIZE) <= dma->dp_copybuf_size) {
309712f080e7Smrj 			dma->dp_pgmap[pidx].pm_cbaddr = dma->dp_cbaddr +
309812f080e7Smrj 			    *copybuf_used;
309912f080e7Smrj 		} else {
310012f080e7Smrj 			if (copybuf_sz_power_2) {
310112f080e7Smrj 				dma->dp_pgmap[pidx].pm_cbaddr = (caddr_t)(
310212f080e7Smrj 				    (uintptr_t)dma->dp_cbaddr +
310312f080e7Smrj 				    (*copybuf_used &
310412f080e7Smrj 				    (dma->dp_copybuf_size - 1)));
310512f080e7Smrj 			} else {
310612f080e7Smrj 				dma->dp_pgmap[pidx].pm_cbaddr = (caddr_t)(
310712f080e7Smrj 				    (uintptr_t)dma->dp_cbaddr +
310812f080e7Smrj 				    (*copybuf_used % dma->dp_copybuf_size));
310912f080e7Smrj 			}
311012f080e7Smrj 		}
311112f080e7Smrj 
311212f080e7Smrj 		/*
311312f080e7Smrj 		 * over write the cookie physical address with the address of
311412f080e7Smrj 		 * the physical address of the copy buffer page that we will
311512f080e7Smrj 		 * use.
311612f080e7Smrj 		 */
311712f080e7Smrj 		cookie->_dmu._dmac_ll = ptob64(hat_getpfnum(kas.a_hat,
311812f080e7Smrj 		    dma->dp_pgmap[pidx].pm_cbaddr)) + poff;
311912f080e7Smrj 
312012f080e7Smrj 		/* if we have a kernel VA, it's easy, just save that address */
312112f080e7Smrj 		if ((dmar_object->dmao_type != DMA_OTYP_PAGES) &&
312212f080e7Smrj 		    (sinfo->si_asp == &kas)) {
312312f080e7Smrj 			/*
312412f080e7Smrj 			 * save away the page aligned virtual address of the
312512f080e7Smrj 			 * driver buffer. Offsets are handled in the sync code.
312612f080e7Smrj 			 */
312712f080e7Smrj 			dma->dp_pgmap[pidx].pm_kaddr = (caddr_t)(((uintptr_t)
312812f080e7Smrj 			    dmar_object->dmao_obj.virt_obj.v_addr + cur_offset)
312912f080e7Smrj 			    & MMU_PAGEMASK);
313012f080e7Smrj #if !defined(__amd64)
313112f080e7Smrj 			/*
313212f080e7Smrj 			 * we didn't need to, and will never need to map this
313312f080e7Smrj 			 * page.
313412f080e7Smrj 			 */
313512f080e7Smrj 			dma->dp_pgmap[pidx].pm_mapped = B_FALSE;
313612f080e7Smrj #endif
313712f080e7Smrj 
313812f080e7Smrj 		/* we don't have a kernel VA. We need one for the bcopy. */
313912f080e7Smrj 		} else {
314012f080e7Smrj #if defined(__amd64)
314112f080e7Smrj 			/*
314212f080e7Smrj 			 * for the 64-bit kernel, it's easy. We use seg kpm to
314312f080e7Smrj 			 * get a Kernel VA for the corresponding pfn.
314412f080e7Smrj 			 */
314512f080e7Smrj 			dma->dp_pgmap[pidx].pm_kaddr = hat_kpm_pfn2va(pfn);
314612f080e7Smrj #else
314712f080e7Smrj 			/*
314812f080e7Smrj 			 * for the 32-bit kernel, this is a pain. First we'll
314912f080e7Smrj 			 * save away the page_t or user VA for this page. This
315012f080e7Smrj 			 * is needed in rootnex_dma_win() when we switch to a
315112f080e7Smrj 			 * new window which requires us to re-map the copy
315212f080e7Smrj 			 * buffer.
315312f080e7Smrj 			 */
315412f080e7Smrj 			pplist = dmar_object->dmao_obj.virt_obj.v_priv;
315512f080e7Smrj 			if (dmar_object->dmao_type == DMA_OTYP_PAGES) {
315612f080e7Smrj 				dma->dp_pgmap[pidx].pm_pp = *cur_pp;
315712f080e7Smrj 				dma->dp_pgmap[pidx].pm_vaddr = NULL;
315812f080e7Smrj 			} else if (pplist != NULL) {
315912f080e7Smrj 				dma->dp_pgmap[pidx].pm_pp = pplist[pidx];
316012f080e7Smrj 				dma->dp_pgmap[pidx].pm_vaddr = NULL;
316112f080e7Smrj 			} else {
316212f080e7Smrj 				dma->dp_pgmap[pidx].pm_pp = NULL;
316312f080e7Smrj 				dma->dp_pgmap[pidx].pm_vaddr = (caddr_t)
316412f080e7Smrj 				    (((uintptr_t)
316512f080e7Smrj 				    dmar_object->dmao_obj.virt_obj.v_addr +
316612f080e7Smrj 				    cur_offset) & MMU_PAGEMASK);
316712f080e7Smrj 			}
316812f080e7Smrj 
316912f080e7Smrj 			/*
317012f080e7Smrj 			 * save away the page aligned virtual address which was
317112f080e7Smrj 			 * allocated from the kernel heap arena (taking into
317212f080e7Smrj 			 * account if we need more copy buffer than we alloced
317312f080e7Smrj 			 * and use multiple windows to handle this, i.e. &,%).
317412f080e7Smrj 			 * NOTE: there isn't and physical memory backing up this
317512f080e7Smrj 			 * virtual address space currently.
317612f080e7Smrj 			 */
317712f080e7Smrj 			if ((*copybuf_used + MMU_PAGESIZE) <=
317812f080e7Smrj 			    dma->dp_copybuf_size) {
317912f080e7Smrj 				dma->dp_pgmap[pidx].pm_kaddr = (caddr_t)
318012f080e7Smrj 				    (((uintptr_t)dma->dp_kva + *copybuf_used) &
318112f080e7Smrj 				    MMU_PAGEMASK);
318212f080e7Smrj 			} else {
318312f080e7Smrj 				if (copybuf_sz_power_2) {
318412f080e7Smrj 					dma->dp_pgmap[pidx].pm_kaddr = (caddr_t)
318512f080e7Smrj 					    (((uintptr_t)dma->dp_kva +
318612f080e7Smrj 					    (*copybuf_used &
318712f080e7Smrj 					    (dma->dp_copybuf_size - 1))) &
318812f080e7Smrj 					    MMU_PAGEMASK);
318912f080e7Smrj 				} else {
319012f080e7Smrj 					dma->dp_pgmap[pidx].pm_kaddr = (caddr_t)
319112f080e7Smrj 					    (((uintptr_t)dma->dp_kva +
319212f080e7Smrj 					    (*copybuf_used %
319312f080e7Smrj 					    dma->dp_copybuf_size)) &
319412f080e7Smrj 					    MMU_PAGEMASK);
319512f080e7Smrj 				}
319612f080e7Smrj 			}
319712f080e7Smrj 
319812f080e7Smrj 			/*
319912f080e7Smrj 			 * if we haven't used up the available copy buffer yet,
320012f080e7Smrj 			 * map the kva to the physical page.
320112f080e7Smrj 			 */
320212f080e7Smrj 			if (!dma->dp_cb_remaping && ((*copybuf_used +
320312f080e7Smrj 			    MMU_PAGESIZE) <= dma->dp_copybuf_size)) {
320412f080e7Smrj 				dma->dp_pgmap[pidx].pm_mapped = B_TRUE;
320512f080e7Smrj 				if (dma->dp_pgmap[pidx].pm_pp != NULL) {
320612f080e7Smrj 					i86_pp_map(dma->dp_pgmap[pidx].pm_pp,
320712f080e7Smrj 					    dma->dp_pgmap[pidx].pm_kaddr);
320812f080e7Smrj 				} else {
320912f080e7Smrj 					i86_va_map(dma->dp_pgmap[pidx].pm_vaddr,
321012f080e7Smrj 					    sinfo->si_asp,
321112f080e7Smrj 					    dma->dp_pgmap[pidx].pm_kaddr);
321212f080e7Smrj 				}
321312f080e7Smrj 
321412f080e7Smrj 			/*
321512f080e7Smrj 			 * we've used up the available copy buffer, this page
321612f080e7Smrj 			 * will have to be mapped during rootnex_dma_win() when
321712f080e7Smrj 			 * we switch to a new window which requires a re-map
321812f080e7Smrj 			 * the copy buffer. (32-bit kernel only)
321912f080e7Smrj 			 */
322012f080e7Smrj 			} else {
322112f080e7Smrj 				dma->dp_pgmap[pidx].pm_mapped = B_FALSE;
322212f080e7Smrj 			}
322312f080e7Smrj #endif
322412f080e7Smrj 			/* go to the next page_t */
322512f080e7Smrj 			if (dmar_object->dmao_type == DMA_OTYP_PAGES) {
322612f080e7Smrj 				*cur_pp = (*cur_pp)->p_next;
322712f080e7Smrj 			}
322812f080e7Smrj 		}
322912f080e7Smrj 
323012f080e7Smrj 		/* add to the copy buffer count */
323112f080e7Smrj 		*copybuf_used += MMU_PAGESIZE;
323212f080e7Smrj 
323312f080e7Smrj 	/*
323412f080e7Smrj 	 * This cookie doesn't use the copy buffer. Walk through the pages this
323512f080e7Smrj 	 * cookie occupies to reflect this.
323612f080e7Smrj 	 */
323712f080e7Smrj 	} else {
323812f080e7Smrj 		/*
323912f080e7Smrj 		 * figure out how many pages the cookie occupies. We need to
324012f080e7Smrj 		 * use the original page offset of the buffer and the cookies
324112f080e7Smrj 		 * offset in the buffer to do this.
324212f080e7Smrj 		 */
324312f080e7Smrj 		poff = (sinfo->si_buf_offset + cur_offset) & MMU_PAGEOFFSET;
324412f080e7Smrj 		pcnt = mmu_btopr(cookie->dmac_size + poff);
324512f080e7Smrj 
324612f080e7Smrj 		while (pcnt > 0) {
324712f080e7Smrj #if !defined(__amd64)
324812f080e7Smrj 			/*
324912f080e7Smrj 			 * the 32-bit kernel doesn't have seg kpm, so we need
325012f080e7Smrj 			 * to map in the driver buffer (if it didn't come down
325112f080e7Smrj 			 * with a kernel VA) on the fly. Since this page doesn't
325212f080e7Smrj 			 * use the copy buffer, it's not, or will it ever, have
325312f080e7Smrj 			 * to be mapped in.
325412f080e7Smrj 			 */
325512f080e7Smrj 			dma->dp_pgmap[pidx].pm_mapped = B_FALSE;
325612f080e7Smrj #endif
325712f080e7Smrj 			dma->dp_pgmap[pidx].pm_uses_copybuf = B_FALSE;
325812f080e7Smrj 
325912f080e7Smrj 			/*
326012f080e7Smrj 			 * we need to update pidx and cur_pp or we'll loose
326112f080e7Smrj 			 * track of where we are.
326212f080e7Smrj 			 */
326312f080e7Smrj 			if (dmar_object->dmao_type == DMA_OTYP_PAGES) {
326412f080e7Smrj 				*cur_pp = (*cur_pp)->p_next;
326512f080e7Smrj 			}
326612f080e7Smrj 			pidx++;
326712f080e7Smrj 			pcnt--;
326812f080e7Smrj 		}
326912f080e7Smrj 	}
327012f080e7Smrj }
327112f080e7Smrj 
327212f080e7Smrj 
327312f080e7Smrj /*
327412f080e7Smrj  * rootnex_sgllen_window_boundary()
327512f080e7Smrj  *    Called in the bind slow path when the next cookie causes us to exceed (in
327612f080e7Smrj  *    this case == since we start at 0 and sgllen starts at 1) the maximum sgl
327712f080e7Smrj  *    length supported by the DMA H/W.
327812f080e7Smrj  */
327912f080e7Smrj static int
328012f080e7Smrj rootnex_sgllen_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma,
328112f080e7Smrj     rootnex_window_t **windowp, ddi_dma_cookie_t *cookie, ddi_dma_attr_t *attr,
328212f080e7Smrj     off_t cur_offset)
328312f080e7Smrj {
328412f080e7Smrj 	off_t new_offset;
328512f080e7Smrj 	size_t trim_sz;
328612f080e7Smrj 	off_t coffset;
328712f080e7Smrj 
328812f080e7Smrj 
328912f080e7Smrj 	/*
329012f080e7Smrj 	 * if we know we'll never have to trim, it's pretty easy. Just move to
329112f080e7Smrj 	 * the next window and init it. We're done.
329212f080e7Smrj 	 */
329312f080e7Smrj 	if (!dma->dp_trim_required) {
329412f080e7Smrj 		(*windowp)++;
329512f080e7Smrj 		rootnex_init_win(hp, dma, *windowp, cookie, cur_offset);
329612f080e7Smrj 		(*windowp)->wd_cookie_cnt++;
329712f080e7Smrj 		(*windowp)->wd_size = cookie->dmac_size;
329812f080e7Smrj 		return (DDI_SUCCESS);
329912f080e7Smrj 	}
330012f080e7Smrj 
330112f080e7Smrj 	/* figure out how much we need to trim from the window */
330212f080e7Smrj 	ASSERT(attr->dma_attr_granular != 0);
330312f080e7Smrj 	if (dma->dp_granularity_power_2) {
330412f080e7Smrj 		trim_sz = (*windowp)->wd_size & (attr->dma_attr_granular - 1);
330512f080e7Smrj 	} else {
330612f080e7Smrj 		trim_sz = (*windowp)->wd_size % attr->dma_attr_granular;
330712f080e7Smrj 	}
330812f080e7Smrj 
330912f080e7Smrj 	/* The window's a whole multiple of granularity. We're done */
331012f080e7Smrj 	if (trim_sz == 0) {
331112f080e7Smrj 		(*windowp)++;
331212f080e7Smrj 		rootnex_init_win(hp, dma, *windowp, cookie, cur_offset);
331312f080e7Smrj 		(*windowp)->wd_cookie_cnt++;
331412f080e7Smrj 		(*windowp)->wd_size = cookie->dmac_size;
331512f080e7Smrj 		return (DDI_SUCCESS);
331612f080e7Smrj 	}
331712f080e7Smrj 
331812f080e7Smrj 	/*
331912f080e7Smrj 	 * The window's not a whole multiple of granularity, since we know this
332012f080e7Smrj 	 * is due to the sgllen, we need to go back to the last cookie and trim
332112f080e7Smrj 	 * that one, add the left over part of the old cookie into the new
332212f080e7Smrj 	 * window, and then add in the new cookie into the new window.
332312f080e7Smrj 	 */
332412f080e7Smrj 
332512f080e7Smrj 	/*
332612f080e7Smrj 	 * make sure the driver isn't making us do something bad... Trimming and
332712f080e7Smrj 	 * sgllen == 1 don't go together.
332812f080e7Smrj 	 */
332912f080e7Smrj 	if (attr->dma_attr_sgllen == 1) {
333012f080e7Smrj 		return (DDI_DMA_NOMAPPING);
333112f080e7Smrj 	}
333212f080e7Smrj 
333312f080e7Smrj 	/*
333412f080e7Smrj 	 * first, setup the current window to account for the trim. Need to go
333512f080e7Smrj 	 * back to the last cookie for this.
333612f080e7Smrj 	 */
333712f080e7Smrj 	cookie--;
333812f080e7Smrj 	(*windowp)->wd_trim.tr_trim_last = B_TRUE;
333912f080e7Smrj 	(*windowp)->wd_trim.tr_last_cookie = cookie;
334012f080e7Smrj 	(*windowp)->wd_trim.tr_last_paddr = cookie->_dmu._dmac_ll;
334112f080e7Smrj 	ASSERT(cookie->dmac_size > trim_sz);
334212f080e7Smrj 	(*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz;
334312f080e7Smrj 	(*windowp)->wd_size -= trim_sz;
334412f080e7Smrj 
334512f080e7Smrj 	/* save the buffer offsets for the next window */
334612f080e7Smrj 	coffset = cookie->dmac_size - trim_sz;
334712f080e7Smrj 	new_offset = (*windowp)->wd_offset + (*windowp)->wd_size;
334812f080e7Smrj 
334912f080e7Smrj 	/*
335012f080e7Smrj 	 * set this now in case this is the first window. all other cases are
335112f080e7Smrj 	 * set in dma_win()
335212f080e7Smrj 	 */
335312f080e7Smrj 	cookie->dmac_size = (*windowp)->wd_trim.tr_last_size;
335412f080e7Smrj 
335512f080e7Smrj 	/*
335612f080e7Smrj 	 * initialize the next window using what's left over in the previous
335712f080e7Smrj 	 * cookie.
335812f080e7Smrj 	 */
335912f080e7Smrj 	(*windowp)++;
336012f080e7Smrj 	rootnex_init_win(hp, dma, *windowp, cookie, new_offset);
336112f080e7Smrj 	(*windowp)->wd_cookie_cnt++;
336212f080e7Smrj 	(*windowp)->wd_trim.tr_trim_first = B_TRUE;
336312f080e7Smrj 	(*windowp)->wd_trim.tr_first_paddr = cookie->_dmu._dmac_ll + coffset;
336412f080e7Smrj 	(*windowp)->wd_trim.tr_first_size = trim_sz;
336512f080e7Smrj 	if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) {
336612f080e7Smrj 		(*windowp)->wd_dosync = B_TRUE;
336712f080e7Smrj 	}
336812f080e7Smrj 
336912f080e7Smrj 	/*
337012f080e7Smrj 	 * now go back to the current cookie and add it to the new window. set
337112f080e7Smrj 	 * the new window size to the what was left over from the previous
337212f080e7Smrj 	 * cookie and what's in the current cookie.
337312f080e7Smrj 	 */
337412f080e7Smrj 	cookie++;
337512f080e7Smrj 	(*windowp)->wd_cookie_cnt++;
337612f080e7Smrj 	(*windowp)->wd_size = trim_sz + cookie->dmac_size;
337712f080e7Smrj 
337812f080e7Smrj 	/*
337912f080e7Smrj 	 * trim plus the next cookie could put us over maxxfer (a cookie can be
338012f080e7Smrj 	 * a max size of maxxfer). Handle that case.
338112f080e7Smrj 	 */
338212f080e7Smrj 	if ((*windowp)->wd_size > dma->dp_maxxfer) {
338312f080e7Smrj 		/*
338412f080e7Smrj 		 * maxxfer is already a whole multiple of granularity, and this
338512f080e7Smrj 		 * trim will be <= the previous trim (since a cookie can't be
338612f080e7Smrj 		 * larger than maxxfer). Make things simple here.
338712f080e7Smrj 		 */
338812f080e7Smrj 		trim_sz = (*windowp)->wd_size - dma->dp_maxxfer;
338912f080e7Smrj 		(*windowp)->wd_trim.tr_trim_last = B_TRUE;
339012f080e7Smrj 		(*windowp)->wd_trim.tr_last_cookie = cookie;
339112f080e7Smrj 		(*windowp)->wd_trim.tr_last_paddr = cookie->_dmu._dmac_ll;
339212f080e7Smrj 		(*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz;
339312f080e7Smrj 		(*windowp)->wd_size -= trim_sz;
339412f080e7Smrj 		ASSERT((*windowp)->wd_size == dma->dp_maxxfer);
339512f080e7Smrj 
339612f080e7Smrj 		/* save the buffer offsets for the next window */
339712f080e7Smrj 		coffset = cookie->dmac_size - trim_sz;
339812f080e7Smrj 		new_offset = (*windowp)->wd_offset + (*windowp)->wd_size;
339912f080e7Smrj 
340012f080e7Smrj 		/* setup the next window */
340112f080e7Smrj 		(*windowp)++;
340212f080e7Smrj 		rootnex_init_win(hp, dma, *windowp, cookie, new_offset);
340312f080e7Smrj 		(*windowp)->wd_cookie_cnt++;
340412f080e7Smrj 		(*windowp)->wd_trim.tr_trim_first = B_TRUE;
340512f080e7Smrj 		(*windowp)->wd_trim.tr_first_paddr = cookie->_dmu._dmac_ll +
340612f080e7Smrj 		    coffset;
340712f080e7Smrj 		(*windowp)->wd_trim.tr_first_size = trim_sz;
340812f080e7Smrj 	}
340912f080e7Smrj 
341012f080e7Smrj 	return (DDI_SUCCESS);
341112f080e7Smrj }
341212f080e7Smrj 
341312f080e7Smrj 
341412f080e7Smrj /*
341512f080e7Smrj  * rootnex_copybuf_window_boundary()
341612f080e7Smrj  *    Called in bind slowpath when we get to a window boundary because we used
341712f080e7Smrj  *    up all the copy buffer that we have.
341812f080e7Smrj  */
341912f080e7Smrj static int
342012f080e7Smrj rootnex_copybuf_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma,
342112f080e7Smrj     rootnex_window_t **windowp, ddi_dma_cookie_t *cookie, off_t cur_offset,
342212f080e7Smrj     size_t *copybuf_used)
342312f080e7Smrj {
342412f080e7Smrj 	rootnex_sglinfo_t *sinfo;
342512f080e7Smrj 	off_t new_offset;
342612f080e7Smrj 	size_t trim_sz;
342712f080e7Smrj 	off_t coffset;
342812f080e7Smrj 	uint_t pidx;
342912f080e7Smrj 	off_t poff;
343012f080e7Smrj 
343112f080e7Smrj 
343212f080e7Smrj 	sinfo = &dma->dp_sglinfo;
343312f080e7Smrj 
343412f080e7Smrj 	/*
343512f080e7Smrj 	 * the copy buffer should be a whole multiple of page size. We know that
343612f080e7Smrj 	 * this cookie is <= MMU_PAGESIZE.
343712f080e7Smrj 	 */
343812f080e7Smrj 	ASSERT(cookie->dmac_size <= MMU_PAGESIZE);
343912f080e7Smrj 
344012f080e7Smrj 	/*
344112f080e7Smrj 	 * from now on, all new windows in this bind need to be re-mapped during
344212f080e7Smrj 	 * ddi_dma_getwin() (32-bit kernel only). i.e. we ran out out copybuf
344312f080e7Smrj 	 * space...
344412f080e7Smrj 	 */
344512f080e7Smrj #if !defined(__amd64)
344612f080e7Smrj 	dma->dp_cb_remaping = B_TRUE;
344712f080e7Smrj #endif
344812f080e7Smrj 
344912f080e7Smrj 	/* reset copybuf used */
345012f080e7Smrj 	*copybuf_used = 0;
345112f080e7Smrj 
345212f080e7Smrj 	/*
345312f080e7Smrj 	 * if we don't have to trim (since granularity is set to 1), go to the
345412f080e7Smrj 	 * next window and add the current cookie to it. We know the current
345512f080e7Smrj 	 * cookie uses the copy buffer since we're in this code path.
345612f080e7Smrj 	 */
345712f080e7Smrj 	if (!dma->dp_trim_required) {
345812f080e7Smrj 		(*windowp)++;
345912f080e7Smrj 		rootnex_init_win(hp, dma, *windowp, cookie, cur_offset);
346012f080e7Smrj 
346112f080e7Smrj 		/* Add this cookie to the new window */
346212f080e7Smrj 		(*windowp)->wd_cookie_cnt++;
346312f080e7Smrj 		(*windowp)->wd_size += cookie->dmac_size;
346412f080e7Smrj 		*copybuf_used += MMU_PAGESIZE;
346512f080e7Smrj 		return (DDI_SUCCESS);
346612f080e7Smrj 	}
346712f080e7Smrj 
346812f080e7Smrj 	/*
346912f080e7Smrj 	 * *** may need to trim, figure it out.
347012f080e7Smrj 	 */
347112f080e7Smrj 
347212f080e7Smrj 	/* figure out how much we need to trim from the window */
347312f080e7Smrj 	if (dma->dp_granularity_power_2) {
347412f080e7Smrj 		trim_sz = (*windowp)->wd_size &
347512f080e7Smrj 		    (hp->dmai_attr.dma_attr_granular - 1);
347612f080e7Smrj 	} else {
347712f080e7Smrj 		trim_sz = (*windowp)->wd_size % hp->dmai_attr.dma_attr_granular;
347812f080e7Smrj 	}
347912f080e7Smrj 
348012f080e7Smrj 	/*
348112f080e7Smrj 	 * if the window's a whole multiple of granularity, go to the next
348212f080e7Smrj 	 * window, init it, then add in the current cookie. We know the current
348312f080e7Smrj 	 * cookie uses the copy buffer since we're in this code path.
348412f080e7Smrj 	 */
348512f080e7Smrj 	if (trim_sz == 0) {
348612f080e7Smrj 		(*windowp)++;
348712f080e7Smrj 		rootnex_init_win(hp, dma, *windowp, cookie, cur_offset);
348812f080e7Smrj 
348912f080e7Smrj 		/* Add this cookie to the new window */
349012f080e7Smrj 		(*windowp)->wd_cookie_cnt++;
349112f080e7Smrj 		(*windowp)->wd_size += cookie->dmac_size;
349212f080e7Smrj 		*copybuf_used += MMU_PAGESIZE;
349312f080e7Smrj 		return (DDI_SUCCESS);
349412f080e7Smrj 	}
349512f080e7Smrj 
349612f080e7Smrj 	/*
349712f080e7Smrj 	 * *** We figured it out, we definitly need to trim
349812f080e7Smrj 	 */
349912f080e7Smrj 
350012f080e7Smrj 	/*
350112f080e7Smrj 	 * make sure the driver isn't making us do something bad...
350212f080e7Smrj 	 * Trimming and sgllen == 1 don't go together.
350312f080e7Smrj 	 */
350412f080e7Smrj 	if (hp->dmai_attr.dma_attr_sgllen == 1) {
350512f080e7Smrj 		return (DDI_DMA_NOMAPPING);
350612f080e7Smrj 	}
350712f080e7Smrj 
350812f080e7Smrj 	/*
350912f080e7Smrj 	 * first, setup the current window to account for the trim. Need to go
351012f080e7Smrj 	 * back to the last cookie for this. Some of the last cookie will be in
351112f080e7Smrj 	 * the current window, and some of the last cookie will be in the new
351212f080e7Smrj 	 * window. All of the current cookie will be in the new window.
351312f080e7Smrj 	 */
351412f080e7Smrj 	cookie--;
351512f080e7Smrj 	(*windowp)->wd_trim.tr_trim_last = B_TRUE;
351612f080e7Smrj 	(*windowp)->wd_trim.tr_last_cookie = cookie;
351712f080e7Smrj 	(*windowp)->wd_trim.tr_last_paddr = cookie->_dmu._dmac_ll;
351812f080e7Smrj 	ASSERT(cookie->dmac_size > trim_sz);
351912f080e7Smrj 	(*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz;
352012f080e7Smrj 	(*windowp)->wd_size -= trim_sz;
352112f080e7Smrj 
352212f080e7Smrj 	/*
352312f080e7Smrj 	 * we're trimming the last cookie (not the current cookie). So that
352412f080e7Smrj 	 * last cookie may have or may not have been using the copy buffer (
352512f080e7Smrj 	 * we know the cookie passed in uses the copy buffer since we're in
352612f080e7Smrj 	 * this code path).
352712f080e7Smrj 	 *
352812f080e7Smrj 	 * If the last cookie doesn't use the copy buffer, nothing special to
352912f080e7Smrj 	 * do. However, if it does uses the copy buffer, it will be both the
353012f080e7Smrj 	 * last page in the current window and the first page in the next
353112f080e7Smrj 	 * window. Since we are reusing the copy buffer (and KVA space on the
353212f080e7Smrj 	 * 32-bit kernel), this page will use the end of the copy buffer in the
353312f080e7Smrj 	 * current window, and the start of the copy buffer in the next window.
353412f080e7Smrj 	 * Track that info... The cookie physical address was already set to
353512f080e7Smrj 	 * the copy buffer physical address in setup_cookie..
353612f080e7Smrj 	 */
353712f080e7Smrj 	if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) {
353812f080e7Smrj 		pidx = (sinfo->si_buf_offset + (*windowp)->wd_offset +
353912f080e7Smrj 		    (*windowp)->wd_size) >> MMU_PAGESHIFT;
354012f080e7Smrj 		(*windowp)->wd_trim.tr_last_copybuf_win = B_TRUE;
354112f080e7Smrj 		(*windowp)->wd_trim.tr_last_pidx = pidx;
354212f080e7Smrj 		(*windowp)->wd_trim.tr_last_cbaddr =
354312f080e7Smrj 		    dma->dp_pgmap[pidx].pm_cbaddr;
354412f080e7Smrj #if !defined(__amd64)
354512f080e7Smrj 		(*windowp)->wd_trim.tr_last_kaddr =
354612f080e7Smrj 		    dma->dp_pgmap[pidx].pm_kaddr;
354712f080e7Smrj #endif
354812f080e7Smrj 	}
354912f080e7Smrj 
355012f080e7Smrj 	/* save the buffer offsets for the next window */
355112f080e7Smrj 	coffset = cookie->dmac_size - trim_sz;
355212f080e7Smrj 	new_offset = (*windowp)->wd_offset + (*windowp)->wd_size;
355312f080e7Smrj 
355412f080e7Smrj 	/*
355512f080e7Smrj 	 * set this now in case this is the first window. all other cases are
355612f080e7Smrj 	 * set in dma_win()
355712f080e7Smrj 	 */
355812f080e7Smrj 	cookie->dmac_size = (*windowp)->wd_trim.tr_last_size;
355912f080e7Smrj 
356012f080e7Smrj 	/*
356112f080e7Smrj 	 * initialize the next window using what's left over in the previous
356212f080e7Smrj 	 * cookie.
356312f080e7Smrj 	 */
356412f080e7Smrj 	(*windowp)++;
356512f080e7Smrj 	rootnex_init_win(hp, dma, *windowp, cookie, new_offset);
356612f080e7Smrj 	(*windowp)->wd_cookie_cnt++;
356712f080e7Smrj 	(*windowp)->wd_trim.tr_trim_first = B_TRUE;
356812f080e7Smrj 	(*windowp)->wd_trim.tr_first_paddr = cookie->_dmu._dmac_ll + coffset;
356912f080e7Smrj 	(*windowp)->wd_trim.tr_first_size = trim_sz;
357012f080e7Smrj 
357112f080e7Smrj 	/*
357212f080e7Smrj 	 * again, we're tracking if the last cookie uses the copy buffer.
357312f080e7Smrj 	 * read the comment above for more info on why we need to track
357412f080e7Smrj 	 * additional state.
357512f080e7Smrj 	 *
357612f080e7Smrj 	 * For the first cookie in the new window, we need reset the physical
357712f080e7Smrj 	 * address to DMA into to the start of the copy buffer plus any
357812f080e7Smrj 	 * initial page offset which may be present.
357912f080e7Smrj 	 */
358012f080e7Smrj 	if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) {
358112f080e7Smrj 		(*windowp)->wd_dosync = B_TRUE;
358212f080e7Smrj 		(*windowp)->wd_trim.tr_first_copybuf_win = B_TRUE;
358312f080e7Smrj 		(*windowp)->wd_trim.tr_first_pidx = pidx;
358412f080e7Smrj 		(*windowp)->wd_trim.tr_first_cbaddr = dma->dp_cbaddr;
358512f080e7Smrj 		poff = (*windowp)->wd_trim.tr_first_paddr & MMU_PAGEOFFSET;
358612f080e7Smrj 		(*windowp)->wd_trim.tr_first_paddr = ptob64(hat_getpfnum(
358712f080e7Smrj 		    kas.a_hat, dma->dp_cbaddr)) + poff;
358812f080e7Smrj #if !defined(__amd64)
358912f080e7Smrj 		(*windowp)->wd_trim.tr_first_kaddr = dma->dp_kva;
359012f080e7Smrj #endif
359112f080e7Smrj 		/* account for the cookie copybuf usage in the new window */
359212f080e7Smrj 		*copybuf_used += MMU_PAGESIZE;
359312f080e7Smrj 
359412f080e7Smrj 		/*
359512f080e7Smrj 		 * every piece of code has to have a hack, and here is this
359612f080e7Smrj 		 * ones :-)
359712f080e7Smrj 		 *
359812f080e7Smrj 		 * There is a complex interaction between setup_cookie and the
359912f080e7Smrj 		 * copybuf window boundary. The complexity had to be in either
360012f080e7Smrj 		 * the maxxfer window, or the copybuf window, and I chose the
360112f080e7Smrj 		 * copybuf code.
360212f080e7Smrj 		 *
360312f080e7Smrj 		 * So in this code path, we have taken the last cookie,
360412f080e7Smrj 		 * virtually broken it in half due to the trim, and it happens
360512f080e7Smrj 		 * to use the copybuf which further complicates life. At the
360612f080e7Smrj 		 * same time, we have already setup the current cookie, which
360712f080e7Smrj 		 * is now wrong. More background info: the current cookie uses
360812f080e7Smrj 		 * the copybuf, so it is only a page long max. So we need to
360912f080e7Smrj 		 * fix the current cookies copy buffer address, physical
361012f080e7Smrj 		 * address, and kva for the 32-bit kernel. We due this by
361112f080e7Smrj 		 * bumping them by page size (of course, we can't due this on
361212f080e7Smrj 		 * the physical address since the copy buffer may not be
361312f080e7Smrj 		 * physically contiguous).
361412f080e7Smrj 		 */
361512f080e7Smrj 		cookie++;
361612f080e7Smrj 		dma->dp_pgmap[pidx + 1].pm_cbaddr += MMU_PAGESIZE;
361712f080e7Smrj 		poff = cookie->_dmu._dmac_ll & MMU_PAGEOFFSET;
361812f080e7Smrj 		cookie->_dmu._dmac_ll = ptob64(hat_getpfnum(kas.a_hat,
361912f080e7Smrj 		    dma->dp_pgmap[pidx + 1].pm_cbaddr)) + poff;
362012f080e7Smrj #if !defined(__amd64)
362112f080e7Smrj 		ASSERT(dma->dp_pgmap[pidx + 1].pm_mapped == B_FALSE);
362212f080e7Smrj 		dma->dp_pgmap[pidx + 1].pm_kaddr += MMU_PAGESIZE;
362312f080e7Smrj #endif
362412f080e7Smrj 	} else {
362512f080e7Smrj 		/* go back to the current cookie */
362612f080e7Smrj 		cookie++;
362712f080e7Smrj 	}
362812f080e7Smrj 
362912f080e7Smrj 	/*
363012f080e7Smrj 	 * add the current cookie to the new window. set the new window size to
363112f080e7Smrj 	 * the what was left over from the previous cookie and what's in the
363212f080e7Smrj 	 * current cookie.
363312f080e7Smrj 	 */
363412f080e7Smrj 	(*windowp)->wd_cookie_cnt++;
363512f080e7Smrj 	(*windowp)->wd_size = trim_sz + cookie->dmac_size;
363612f080e7Smrj 	ASSERT((*windowp)->wd_size < dma->dp_maxxfer);
363712f080e7Smrj 
363812f080e7Smrj 	/*
363912f080e7Smrj 	 * we know that the cookie passed in always uses the copy buffer. We
364012f080e7Smrj 	 * wouldn't be here if it didn't.
364112f080e7Smrj 	 */
364212f080e7Smrj 	*copybuf_used += MMU_PAGESIZE;
364312f080e7Smrj 
364412f080e7Smrj 	return (DDI_SUCCESS);
364512f080e7Smrj }
364612f080e7Smrj 
364712f080e7Smrj 
364812f080e7Smrj /*
364912f080e7Smrj  * rootnex_maxxfer_window_boundary()
365012f080e7Smrj  *    Called in bind slowpath when we get to a window boundary because we will
365112f080e7Smrj  *    go over maxxfer.
365212f080e7Smrj  */
365312f080e7Smrj static int
365412f080e7Smrj rootnex_maxxfer_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma,
365512f080e7Smrj     rootnex_window_t **windowp, ddi_dma_cookie_t *cookie)
365612f080e7Smrj {
365712f080e7Smrj 	size_t dmac_size;
365812f080e7Smrj 	off_t new_offset;
365912f080e7Smrj 	size_t trim_sz;
366012f080e7Smrj 	off_t coffset;
366112f080e7Smrj 
366212f080e7Smrj 
366312f080e7Smrj 	/*
366412f080e7Smrj 	 * calculate how much we have to trim off of the current cookie to equal
366512f080e7Smrj 	 * maxxfer. We don't have to account for granularity here since our
366612f080e7Smrj 	 * maxxfer already takes that into account.
366712f080e7Smrj 	 */
366812f080e7Smrj 	trim_sz = ((*windowp)->wd_size + cookie->dmac_size) - dma->dp_maxxfer;
366912f080e7Smrj 	ASSERT(trim_sz <= cookie->dmac_size);
367012f080e7Smrj 	ASSERT(trim_sz <= dma->dp_maxxfer);
367112f080e7Smrj 
367212f080e7Smrj 	/* save cookie size since we need it later and we might change it */
367312f080e7Smrj 	dmac_size = cookie->dmac_size;
367412f080e7Smrj 
367512f080e7Smrj 	/*
367612f080e7Smrj 	 * if we're not trimming the entire cookie, setup the current window to
367712f080e7Smrj 	 * account for the trim.
367812f080e7Smrj 	 */
367912f080e7Smrj 	if (trim_sz < cookie->dmac_size) {
368012f080e7Smrj 		(*windowp)->wd_cookie_cnt++;
368112f080e7Smrj 		(*windowp)->wd_trim.tr_trim_last = B_TRUE;
368212f080e7Smrj 		(*windowp)->wd_trim.tr_last_cookie = cookie;
368312f080e7Smrj 		(*windowp)->wd_trim.tr_last_paddr = cookie->_dmu._dmac_ll;
368412f080e7Smrj 		(*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz;
368512f080e7Smrj 		(*windowp)->wd_size = dma->dp_maxxfer;
368612f080e7Smrj 
368712f080e7Smrj 		/*
368812f080e7Smrj 		 * set the adjusted cookie size now in case this is the first
368912f080e7Smrj 		 * window. All other windows are taken care of in get win
369012f080e7Smrj 		 */
369112f080e7Smrj 		cookie->dmac_size = (*windowp)->wd_trim.tr_last_size;
369212f080e7Smrj 	}
369312f080e7Smrj 
369412f080e7Smrj 	/*
369512f080e7Smrj 	 * coffset is the current offset within the cookie, new_offset is the
369612f080e7Smrj 	 * current offset with the entire buffer.
369712f080e7Smrj 	 */
369812f080e7Smrj 	coffset = dmac_size - trim_sz;
369912f080e7Smrj 	new_offset = (*windowp)->wd_offset + (*windowp)->wd_size;
370012f080e7Smrj 
370112f080e7Smrj 	/* initialize the next window */
370212f080e7Smrj 	(*windowp)++;
370312f080e7Smrj 	rootnex_init_win(hp, dma, *windowp, cookie, new_offset);
370412f080e7Smrj 	(*windowp)->wd_cookie_cnt++;
370512f080e7Smrj 	(*windowp)->wd_size = trim_sz;
370612f080e7Smrj 	if (trim_sz < dmac_size) {
370712f080e7Smrj 		(*windowp)->wd_trim.tr_trim_first = B_TRUE;
370812f080e7Smrj 		(*windowp)->wd_trim.tr_first_paddr = cookie->_dmu._dmac_ll +
370912f080e7Smrj 		    coffset;
371012f080e7Smrj 		(*windowp)->wd_trim.tr_first_size = trim_sz;
371112f080e7Smrj 	}
371212f080e7Smrj 
371312f080e7Smrj 	return (DDI_SUCCESS);
371412f080e7Smrj }
371512f080e7Smrj 
371612f080e7Smrj 
371712f080e7Smrj /*
371812f080e7Smrj  * rootnex_dma_sync()
371912f080e7Smrj  *    called from ddi_dma_sync() if DMP_NOSYNC is not set in hp->dmai_rflags.
372012f080e7Smrj  *    We set DMP_NOSYNC if we're not using the copy buffer. If DMP_NOSYNC
372112f080e7Smrj  *    is set, ddi_dma_sync() returns immediately passing back success.
372212f080e7Smrj  */
372312f080e7Smrj /*ARGSUSED*/
372412f080e7Smrj static int
372512f080e7Smrj rootnex_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
372612f080e7Smrj     off_t off, size_t len, uint_t cache_flags)
372712f080e7Smrj {
372812f080e7Smrj 	rootnex_sglinfo_t *sinfo;
372912f080e7Smrj 	rootnex_pgmap_t *cbpage;
373012f080e7Smrj 	rootnex_window_t *win;
373112f080e7Smrj 	ddi_dma_impl_t *hp;
373212f080e7Smrj 	rootnex_dma_t *dma;
373312f080e7Smrj 	caddr_t fromaddr;
373412f080e7Smrj 	caddr_t toaddr;
373512f080e7Smrj 	uint_t psize;
373612f080e7Smrj 	off_t offset;
373712f080e7Smrj 	uint_t pidx;
373812f080e7Smrj 	size_t size;
373912f080e7Smrj 	off_t poff;
374012f080e7Smrj 	int e;
374112f080e7Smrj 
374212f080e7Smrj 
374312f080e7Smrj 	hp = (ddi_dma_impl_t *)handle;
374412f080e7Smrj 	dma = (rootnex_dma_t *)hp->dmai_private;
374512f080e7Smrj 	sinfo = &dma->dp_sglinfo;
374612f080e7Smrj 
374712f080e7Smrj 	/*
374812f080e7Smrj 	 * if we don't have any windows, we don't need to sync. A copybuf
374912f080e7Smrj 	 * will cause us to have at least one window.
375012f080e7Smrj 	 */
375112f080e7Smrj 	if (dma->dp_window == NULL) {
375212f080e7Smrj 		return (DDI_SUCCESS);
375312f080e7Smrj 	}
375412f080e7Smrj 
375512f080e7Smrj 	/* This window may not need to be sync'd */
375612f080e7Smrj 	win = &dma->dp_window[dma->dp_current_win];
375712f080e7Smrj 	if (!win->wd_dosync) {
375812f080e7Smrj 		return (DDI_SUCCESS);
375912f080e7Smrj 	}
376012f080e7Smrj 
376112f080e7Smrj 	/* handle off and len special cases */
376212f080e7Smrj 	if ((off == 0) || (rootnex_sync_ignore_params)) {
376312f080e7Smrj 		offset = win->wd_offset;
376412f080e7Smrj 	} else {
376512f080e7Smrj 		offset = off;
376612f080e7Smrj 	}
376712f080e7Smrj 	if ((len == 0) || (rootnex_sync_ignore_params)) {
376812f080e7Smrj 		size = win->wd_size;
376912f080e7Smrj 	} else {
377012f080e7Smrj 		size = len;
377112f080e7Smrj 	}
377212f080e7Smrj 
377312f080e7Smrj 	/* check the sync args to make sure they make a little sense */
377412f080e7Smrj 	if (rootnex_sync_check_parms) {
377512f080e7Smrj 		e = rootnex_valid_sync_parms(hp, win, offset, size,
377612f080e7Smrj 		    cache_flags);
377712f080e7Smrj 		if (e != DDI_SUCCESS) {
377812f080e7Smrj 			ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_SYNC_FAIL]);
377912f080e7Smrj 			return (DDI_FAILURE);
378012f080e7Smrj 		}
378112f080e7Smrj 	}
378212f080e7Smrj 
378312f080e7Smrj 	/*
378412f080e7Smrj 	 * special case the first page to handle the offset into the page. The
378512f080e7Smrj 	 * offset to the current page for our buffer is the offset into the
378612f080e7Smrj 	 * first page of the buffer plus our current offset into the buffer
378712f080e7Smrj 	 * itself, masked of course.
378812f080e7Smrj 	 */
378912f080e7Smrj 	poff = (sinfo->si_buf_offset + offset) & MMU_PAGEOFFSET;
379012f080e7Smrj 	psize = MIN((MMU_PAGESIZE - poff), size);
379112f080e7Smrj 
379212f080e7Smrj 	/* go through all the pages that we want to sync */
379312f080e7Smrj 	while (size > 0) {
379412f080e7Smrj 		/*
379512f080e7Smrj 		 * Calculate the page index relative to the start of the buffer.
379612f080e7Smrj 		 * The index to the current page for our buffer is the offset
379712f080e7Smrj 		 * into the first page of the buffer plus our current offset
379812f080e7Smrj 		 * into the buffer itself, shifted of course...
379912f080e7Smrj 		 */
380012f080e7Smrj 		pidx = (sinfo->si_buf_offset + offset) >> MMU_PAGESHIFT;
380112f080e7Smrj 		ASSERT(pidx < sinfo->si_max_pages);
380212f080e7Smrj 
380312f080e7Smrj 		/*
380412f080e7Smrj 		 * if this page uses the copy buffer, we need to sync it,
380512f080e7Smrj 		 * otherwise, go on to the next page.
380612f080e7Smrj 		 */
380712f080e7Smrj 		cbpage = &dma->dp_pgmap[pidx];
380812f080e7Smrj 		ASSERT((cbpage->pm_uses_copybuf == B_TRUE) ||
380912f080e7Smrj 		    (cbpage->pm_uses_copybuf == B_FALSE));
381012f080e7Smrj 		if (cbpage->pm_uses_copybuf) {
381112f080e7Smrj 			/* cbaddr and kaddr should be page aligned */
381212f080e7Smrj 			ASSERT(((uintptr_t)cbpage->pm_cbaddr &
381312f080e7Smrj 			    MMU_PAGEOFFSET) == 0);
381412f080e7Smrj 			ASSERT(((uintptr_t)cbpage->pm_kaddr &
381512f080e7Smrj 			    MMU_PAGEOFFSET) == 0);
381612f080e7Smrj 
381712f080e7Smrj 			/*
381812f080e7Smrj 			 * if we're copying for the device, we are going to
381912f080e7Smrj 			 * copy from the drivers buffer and to the rootnex
382012f080e7Smrj 			 * allocated copy buffer.
382112f080e7Smrj 			 */
382212f080e7Smrj 			if (cache_flags == DDI_DMA_SYNC_FORDEV) {
382312f080e7Smrj 				fromaddr = cbpage->pm_kaddr + poff;
382412f080e7Smrj 				toaddr = cbpage->pm_cbaddr + poff;
382512f080e7Smrj 				DTRACE_PROBE2(rootnex__sync__dev,
382612f080e7Smrj 				    dev_info_t *, dma->dp_dip, size_t, psize);
382712f080e7Smrj 
382812f080e7Smrj 			/*
382912f080e7Smrj 			 * if we're copying for the cpu/kernel, we are going to
383012f080e7Smrj 			 * copy from the rootnex allocated copy buffer to the
383112f080e7Smrj 			 * drivers buffer.
383212f080e7Smrj 			 */
383312f080e7Smrj 			} else {
383412f080e7Smrj 				fromaddr = cbpage->pm_cbaddr + poff;
383512f080e7Smrj 				toaddr = cbpage->pm_kaddr + poff;
383612f080e7Smrj 				DTRACE_PROBE2(rootnex__sync__cpu,
383712f080e7Smrj 				    dev_info_t *, dma->dp_dip, size_t, psize);
383812f080e7Smrj 			}
383912f080e7Smrj 
384012f080e7Smrj 			bcopy(fromaddr, toaddr, psize);
384112f080e7Smrj 		}
384212f080e7Smrj 
384312f080e7Smrj 		/*
384412f080e7Smrj 		 * decrement size until we're done, update our offset into the
384512f080e7Smrj 		 * buffer, and get the next page size.
384612f080e7Smrj 		 */
384712f080e7Smrj 		size -= psize;
384812f080e7Smrj 		offset += psize;
384912f080e7Smrj 		psize = MIN(MMU_PAGESIZE, size);
385012f080e7Smrj 
385112f080e7Smrj 		/* page offset is zero for the rest of this loop */
385212f080e7Smrj 		poff = 0;
385312f080e7Smrj 	}
385412f080e7Smrj 
385512f080e7Smrj 	return (DDI_SUCCESS);
385612f080e7Smrj }
385712f080e7Smrj 
385812f080e7Smrj 
385912f080e7Smrj /*
386012f080e7Smrj  * rootnex_valid_sync_parms()
386112f080e7Smrj  *    checks the parameters passed to sync to verify they are correct.
386212f080e7Smrj  */
386312f080e7Smrj static int
386412f080e7Smrj rootnex_valid_sync_parms(ddi_dma_impl_t *hp, rootnex_window_t *win,
386512f080e7Smrj     off_t offset, size_t size, uint_t cache_flags)
386612f080e7Smrj {
386712f080e7Smrj 	off_t woffset;
386812f080e7Smrj 
386912f080e7Smrj 
387012f080e7Smrj 	/*
387112f080e7Smrj 	 * the first part of the test to make sure the offset passed in is
387212f080e7Smrj 	 * within the window.
387312f080e7Smrj 	 */
387412f080e7Smrj 	if (offset < win->wd_offset) {
387512f080e7Smrj 		return (DDI_FAILURE);
387612f080e7Smrj 	}
387712f080e7Smrj 
387812f080e7Smrj 	/*
387912f080e7Smrj 	 * second and last part of the test to make sure the offset and length
388012f080e7Smrj 	 * passed in is within the window.
388112f080e7Smrj 	 */
388212f080e7Smrj 	woffset = offset - win->wd_offset;
388312f080e7Smrj 	if ((woffset + size) > win->wd_size) {
388412f080e7Smrj 		return (DDI_FAILURE);
388512f080e7Smrj 	}
388612f080e7Smrj 
388712f080e7Smrj 	/*
388812f080e7Smrj 	 * if we are sync'ing for the device, the DDI_DMA_WRITE flag should
388912f080e7Smrj 	 * be set too.
389012f080e7Smrj 	 */
389112f080e7Smrj 	if ((cache_flags == DDI_DMA_SYNC_FORDEV) &&
389212f080e7Smrj 	    (hp->dmai_rflags & DDI_DMA_WRITE)) {
389312f080e7Smrj 		return (DDI_SUCCESS);
389412f080e7Smrj 	}
389512f080e7Smrj 
389612f080e7Smrj 	/*
389712f080e7Smrj 	 * at this point, either DDI_DMA_SYNC_FORCPU or DDI_DMA_SYNC_FORKERNEL
389812f080e7Smrj 	 * should be set. Also DDI_DMA_READ should be set in the flags.
389912f080e7Smrj 	 */
390012f080e7Smrj 	if (((cache_flags == DDI_DMA_SYNC_FORCPU) ||
390112f080e7Smrj 	    (cache_flags == DDI_DMA_SYNC_FORKERNEL)) &&
390212f080e7Smrj 	    (hp->dmai_rflags & DDI_DMA_READ)) {
390312f080e7Smrj 		return (DDI_SUCCESS);
390412f080e7Smrj 	}
390512f080e7Smrj 
390612f080e7Smrj 	return (DDI_FAILURE);
390712f080e7Smrj }
390812f080e7Smrj 
390912f080e7Smrj 
391012f080e7Smrj /*
391112f080e7Smrj  * rootnex_dma_win()
391212f080e7Smrj  *    called from ddi_dma_getwin()
391312f080e7Smrj  */
391412f080e7Smrj /*ARGSUSED*/
391512f080e7Smrj static int
391612f080e7Smrj rootnex_dma_win(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
391712f080e7Smrj     uint_t win, off_t *offp, size_t *lenp, ddi_dma_cookie_t *cookiep,
391812f080e7Smrj     uint_t *ccountp)
391912f080e7Smrj {
392012f080e7Smrj 	rootnex_window_t *window;
392112f080e7Smrj 	rootnex_trim_t *trim;
392212f080e7Smrj 	ddi_dma_impl_t *hp;
392312f080e7Smrj 	rootnex_dma_t *dma;
392412f080e7Smrj #if !defined(__amd64)
392512f080e7Smrj 	rootnex_sglinfo_t *sinfo;
392612f080e7Smrj 	rootnex_pgmap_t *pmap;
392712f080e7Smrj 	uint_t pidx;
392812f080e7Smrj 	uint_t pcnt;
392912f080e7Smrj 	off_t poff;
393012f080e7Smrj 	int i;
393112f080e7Smrj #endif
393212f080e7Smrj 
393312f080e7Smrj 
393412f080e7Smrj 	hp = (ddi_dma_impl_t *)handle;
393512f080e7Smrj 	dma = (rootnex_dma_t *)hp->dmai_private;
393612f080e7Smrj #if !defined(__amd64)
393712f080e7Smrj 	sinfo = &dma->dp_sglinfo;
393812f080e7Smrj #endif
393912f080e7Smrj 
394012f080e7Smrj 	/* If we try and get a window which doesn't exist, return failure */
394112f080e7Smrj 	if (win >= hp->dmai_nwin) {
394212f080e7Smrj 		ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_GETWIN_FAIL]);
394312f080e7Smrj 		return (DDI_FAILURE);
394412f080e7Smrj 	}
394512f080e7Smrj 
394612f080e7Smrj 	/*
394712f080e7Smrj 	 * if we don't have any windows, and they're asking for the first
394812f080e7Smrj 	 * window, setup the cookie pointer to the first cookie in the bind.
394912f080e7Smrj 	 * setup our return values, then increment the cookie since we return
395012f080e7Smrj 	 * the first cookie on the stack.
395112f080e7Smrj 	 */
395212f080e7Smrj 	if (dma->dp_window == NULL) {
395312f080e7Smrj 		if (win != 0) {
395412f080e7Smrj 			ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_GETWIN_FAIL]);
395512f080e7Smrj 			return (DDI_FAILURE);
395612f080e7Smrj 		}
395712f080e7Smrj 		hp->dmai_cookie = dma->dp_cookies;
395812f080e7Smrj 		*offp = 0;
395912f080e7Smrj 		*lenp = dma->dp_dma.dmao_size;
396012f080e7Smrj 		*ccountp = dma->dp_sglinfo.si_sgl_size;
396112f080e7Smrj 		*cookiep = hp->dmai_cookie[0];
396212f080e7Smrj 		hp->dmai_cookie++;
396312f080e7Smrj 		return (DDI_SUCCESS);
396412f080e7Smrj 	}
396512f080e7Smrj 
396612f080e7Smrj 	/* sync the old window before moving on to the new one */
396712f080e7Smrj 	window = &dma->dp_window[dma->dp_current_win];
396812f080e7Smrj 	if ((window->wd_dosync) && (hp->dmai_rflags & DDI_DMA_READ)) {
396912f080e7Smrj 		(void) rootnex_dma_sync(dip, rdip, handle, 0, 0,
397012f080e7Smrj 		    DDI_DMA_SYNC_FORCPU);
397112f080e7Smrj 	}
397212f080e7Smrj 
397312f080e7Smrj #if !defined(__amd64)
397412f080e7Smrj 	/*
397512f080e7Smrj 	 * before we move to the next window, if we need to re-map, unmap all
397612f080e7Smrj 	 * the pages in this window.
397712f080e7Smrj 	 */
397812f080e7Smrj 	if (dma->dp_cb_remaping) {
397912f080e7Smrj 		/*
398012f080e7Smrj 		 * If we switch to this window again, we'll need to map in
398112f080e7Smrj 		 * on the fly next time.
398212f080e7Smrj 		 */
398312f080e7Smrj 		window->wd_remap_copybuf = B_TRUE;
398412f080e7Smrj 
398512f080e7Smrj 		/*
398612f080e7Smrj 		 * calculate the page index into the buffer where this window
398712f080e7Smrj 		 * starts, and the number of pages this window takes up.
398812f080e7Smrj 		 */
398912f080e7Smrj 		pidx = (sinfo->si_buf_offset + window->wd_offset) >>
399012f080e7Smrj 		    MMU_PAGESHIFT;
399112f080e7Smrj 		poff = (sinfo->si_buf_offset + window->wd_offset) &
399212f080e7Smrj 		    MMU_PAGEOFFSET;
399312f080e7Smrj 		pcnt = mmu_btopr(window->wd_size + poff);
399412f080e7Smrj 		ASSERT((pidx + pcnt) <= sinfo->si_max_pages);
399512f080e7Smrj 
399612f080e7Smrj 		/* unmap pages which are currently mapped in this window */
399712f080e7Smrj 		for (i = 0; i < pcnt; i++) {
399812f080e7Smrj 			if (dma->dp_pgmap[pidx].pm_mapped) {
399912f080e7Smrj 				hat_unload(kas.a_hat,
400012f080e7Smrj 				    dma->dp_pgmap[pidx].pm_kaddr, MMU_PAGESIZE,
400112f080e7Smrj 				    HAT_UNLOAD);
400212f080e7Smrj 				dma->dp_pgmap[pidx].pm_mapped = B_FALSE;
400312f080e7Smrj 			}
400412f080e7Smrj 			pidx++;
400512f080e7Smrj 		}
400612f080e7Smrj 	}
400712f080e7Smrj #endif
400812f080e7Smrj 
400912f080e7Smrj 	/*
401012f080e7Smrj 	 * Move to the new window.
401112f080e7Smrj 	 * NOTE: current_win must be set for sync to work right
401212f080e7Smrj 	 */
401312f080e7Smrj 	dma->dp_current_win = win;
401412f080e7Smrj 	window = &dma->dp_window[win];
401512f080e7Smrj 
401612f080e7Smrj 	/* if needed, adjust the first and/or last cookies for trim */
401712f080e7Smrj 	trim = &window->wd_trim;
401812f080e7Smrj 	if (trim->tr_trim_first) {
401912f080e7Smrj 		window->wd_first_cookie->_dmu._dmac_ll = trim->tr_first_paddr;
402012f080e7Smrj 		window->wd_first_cookie->dmac_size = trim->tr_first_size;
402112f080e7Smrj #if !defined(__amd64)
402212f080e7Smrj 		window->wd_first_cookie->dmac_type =
402312f080e7Smrj 		    (window->wd_first_cookie->dmac_type &
402412f080e7Smrj 		    ROOTNEX_USES_COPYBUF) + window->wd_offset;
402512f080e7Smrj #endif
402612f080e7Smrj 		if (trim->tr_first_copybuf_win) {
402712f080e7Smrj 			dma->dp_pgmap[trim->tr_first_pidx].pm_cbaddr =
402812f080e7Smrj 			    trim->tr_first_cbaddr;
402912f080e7Smrj #if !defined(__amd64)
403012f080e7Smrj 			dma->dp_pgmap[trim->tr_first_pidx].pm_kaddr =
403112f080e7Smrj 			    trim->tr_first_kaddr;
403212f080e7Smrj #endif
403312f080e7Smrj 		}
403412f080e7Smrj 	}
403512f080e7Smrj 	if (trim->tr_trim_last) {
403612f080e7Smrj 		trim->tr_last_cookie->_dmu._dmac_ll = trim->tr_last_paddr;
403712f080e7Smrj 		trim->tr_last_cookie->dmac_size = trim->tr_last_size;
403812f080e7Smrj 		if (trim->tr_last_copybuf_win) {
403912f080e7Smrj 			dma->dp_pgmap[trim->tr_last_pidx].pm_cbaddr =
404012f080e7Smrj 			    trim->tr_last_cbaddr;
404112f080e7Smrj #if !defined(__amd64)
404212f080e7Smrj 			dma->dp_pgmap[trim->tr_last_pidx].pm_kaddr =
404312f080e7Smrj 			    trim->tr_last_kaddr;
404412f080e7Smrj #endif
404512f080e7Smrj 		}
404612f080e7Smrj 	}
404712f080e7Smrj 
404812f080e7Smrj 	/*
404912f080e7Smrj 	 * setup the cookie pointer to the first cookie in the window. setup
405012f080e7Smrj 	 * our return values, then increment the cookie since we return the
405112f080e7Smrj 	 * first cookie on the stack.
405212f080e7Smrj 	 */
405312f080e7Smrj 	hp->dmai_cookie = window->wd_first_cookie;
405412f080e7Smrj 	*offp = window->wd_offset;
405512f080e7Smrj 	*lenp = window->wd_size;
405612f080e7Smrj 	*ccountp = window->wd_cookie_cnt;
405712f080e7Smrj 	*cookiep = hp->dmai_cookie[0];
405812f080e7Smrj 	hp->dmai_cookie++;
405912f080e7Smrj 
406012f080e7Smrj #if !defined(__amd64)
406112f080e7Smrj 	/* re-map copybuf if required for this window */
406212f080e7Smrj 	if (dma->dp_cb_remaping) {
406312f080e7Smrj 		/*
406412f080e7Smrj 		 * calculate the page index into the buffer where this
406512f080e7Smrj 		 * window starts.
406612f080e7Smrj 		 */
406712f080e7Smrj 		pidx = (sinfo->si_buf_offset + window->wd_offset) >>
406812f080e7Smrj 		    MMU_PAGESHIFT;
406912f080e7Smrj 		ASSERT(pidx < sinfo->si_max_pages);
407012f080e7Smrj 
407112f080e7Smrj 		/*
407212f080e7Smrj 		 * the first page can get unmapped if it's shared with the
407312f080e7Smrj 		 * previous window. Even if the rest of this window is already
407412f080e7Smrj 		 * mapped in, we need to still check this one.
407512f080e7Smrj 		 */
407612f080e7Smrj 		pmap = &dma->dp_pgmap[pidx];
407712f080e7Smrj 		if ((pmap->pm_uses_copybuf) && (pmap->pm_mapped == B_FALSE)) {
407812f080e7Smrj 			if (pmap->pm_pp != NULL) {
407912f080e7Smrj 				pmap->pm_mapped = B_TRUE;
408012f080e7Smrj 				i86_pp_map(pmap->pm_pp, pmap->pm_kaddr);
408112f080e7Smrj 			} else if (pmap->pm_vaddr != NULL) {
408212f080e7Smrj 				pmap->pm_mapped = B_TRUE;
408312f080e7Smrj 				i86_va_map(pmap->pm_vaddr, sinfo->si_asp,
408412f080e7Smrj 				    pmap->pm_kaddr);
408512f080e7Smrj 			}
408612f080e7Smrj 		}
408712f080e7Smrj 		pidx++;
408812f080e7Smrj 
408912f080e7Smrj 		/* map in the rest of the pages if required */
409012f080e7Smrj 		if (window->wd_remap_copybuf) {
409112f080e7Smrj 			window->wd_remap_copybuf = B_FALSE;
409212f080e7Smrj 
409312f080e7Smrj 			/* figure out many pages this window takes up */
409412f080e7Smrj 			poff = (sinfo->si_buf_offset + window->wd_offset) &
409512f080e7Smrj 			    MMU_PAGEOFFSET;
409612f080e7Smrj 			pcnt = mmu_btopr(window->wd_size + poff);
409712f080e7Smrj 			ASSERT(((pidx - 1) + pcnt) <= sinfo->si_max_pages);
409812f080e7Smrj 
409912f080e7Smrj 			/* map pages which require it */
410012f080e7Smrj 			for (i = 1; i < pcnt; i++) {
410112f080e7Smrj 				pmap = &dma->dp_pgmap[pidx];
410212f080e7Smrj 				if (pmap->pm_uses_copybuf) {
410312f080e7Smrj 					ASSERT(pmap->pm_mapped == B_FALSE);
410412f080e7Smrj 					if (pmap->pm_pp != NULL) {
410512f080e7Smrj 						pmap->pm_mapped = B_TRUE;
410612f080e7Smrj 						i86_pp_map(pmap->pm_pp,
410712f080e7Smrj 						    pmap->pm_kaddr);
410812f080e7Smrj 					} else if (pmap->pm_vaddr != NULL) {
410912f080e7Smrj 						pmap->pm_mapped = B_TRUE;
411012f080e7Smrj 						i86_va_map(pmap->pm_vaddr,
411112f080e7Smrj 						    sinfo->si_asp,
411212f080e7Smrj 						    pmap->pm_kaddr);
411312f080e7Smrj 					}
411412f080e7Smrj 				}
411512f080e7Smrj 				pidx++;
411612f080e7Smrj 			}
411712f080e7Smrj 		}
411812f080e7Smrj 	}
411912f080e7Smrj #endif
412012f080e7Smrj 
412112f080e7Smrj 	/* if the new window uses the copy buffer, sync it for the device */
412212f080e7Smrj 	if ((window->wd_dosync) && (hp->dmai_rflags & DDI_DMA_WRITE)) {
412312f080e7Smrj 		(void) rootnex_dma_sync(dip, rdip, handle, 0, 0,
412412f080e7Smrj 		    DDI_DMA_SYNC_FORDEV);
412512f080e7Smrj 	}
412612f080e7Smrj 
412712f080e7Smrj 	return (DDI_SUCCESS);
412812f080e7Smrj }
412912f080e7Smrj 
413012f080e7Smrj 
413112f080e7Smrj 
413212f080e7Smrj /*
413312f080e7Smrj  * ************************
413412f080e7Smrj  *  obsoleted dma routines
413512f080e7Smrj  * ************************
413612f080e7Smrj  */
413712f080e7Smrj 
413812f080e7Smrj /*
413912f080e7Smrj  * rootnex_dma_map()
414012f080e7Smrj  *    called from ddi_dma_setup()
414112f080e7Smrj  */
414212f080e7Smrj /* ARGSUSED */
414312f080e7Smrj static int
414412f080e7Smrj rootnex_dma_map(dev_info_t *dip, dev_info_t *rdip, struct ddi_dma_req *dmareq,
414512f080e7Smrj     ddi_dma_handle_t *handlep)
414612f080e7Smrj {
414712f080e7Smrj #if defined(__amd64)
414812f080e7Smrj 	/*
414912f080e7Smrj 	 * this interface is not supported in 64-bit x86 kernel. See comment in
415012f080e7Smrj 	 * rootnex_dma_mctl()
415112f080e7Smrj 	 */
415212f080e7Smrj 	return (DDI_DMA_NORESOURCES);
415312f080e7Smrj 
415412f080e7Smrj #else /* 32-bit x86 kernel */
415512f080e7Smrj 	ddi_dma_handle_t *lhandlep;
415612f080e7Smrj 	ddi_dma_handle_t lhandle;
415712f080e7Smrj 	ddi_dma_cookie_t cookie;
415812f080e7Smrj 	ddi_dma_attr_t dma_attr;
415912f080e7Smrj 	ddi_dma_lim_t *dma_lim;
416012f080e7Smrj 	uint_t ccnt;
416112f080e7Smrj 	int e;
416212f080e7Smrj 
416312f080e7Smrj 
416412f080e7Smrj 	/*
416512f080e7Smrj 	 * if the driver is just testing to see if it's possible to do the bind,
416612f080e7Smrj 	 * we'll use local state. Otherwise, use the handle pointer passed in.
416712f080e7Smrj 	 */
416812f080e7Smrj 	if (handlep == NULL) {
416912f080e7Smrj 		lhandlep = &lhandle;
417012f080e7Smrj 	} else {
417112f080e7Smrj 		lhandlep = handlep;
417212f080e7Smrj 	}
417312f080e7Smrj 
417412f080e7Smrj 	/* convert the limit structure to a dma_attr one */
417512f080e7Smrj 	dma_lim = dmareq->dmar_limits;
417612f080e7Smrj 	dma_attr.dma_attr_version = DMA_ATTR_V0;
417712f080e7Smrj 	dma_attr.dma_attr_addr_lo = dma_lim->dlim_addr_lo;
417812f080e7Smrj 	dma_attr.dma_attr_addr_hi = dma_lim->dlim_addr_hi;
417912f080e7Smrj 	dma_attr.dma_attr_minxfer = dma_lim->dlim_minxfer;
418012f080e7Smrj 	dma_attr.dma_attr_seg = dma_lim->dlim_adreg_max;
418112f080e7Smrj 	dma_attr.dma_attr_count_max = dma_lim->dlim_ctreg_max;
418212f080e7Smrj 	dma_attr.dma_attr_granular = dma_lim->dlim_granular;
418312f080e7Smrj 	dma_attr.dma_attr_sgllen = dma_lim->dlim_sgllen;
418412f080e7Smrj 	dma_attr.dma_attr_maxxfer = dma_lim->dlim_reqsize;
418512f080e7Smrj 	dma_attr.dma_attr_burstsizes = dma_lim->dlim_burstsizes;
418612f080e7Smrj 	dma_attr.dma_attr_align = MMU_PAGESIZE;
418712f080e7Smrj 	dma_attr.dma_attr_flags = 0;
418812f080e7Smrj 
418912f080e7Smrj 	e = rootnex_dma_allochdl(dip, rdip, &dma_attr, dmareq->dmar_fp,
419012f080e7Smrj 	    dmareq->dmar_arg, lhandlep);
419112f080e7Smrj 	if (e != DDI_SUCCESS) {
419212f080e7Smrj 		return (e);
419312f080e7Smrj 	}
419412f080e7Smrj 
419512f080e7Smrj 	e = rootnex_dma_bindhdl(dip, rdip, *lhandlep, dmareq, &cookie, &ccnt);
419612f080e7Smrj 	if ((e != DDI_DMA_MAPPED) && (e != DDI_DMA_PARTIAL_MAP)) {
419712f080e7Smrj 		(void) rootnex_dma_freehdl(dip, rdip, *lhandlep);
419812f080e7Smrj 		return (e);
419912f080e7Smrj 	}
420012f080e7Smrj 
420112f080e7Smrj 	/*
420212f080e7Smrj 	 * if the driver is just testing to see if it's possible to do the bind,
420312f080e7Smrj 	 * free up the local state and return the result.
420412f080e7Smrj 	 */
420512f080e7Smrj 	if (handlep == NULL) {
420612f080e7Smrj 		(void) rootnex_dma_unbindhdl(dip, rdip, *lhandlep);
420712f080e7Smrj 		(void) rootnex_dma_freehdl(dip, rdip, *lhandlep);
420812f080e7Smrj 		if (e == DDI_DMA_MAPPED) {
420912f080e7Smrj 			return (DDI_DMA_MAPOK);
421012f080e7Smrj 		} else {
421112f080e7Smrj 			return (DDI_DMA_NOMAPPING);
421212f080e7Smrj 		}
421312f080e7Smrj 	}
421412f080e7Smrj 
421512f080e7Smrj 	return (e);
421612f080e7Smrj #endif /* defined(__amd64) */
421712f080e7Smrj }
421812f080e7Smrj 
421912f080e7Smrj 
422012f080e7Smrj /*
422112f080e7Smrj  * rootnex_dma_mctl()
422212f080e7Smrj  *
422312f080e7Smrj  */
422412f080e7Smrj /* ARGSUSED */
422512f080e7Smrj static int
422612f080e7Smrj rootnex_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
422712f080e7Smrj     enum ddi_dma_ctlops request, off_t *offp, size_t *lenp, caddr_t *objpp,
422812f080e7Smrj     uint_t cache_flags)
422912f080e7Smrj {
423012f080e7Smrj #if defined(__amd64)
423112f080e7Smrj 	/*
423212f080e7Smrj 	 * DDI_DMA_SMEM_ALLOC & DDI_DMA_IOPB_ALLOC we're changed to have a
423312f080e7Smrj 	 * common implementation in genunix, so they no longer have x86
423412f080e7Smrj 	 * specific functionality which called into dma_ctl.
423512f080e7Smrj 	 *
423612f080e7Smrj 	 * The rest of the obsoleted interfaces were never supported in the
423712f080e7Smrj 	 * 64-bit x86 kernel. For s10, the obsoleted DDI_DMA_SEGTOC interface
423812f080e7Smrj 	 * was not ported to the x86 64-bit kernel do to serious x86 rootnex
423912f080e7Smrj 	 * implementation issues.
424012f080e7Smrj 	 *
424112f080e7Smrj 	 * If you can't use DDI_DMA_SEGTOC; DDI_DMA_NEXTSEG, DDI_DMA_FREE, and
424212f080e7Smrj 	 * DDI_DMA_NEXTWIN are useless since you can get to the cookie, so we
424312f080e7Smrj 	 * reflect that now too...
424412f080e7Smrj 	 *
424512f080e7Smrj 	 * Even though we fixed the pointer problem in DDI_DMA_SEGTOC, we are
424612f080e7Smrj 	 * not going to put this functionality into the 64-bit x86 kernel now.
424712f080e7Smrj 	 * It wasn't ported to the 64-bit kernel for s10, no reason to change
424812f080e7Smrj 	 * that in a future release.
424912f080e7Smrj 	 */
425012f080e7Smrj 	return (DDI_FAILURE);
425112f080e7Smrj 
425212f080e7Smrj #else /* 32-bit x86 kernel */
425312f080e7Smrj 	ddi_dma_cookie_t lcookie;
425412f080e7Smrj 	ddi_dma_cookie_t *cookie;
425512f080e7Smrj 	rootnex_window_t *window;
425612f080e7Smrj 	ddi_dma_impl_t *hp;
425712f080e7Smrj 	rootnex_dma_t *dma;
425812f080e7Smrj 	uint_t nwin;
425912f080e7Smrj 	uint_t ccnt;
426012f080e7Smrj 	size_t len;
426112f080e7Smrj 	off_t off;
426212f080e7Smrj 	int e;
426312f080e7Smrj 
426412f080e7Smrj 
426512f080e7Smrj 	/*
426612f080e7Smrj 	 * DDI_DMA_SEGTOC, DDI_DMA_NEXTSEG, and DDI_DMA_NEXTWIN are a little
426712f080e7Smrj 	 * hacky since were optimizing for the current interfaces and so we can
426812f080e7Smrj 	 * cleanup the mess in genunix. Hopefully we will remove the this
426912f080e7Smrj 	 * obsoleted routines someday soon.
427012f080e7Smrj 	 */
427112f080e7Smrj 
427212f080e7Smrj 	switch (request) {
427312f080e7Smrj 
427412f080e7Smrj 	case DDI_DMA_SEGTOC: /* ddi_dma_segtocookie() */
427512f080e7Smrj 		hp = (ddi_dma_impl_t *)handle;
427612f080e7Smrj 		cookie = (ddi_dma_cookie_t *)objpp;
427712f080e7Smrj 
427812f080e7Smrj 		/*
427912f080e7Smrj 		 * convert segment to cookie. We don't distinguish between the
428012f080e7Smrj 		 * two :-)
428112f080e7Smrj 		 */
428212f080e7Smrj 		*cookie = *hp->dmai_cookie;
428312f080e7Smrj 		*lenp = cookie->dmac_size;
428412f080e7Smrj 		*offp = cookie->dmac_type & ~ROOTNEX_USES_COPYBUF;
428512f080e7Smrj 		return (DDI_SUCCESS);
428612f080e7Smrj 
428712f080e7Smrj 	case DDI_DMA_NEXTSEG: /* ddi_dma_nextseg() */
428812f080e7Smrj 		hp = (ddi_dma_impl_t *)handle;
428912f080e7Smrj 		dma = (rootnex_dma_t *)hp->dmai_private;
429012f080e7Smrj 
429112f080e7Smrj 		if ((*lenp != NULL) && ((uintptr_t)*lenp != (uintptr_t)hp)) {
429212f080e7Smrj 			return (DDI_DMA_STALE);
429312f080e7Smrj 		}
429412f080e7Smrj 
429512f080e7Smrj 		/* handle the case where we don't have any windows */
429612f080e7Smrj 		if (dma->dp_window == NULL) {
429712f080e7Smrj 			/*
429812f080e7Smrj 			 * if seg == NULL, and we don't have any windows,
429912f080e7Smrj 			 * return the first cookie in the sgl.
430012f080e7Smrj 			 */
430112f080e7Smrj 			if (*lenp == NULL) {
430212f080e7Smrj 				dma->dp_current_cookie = 0;
430312f080e7Smrj 				hp->dmai_cookie = dma->dp_cookies;
430412f080e7Smrj 				*objpp = (caddr_t)handle;
430512f080e7Smrj 				return (DDI_SUCCESS);
430612f080e7Smrj 
430712f080e7Smrj 			/* if we have more cookies, go to the next cookie */
430812f080e7Smrj 			} else {
430912f080e7Smrj 				if ((dma->dp_current_cookie + 1) >=
431012f080e7Smrj 				    dma->dp_sglinfo.si_sgl_size) {
431112f080e7Smrj 					return (DDI_DMA_DONE);
431212f080e7Smrj 				}
431312f080e7Smrj 				dma->dp_current_cookie++;
431412f080e7Smrj 				hp->dmai_cookie++;
431512f080e7Smrj 				return (DDI_SUCCESS);
431612f080e7Smrj 			}
431712f080e7Smrj 		}
431812f080e7Smrj 
431912f080e7Smrj 		/* We have one or more windows */
432012f080e7Smrj 		window = &dma->dp_window[dma->dp_current_win];
432112f080e7Smrj 
432212f080e7Smrj 		/*
432312f080e7Smrj 		 * if seg == NULL, return the first cookie in the current
432412f080e7Smrj 		 * window
432512f080e7Smrj 		 */
432612f080e7Smrj 		if (*lenp == NULL) {
432712f080e7Smrj 			dma->dp_current_cookie = 0;
4328cf4e9a1dSmrj 			hp->dmai_cookie = window->wd_first_cookie;
432912f080e7Smrj 
433012f080e7Smrj 		/*
433112f080e7Smrj 		 * go to the next cookie in the window then see if we done with
433212f080e7Smrj 		 * this window.
433312f080e7Smrj 		 */
433412f080e7Smrj 		} else {
433512f080e7Smrj 			if ((dma->dp_current_cookie + 1) >=
433612f080e7Smrj 			    window->wd_cookie_cnt) {
433712f080e7Smrj 				return (DDI_DMA_DONE);
433812f080e7Smrj 			}
433912f080e7Smrj 			dma->dp_current_cookie++;
434012f080e7Smrj 			hp->dmai_cookie++;
434112f080e7Smrj 		}
434212f080e7Smrj 		*objpp = (caddr_t)handle;
434312f080e7Smrj 		return (DDI_SUCCESS);
434412f080e7Smrj 
434512f080e7Smrj 	case DDI_DMA_NEXTWIN: /* ddi_dma_nextwin() */
434612f080e7Smrj 		hp = (ddi_dma_impl_t *)handle;
434712f080e7Smrj 		dma = (rootnex_dma_t *)hp->dmai_private;
434812f080e7Smrj 
434912f080e7Smrj 		if ((*offp != NULL) && ((uintptr_t)*offp != (uintptr_t)hp)) {
435012f080e7Smrj 			return (DDI_DMA_STALE);
435112f080e7Smrj 		}
435212f080e7Smrj 
435312f080e7Smrj 		/* if win == NULL, return the first window in the bind */
435412f080e7Smrj 		if (*offp == NULL) {
435512f080e7Smrj 			nwin = 0;
435612f080e7Smrj 
435712f080e7Smrj 		/*
435812f080e7Smrj 		 * else, go to the next window then see if we're done with all
435912f080e7Smrj 		 * the windows.
436012f080e7Smrj 		 */
436112f080e7Smrj 		} else {
436212f080e7Smrj 			nwin = dma->dp_current_win + 1;
436312f080e7Smrj 			if (nwin >= hp->dmai_nwin) {
436412f080e7Smrj 				return (DDI_DMA_DONE);
436512f080e7Smrj 			}
436612f080e7Smrj 		}
436712f080e7Smrj 
436812f080e7Smrj 		/* switch to the next window */
436912f080e7Smrj 		e = rootnex_dma_win(dip, rdip, handle, nwin, &off, &len,
437012f080e7Smrj 		    &lcookie, &ccnt);
437112f080e7Smrj 		ASSERT(e == DDI_SUCCESS);
437212f080e7Smrj 		if (e != DDI_SUCCESS) {
437312f080e7Smrj 			return (DDI_DMA_STALE);
437412f080e7Smrj 		}
437512f080e7Smrj 
437612f080e7Smrj 		/* reset the cookie back to the first cookie in the window */
437712f080e7Smrj 		if (dma->dp_window != NULL) {
437812f080e7Smrj 			window = &dma->dp_window[dma->dp_current_win];
437912f080e7Smrj 			hp->dmai_cookie = window->wd_first_cookie;
438012f080e7Smrj 		} else {
438112f080e7Smrj 			hp->dmai_cookie = dma->dp_cookies;
438212f080e7Smrj 		}
438312f080e7Smrj 
438412f080e7Smrj 		*objpp = (caddr_t)handle;
438512f080e7Smrj 		return (DDI_SUCCESS);
438612f080e7Smrj 
438712f080e7Smrj 	case DDI_DMA_FREE: /* ddi_dma_free() */
438812f080e7Smrj 		(void) rootnex_dma_unbindhdl(dip, rdip, handle);
438912f080e7Smrj 		(void) rootnex_dma_freehdl(dip, rdip, handle);
439012f080e7Smrj 		if (rootnex_state->r_dvma_call_list_id) {
439112f080e7Smrj 			ddi_run_callback(&rootnex_state->r_dvma_call_list_id);
439212f080e7Smrj 		}
439312f080e7Smrj 		return (DDI_SUCCESS);
439412f080e7Smrj 
439512f080e7Smrj 	case DDI_DMA_IOPB_ALLOC:	/* get contiguous DMA-able memory */
439612f080e7Smrj 	case DDI_DMA_SMEM_ALLOC:	/* get contiguous DMA-able memory */
439712f080e7Smrj 		/* should never get here, handled in genunix */
439812f080e7Smrj 		ASSERT(0);
439912f080e7Smrj 		return (DDI_FAILURE);
440012f080e7Smrj 
440112f080e7Smrj 	case DDI_DMA_KVADDR:
440212f080e7Smrj 	case DDI_DMA_GETERR:
440312f080e7Smrj 	case DDI_DMA_COFF:
440412f080e7Smrj 		return (DDI_FAILURE);
440512f080e7Smrj 	}
440612f080e7Smrj 
440712f080e7Smrj 	return (DDI_FAILURE);
440812f080e7Smrj #endif /* defined(__amd64) */
44097c478bd9Sstevel@tonic-gate }
4410