17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 500d0963fSdilpreet * Common Development and Distribution License (the "License"). 600d0963fSdilpreet * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22d21b39ddSmrj * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate /* 2712f080e7Smrj * x86 root nexus driver 287c478bd9Sstevel@tonic-gate */ 297c478bd9Sstevel@tonic-gate 307c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h> 317c478bd9Sstevel@tonic-gate #include <sys/conf.h> 327c478bd9Sstevel@tonic-gate #include <sys/autoconf.h> 337c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h> 347c478bd9Sstevel@tonic-gate #include <sys/debug.h> 357c478bd9Sstevel@tonic-gate #include <sys/psw.h> 367c478bd9Sstevel@tonic-gate #include <sys/ddidmareq.h> 377c478bd9Sstevel@tonic-gate #include <sys/promif.h> 387c478bd9Sstevel@tonic-gate #include <sys/devops.h> 397c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 407c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 417c478bd9Sstevel@tonic-gate #include <vm/seg.h> 427c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 437c478bd9Sstevel@tonic-gate #include <vm/seg_dev.h> 447c478bd9Sstevel@tonic-gate #include <sys/vmem.h> 457c478bd9Sstevel@tonic-gate #include <sys/mman.h> 467c478bd9Sstevel@tonic-gate #include <vm/hat.h> 477c478bd9Sstevel@tonic-gate #include <vm/as.h> 487c478bd9Sstevel@tonic-gate #include <vm/page.h> 497c478bd9Sstevel@tonic-gate #include <sys/avintr.h> 507c478bd9Sstevel@tonic-gate #include <sys/errno.h> 517c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 527c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 537c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 547c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 557a364d25Sschwartz #include <sys/mach_intr.h> 567c478bd9Sstevel@tonic-gate #include <sys/psm.h> 577c478bd9Sstevel@tonic-gate #include <sys/ontrap.h> 5812f080e7Smrj #include <sys/atomic.h> 5912f080e7Smrj #include <sys/sdt.h> 6012f080e7Smrj #include <sys/rootnex.h> 6112f080e7Smrj #include <vm/hat_i86.h> 6200d0963fSdilpreet #include <sys/ddifm.h> 6336945f79Smrj #include <sys/ddi_isa.h> 647c478bd9Sstevel@tonic-gate 65843e1988Sjohnlev #ifdef __xpv 66843e1988Sjohnlev #include <sys/bootinfo.h> 67843e1988Sjohnlev #include <sys/hypervisor.h> 68843e1988Sjohnlev #include <sys/bootconf.h> 69843e1988Sjohnlev #include <vm/kboot_mmu.h> 70843e1988Sjohnlev #endif 71843e1988Sjohnlev 72*86c1f4dcSVikram Hegde #include <sys/intel_iommu.h> 73*86c1f4dcSVikram Hegde 74*86c1f4dcSVikram Hegde /* 75*86c1f4dcSVikram Hegde * add to support dmar fault interrupt, will change soon 76*86c1f4dcSVikram Hegde */ 77*86c1f4dcSVikram Hegde char _depends_on[] = "mach/pcplusmp"; 78*86c1f4dcSVikram Hegde 7912f080e7Smrj /* 8012f080e7Smrj * enable/disable extra checking of function parameters. Useful for debugging 8112f080e7Smrj * drivers. 8212f080e7Smrj */ 8312f080e7Smrj #ifdef DEBUG 8412f080e7Smrj int rootnex_alloc_check_parms = 1; 8512f080e7Smrj int rootnex_bind_check_parms = 1; 8612f080e7Smrj int rootnex_bind_check_inuse = 1; 8712f080e7Smrj int rootnex_unbind_verify_buffer = 0; 8812f080e7Smrj int rootnex_sync_check_parms = 1; 8912f080e7Smrj #else 9012f080e7Smrj int rootnex_alloc_check_parms = 0; 9112f080e7Smrj int rootnex_bind_check_parms = 0; 9212f080e7Smrj int rootnex_bind_check_inuse = 0; 9312f080e7Smrj int rootnex_unbind_verify_buffer = 0; 9412f080e7Smrj int rootnex_sync_check_parms = 0; 9512f080e7Smrj #endif 967c478bd9Sstevel@tonic-gate 977aec1d6eScindi /* Master Abort and Target Abort panic flag */ 987aec1d6eScindi int rootnex_fm_ma_ta_panic_flag = 0; 997aec1d6eScindi 10012f080e7Smrj /* Semi-temporary patchables to phase in bug fixes, test drivers, etc. */ 1017c478bd9Sstevel@tonic-gate int rootnex_bind_fail = 1; 1027c478bd9Sstevel@tonic-gate int rootnex_bind_warn = 1; 1037c478bd9Sstevel@tonic-gate uint8_t *rootnex_warn_list; 1047c478bd9Sstevel@tonic-gate /* bitmasks for rootnex_warn_list. Up to 8 different warnings with uint8_t */ 1057c478bd9Sstevel@tonic-gate #define ROOTNEX_BIND_WARNING (0x1 << 0) 1067c478bd9Sstevel@tonic-gate 1077c478bd9Sstevel@tonic-gate /* 10812f080e7Smrj * revert back to old broken behavior of always sync'ing entire copy buffer. 10912f080e7Smrj * This is useful if be have a buggy driver which doesn't correctly pass in 11012f080e7Smrj * the offset and size into ddi_dma_sync(). 1117c478bd9Sstevel@tonic-gate */ 11212f080e7Smrj int rootnex_sync_ignore_params = 0; 1137c478bd9Sstevel@tonic-gate 1147c478bd9Sstevel@tonic-gate /* 11512f080e7Smrj * For the 64-bit kernel, pre-alloc enough cookies for a 256K buffer plus 1 11612f080e7Smrj * page for alignment. For the 32-bit kernel, pre-alloc enough cookies for a 11712f080e7Smrj * 64K buffer plus 1 page for alignment (we have less kernel space in a 32-bit 11812f080e7Smrj * kernel). Allocate enough windows to handle a 256K buffer w/ at least 65 11912f080e7Smrj * sgllen DMA engine, and enough copybuf buffer state pages to handle 2 pages 12012f080e7Smrj * (< 8K). We will still need to allocate the copy buffer during bind though 12112f080e7Smrj * (if we need one). These can only be modified in /etc/system before rootnex 12212f080e7Smrj * attach. 1237c478bd9Sstevel@tonic-gate */ 12412f080e7Smrj #if defined(__amd64) 12512f080e7Smrj int rootnex_prealloc_cookies = 65; 12612f080e7Smrj int rootnex_prealloc_windows = 4; 12712f080e7Smrj int rootnex_prealloc_copybuf = 2; 12812f080e7Smrj #else 12912f080e7Smrj int rootnex_prealloc_cookies = 33; 13012f080e7Smrj int rootnex_prealloc_windows = 4; 13112f080e7Smrj int rootnex_prealloc_copybuf = 2; 13212f080e7Smrj #endif 1337c478bd9Sstevel@tonic-gate 13412f080e7Smrj /* driver global state */ 13512f080e7Smrj static rootnex_state_t *rootnex_state; 13612f080e7Smrj 13712f080e7Smrj /* shortcut to rootnex counters */ 13812f080e7Smrj static uint64_t *rootnex_cnt; 1397c478bd9Sstevel@tonic-gate 1407c478bd9Sstevel@tonic-gate /* 14112f080e7Smrj * XXX - does x86 even need these or are they left over from the SPARC days? 1427c478bd9Sstevel@tonic-gate */ 14312f080e7Smrj /* statically defined integer/boolean properties for the root node */ 14412f080e7Smrj static rootnex_intprop_t rootnex_intprp[] = { 14512f080e7Smrj { "PAGESIZE", PAGESIZE }, 14612f080e7Smrj { "MMU_PAGESIZE", MMU_PAGESIZE }, 14712f080e7Smrj { "MMU_PAGEOFFSET", MMU_PAGEOFFSET }, 14812f080e7Smrj { DDI_RELATIVE_ADDRESSING, 1 }, 14912f080e7Smrj }; 15012f080e7Smrj #define NROOT_INTPROPS (sizeof (rootnex_intprp) / sizeof (rootnex_intprop_t)) 1517c478bd9Sstevel@tonic-gate 152843e1988Sjohnlev #ifdef __xpv 153843e1988Sjohnlev typedef maddr_t rootnex_addr_t; 154843e1988Sjohnlev #define ROOTNEX_PADDR_TO_RBASE(xinfo, pa) \ 155843e1988Sjohnlev (DOMAIN_IS_INITDOMAIN(xinfo) ? pa_to_ma(pa) : (pa)) 156843e1988Sjohnlev #else 157843e1988Sjohnlev typedef paddr_t rootnex_addr_t; 158843e1988Sjohnlev #endif 159843e1988Sjohnlev 1607c478bd9Sstevel@tonic-gate 16112f080e7Smrj static struct cb_ops rootnex_cb_ops = { 16212f080e7Smrj nodev, /* open */ 16312f080e7Smrj nodev, /* close */ 16412f080e7Smrj nodev, /* strategy */ 16512f080e7Smrj nodev, /* print */ 16612f080e7Smrj nodev, /* dump */ 16712f080e7Smrj nodev, /* read */ 16812f080e7Smrj nodev, /* write */ 16912f080e7Smrj nodev, /* ioctl */ 17012f080e7Smrj nodev, /* devmap */ 17112f080e7Smrj nodev, /* mmap */ 17212f080e7Smrj nodev, /* segmap */ 17312f080e7Smrj nochpoll, /* chpoll */ 17412f080e7Smrj ddi_prop_op, /* cb_prop_op */ 17512f080e7Smrj NULL, /* struct streamtab */ 17612f080e7Smrj D_NEW | D_MP | D_HOTPLUG, /* compatibility flags */ 17712f080e7Smrj CB_REV, /* Rev */ 17812f080e7Smrj nodev, /* cb_aread */ 17912f080e7Smrj nodev /* cb_awrite */ 18012f080e7Smrj }; 1817c478bd9Sstevel@tonic-gate 18212f080e7Smrj static int rootnex_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 1837c478bd9Sstevel@tonic-gate off_t offset, off_t len, caddr_t *vaddrp); 18412f080e7Smrj static int rootnex_map_fault(dev_info_t *dip, dev_info_t *rdip, 1857c478bd9Sstevel@tonic-gate struct hat *hat, struct seg *seg, caddr_t addr, 1867c478bd9Sstevel@tonic-gate struct devpage *dp, pfn_t pfn, uint_t prot, uint_t lock); 18712f080e7Smrj static int rootnex_dma_map(dev_info_t *dip, dev_info_t *rdip, 1887c478bd9Sstevel@tonic-gate struct ddi_dma_req *dmareq, ddi_dma_handle_t *handlep); 18912f080e7Smrj static int rootnex_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 19012f080e7Smrj ddi_dma_attr_t *attr, int (*waitfp)(caddr_t), caddr_t arg, 19112f080e7Smrj ddi_dma_handle_t *handlep); 19212f080e7Smrj static int rootnex_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, 19312f080e7Smrj ddi_dma_handle_t handle); 19412f080e7Smrj static int rootnex_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 19512f080e7Smrj ddi_dma_handle_t handle, struct ddi_dma_req *dmareq, 19612f080e7Smrj ddi_dma_cookie_t *cookiep, uint_t *ccountp); 19712f080e7Smrj static int rootnex_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 19812f080e7Smrj ddi_dma_handle_t handle); 19912f080e7Smrj static int rootnex_dma_sync(dev_info_t *dip, dev_info_t *rdip, 20012f080e7Smrj ddi_dma_handle_t handle, off_t off, size_t len, uint_t cache_flags); 20112f080e7Smrj static int rootnex_dma_win(dev_info_t *dip, dev_info_t *rdip, 20212f080e7Smrj ddi_dma_handle_t handle, uint_t win, off_t *offp, size_t *lenp, 20312f080e7Smrj ddi_dma_cookie_t *cookiep, uint_t *ccountp); 20412f080e7Smrj static int rootnex_dma_mctl(dev_info_t *dip, dev_info_t *rdip, 2057c478bd9Sstevel@tonic-gate ddi_dma_handle_t handle, enum ddi_dma_ctlops request, 2067c478bd9Sstevel@tonic-gate off_t *offp, size_t *lenp, caddr_t *objp, uint_t cache_flags); 20712f080e7Smrj static int rootnex_ctlops(dev_info_t *dip, dev_info_t *rdip, 20812f080e7Smrj ddi_ctl_enum_t ctlop, void *arg, void *result); 20900d0963fSdilpreet static int rootnex_fm_init(dev_info_t *dip, dev_info_t *tdip, int tcap, 21000d0963fSdilpreet ddi_iblock_cookie_t *ibc); 21112f080e7Smrj static int rootnex_intr_ops(dev_info_t *pdip, dev_info_t *rdip, 21212f080e7Smrj ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 2137c478bd9Sstevel@tonic-gate 2147c478bd9Sstevel@tonic-gate 2157c478bd9Sstevel@tonic-gate static struct bus_ops rootnex_bus_ops = { 2167c478bd9Sstevel@tonic-gate BUSO_REV, 2177c478bd9Sstevel@tonic-gate rootnex_map, 2187c478bd9Sstevel@tonic-gate NULL, 2197c478bd9Sstevel@tonic-gate NULL, 2207c478bd9Sstevel@tonic-gate NULL, 2217c478bd9Sstevel@tonic-gate rootnex_map_fault, 2227c478bd9Sstevel@tonic-gate rootnex_dma_map, 2237c478bd9Sstevel@tonic-gate rootnex_dma_allochdl, 2247c478bd9Sstevel@tonic-gate rootnex_dma_freehdl, 2257c478bd9Sstevel@tonic-gate rootnex_dma_bindhdl, 2267c478bd9Sstevel@tonic-gate rootnex_dma_unbindhdl, 22712f080e7Smrj rootnex_dma_sync, 2287c478bd9Sstevel@tonic-gate rootnex_dma_win, 2297c478bd9Sstevel@tonic-gate rootnex_dma_mctl, 2307c478bd9Sstevel@tonic-gate rootnex_ctlops, 2317c478bd9Sstevel@tonic-gate ddi_bus_prop_op, 2327c478bd9Sstevel@tonic-gate i_ddi_rootnex_get_eventcookie, 2337c478bd9Sstevel@tonic-gate i_ddi_rootnex_add_eventcall, 2347c478bd9Sstevel@tonic-gate i_ddi_rootnex_remove_eventcall, 2357c478bd9Sstevel@tonic-gate i_ddi_rootnex_post_event, 2367c478bd9Sstevel@tonic-gate 0, /* bus_intr_ctl */ 2377c478bd9Sstevel@tonic-gate 0, /* bus_config */ 2387c478bd9Sstevel@tonic-gate 0, /* bus_unconfig */ 23900d0963fSdilpreet rootnex_fm_init, /* bus_fm_init */ 2407c478bd9Sstevel@tonic-gate NULL, /* bus_fm_fini */ 2417c478bd9Sstevel@tonic-gate NULL, /* bus_fm_access_enter */ 2427c478bd9Sstevel@tonic-gate NULL, /* bus_fm_access_exit */ 2437c478bd9Sstevel@tonic-gate NULL, /* bus_powr */ 2447c478bd9Sstevel@tonic-gate rootnex_intr_ops /* bus_intr_op */ 2457c478bd9Sstevel@tonic-gate }; 2467c478bd9Sstevel@tonic-gate 24712f080e7Smrj static int rootnex_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 24812f080e7Smrj static int rootnex_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 2497c478bd9Sstevel@tonic-gate 2507c478bd9Sstevel@tonic-gate static struct dev_ops rootnex_ops = { 2517c478bd9Sstevel@tonic-gate DEVO_REV, 25212f080e7Smrj 0, 25312f080e7Smrj ddi_no_info, 2547c478bd9Sstevel@tonic-gate nulldev, 25512f080e7Smrj nulldev, 2567c478bd9Sstevel@tonic-gate rootnex_attach, 25712f080e7Smrj rootnex_detach, 25812f080e7Smrj nulldev, 25912f080e7Smrj &rootnex_cb_ops, 2607c478bd9Sstevel@tonic-gate &rootnex_bus_ops 2617c478bd9Sstevel@tonic-gate }; 2627c478bd9Sstevel@tonic-gate 26312f080e7Smrj static struct modldrv rootnex_modldrv = { 26412f080e7Smrj &mod_driverops, 265613b2871SRichard Bean "i86pc root nexus", 26612f080e7Smrj &rootnex_ops 2677c478bd9Sstevel@tonic-gate }; 2687c478bd9Sstevel@tonic-gate 26912f080e7Smrj static struct modlinkage rootnex_modlinkage = { 27012f080e7Smrj MODREV_1, 27112f080e7Smrj (void *)&rootnex_modldrv, 27212f080e7Smrj NULL 2737c478bd9Sstevel@tonic-gate }; 2747c478bd9Sstevel@tonic-gate 2757c478bd9Sstevel@tonic-gate 27612f080e7Smrj /* 27712f080e7Smrj * extern hacks 27812f080e7Smrj */ 27912f080e7Smrj extern struct seg_ops segdev_ops; 28012f080e7Smrj extern int ignore_hardware_nodes; /* force flag from ddi_impl.c */ 28112f080e7Smrj #ifdef DDI_MAP_DEBUG 28212f080e7Smrj extern int ddi_map_debug_flag; 28312f080e7Smrj #define ddi_map_debug if (ddi_map_debug_flag) prom_printf 28412f080e7Smrj #endif 28512f080e7Smrj extern void i86_pp_map(page_t *pp, caddr_t kaddr); 28612f080e7Smrj extern void i86_va_map(caddr_t vaddr, struct as *asp, caddr_t kaddr); 28712f080e7Smrj extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, 28812f080e7Smrj psm_intr_op_t, int *); 28912f080e7Smrj extern int impl_ddi_sunbus_initchild(dev_info_t *dip); 29012f080e7Smrj extern void impl_ddi_sunbus_removechild(dev_info_t *dip); 29136945f79Smrj 29212f080e7Smrj /* 29312f080e7Smrj * Use device arena to use for device control register mappings. 29412f080e7Smrj * Various kernel memory walkers (debugger, dtrace) need to know 29512f080e7Smrj * to avoid this address range to prevent undesired device activity. 29612f080e7Smrj */ 29712f080e7Smrj extern void *device_arena_alloc(size_t size, int vm_flag); 29812f080e7Smrj extern void device_arena_free(void * vaddr, size_t size); 29912f080e7Smrj 30012f080e7Smrj 30112f080e7Smrj /* 30212f080e7Smrj * Internal functions 30312f080e7Smrj */ 30412f080e7Smrj static int rootnex_dma_init(); 30512f080e7Smrj static void rootnex_add_props(dev_info_t *); 30612f080e7Smrj static int rootnex_ctl_reportdev(dev_info_t *dip); 30712f080e7Smrj static struct intrspec *rootnex_get_ispec(dev_info_t *rdip, int inum); 30812f080e7Smrj static int rootnex_map_regspec(ddi_map_req_t *mp, caddr_t *vaddrp); 30912f080e7Smrj static int rootnex_unmap_regspec(ddi_map_req_t *mp, caddr_t *vaddrp); 31012f080e7Smrj static int rootnex_map_handle(ddi_map_req_t *mp); 31112f080e7Smrj static void rootnex_clean_dmahdl(ddi_dma_impl_t *hp); 31212f080e7Smrj static int rootnex_valid_alloc_parms(ddi_dma_attr_t *attr, uint_t maxsegsize); 31312f080e7Smrj static int rootnex_valid_bind_parms(ddi_dma_req_t *dmareq, 31412f080e7Smrj ddi_dma_attr_t *attr); 31512f080e7Smrj static void rootnex_get_sgl(ddi_dma_obj_t *dmar_object, ddi_dma_cookie_t *sgl, 31612f080e7Smrj rootnex_sglinfo_t *sglinfo); 31712f080e7Smrj static int rootnex_bind_slowpath(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq, 31812f080e7Smrj rootnex_dma_t *dma, ddi_dma_attr_t *attr, int kmflag); 31912f080e7Smrj static int rootnex_setup_copybuf(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq, 32012f080e7Smrj rootnex_dma_t *dma, ddi_dma_attr_t *attr); 32112f080e7Smrj static void rootnex_teardown_copybuf(rootnex_dma_t *dma); 32212f080e7Smrj static int rootnex_setup_windows(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 32312f080e7Smrj ddi_dma_attr_t *attr, int kmflag); 32412f080e7Smrj static void rootnex_teardown_windows(rootnex_dma_t *dma); 32512f080e7Smrj static void rootnex_init_win(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 32612f080e7Smrj rootnex_window_t *window, ddi_dma_cookie_t *cookie, off_t cur_offset); 32712f080e7Smrj static void rootnex_setup_cookie(ddi_dma_obj_t *dmar_object, 32812f080e7Smrj rootnex_dma_t *dma, ddi_dma_cookie_t *cookie, off_t cur_offset, 32912f080e7Smrj size_t *copybuf_used, page_t **cur_pp); 33012f080e7Smrj static int rootnex_sgllen_window_boundary(ddi_dma_impl_t *hp, 33112f080e7Smrj rootnex_dma_t *dma, rootnex_window_t **windowp, ddi_dma_cookie_t *cookie, 33212f080e7Smrj ddi_dma_attr_t *attr, off_t cur_offset); 33312f080e7Smrj static int rootnex_copybuf_window_boundary(ddi_dma_impl_t *hp, 33412f080e7Smrj rootnex_dma_t *dma, rootnex_window_t **windowp, 33512f080e7Smrj ddi_dma_cookie_t *cookie, off_t cur_offset, size_t *copybuf_used); 33612f080e7Smrj static int rootnex_maxxfer_window_boundary(ddi_dma_impl_t *hp, 33712f080e7Smrj rootnex_dma_t *dma, rootnex_window_t **windowp, ddi_dma_cookie_t *cookie); 33812f080e7Smrj static int rootnex_valid_sync_parms(ddi_dma_impl_t *hp, rootnex_window_t *win, 33912f080e7Smrj off_t offset, size_t size, uint_t cache_flags); 34012f080e7Smrj static int rootnex_verify_buffer(rootnex_dma_t *dma); 34100d0963fSdilpreet static int rootnex_dma_check(dev_info_t *dip, const void *handle, 34200d0963fSdilpreet const void *comp_addr, const void *not_used); 34312f080e7Smrj 34412f080e7Smrj /* 34512f080e7Smrj * _init() 34612f080e7Smrj * 34712f080e7Smrj */ 3487c478bd9Sstevel@tonic-gate int 3497c478bd9Sstevel@tonic-gate _init(void) 3507c478bd9Sstevel@tonic-gate { 35112f080e7Smrj 35212f080e7Smrj rootnex_state = NULL; 35312f080e7Smrj return (mod_install(&rootnex_modlinkage)); 3547c478bd9Sstevel@tonic-gate } 3557c478bd9Sstevel@tonic-gate 35612f080e7Smrj 35712f080e7Smrj /* 35812f080e7Smrj * _info() 35912f080e7Smrj * 36012f080e7Smrj */ 36112f080e7Smrj int 36212f080e7Smrj _info(struct modinfo *modinfop) 36312f080e7Smrj { 36412f080e7Smrj return (mod_info(&rootnex_modlinkage, modinfop)); 36512f080e7Smrj } 36612f080e7Smrj 36712f080e7Smrj 36812f080e7Smrj /* 36912f080e7Smrj * _fini() 37012f080e7Smrj * 37112f080e7Smrj */ 3727c478bd9Sstevel@tonic-gate int 3737c478bd9Sstevel@tonic-gate _fini(void) 3747c478bd9Sstevel@tonic-gate { 3757c478bd9Sstevel@tonic-gate return (EBUSY); 3767c478bd9Sstevel@tonic-gate } 3777c478bd9Sstevel@tonic-gate 37812f080e7Smrj 37912f080e7Smrj /* 38012f080e7Smrj * rootnex_attach() 38112f080e7Smrj * 38212f080e7Smrj */ 38312f080e7Smrj static int 38412f080e7Smrj rootnex_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 3857c478bd9Sstevel@tonic-gate { 3867aec1d6eScindi int fmcap; 38712f080e7Smrj int e; 38812f080e7Smrj 38912f080e7Smrj switch (cmd) { 39012f080e7Smrj case DDI_ATTACH: 39112f080e7Smrj break; 39212f080e7Smrj case DDI_RESUME: 39312f080e7Smrj return (DDI_SUCCESS); 39412f080e7Smrj default: 39512f080e7Smrj return (DDI_FAILURE); 3967c478bd9Sstevel@tonic-gate } 3977c478bd9Sstevel@tonic-gate 3987c478bd9Sstevel@tonic-gate /* 39912f080e7Smrj * We should only have one instance of rootnex. Save it away since we 40012f080e7Smrj * don't have an easy way to get it back later. 4017c478bd9Sstevel@tonic-gate */ 40212f080e7Smrj ASSERT(rootnex_state == NULL); 40312f080e7Smrj rootnex_state = kmem_zalloc(sizeof (rootnex_state_t), KM_SLEEP); 4047c478bd9Sstevel@tonic-gate 40512f080e7Smrj rootnex_state->r_dip = dip; 4067aec1d6eScindi rootnex_state->r_err_ibc = (ddi_iblock_cookie_t)ipltospl(15); 40712f080e7Smrj rootnex_state->r_reserved_msg_printed = B_FALSE; 40812f080e7Smrj rootnex_cnt = &rootnex_state->r_counters[0]; 409*86c1f4dcSVikram Hegde rootnex_state->r_intel_iommu_enabled = B_FALSE; 4107c478bd9Sstevel@tonic-gate 4117aec1d6eScindi /* 4127aec1d6eScindi * Set minimum fm capability level for i86pc platforms and then 4137aec1d6eScindi * initialize error handling. Since we're the rootnex, we don't 4147aec1d6eScindi * care what's returned in the fmcap field. 4157aec1d6eScindi */ 41600d0963fSdilpreet ddi_system_fmcap = DDI_FM_EREPORT_CAPABLE | DDI_FM_ERRCB_CAPABLE | 41700d0963fSdilpreet DDI_FM_ACCCHK_CAPABLE | DDI_FM_DMACHK_CAPABLE; 4187aec1d6eScindi fmcap = ddi_system_fmcap; 4197aec1d6eScindi ddi_fm_init(dip, &fmcap, &rootnex_state->r_err_ibc); 4207aec1d6eScindi 42112f080e7Smrj /* initialize DMA related state */ 42212f080e7Smrj e = rootnex_dma_init(); 42312f080e7Smrj if (e != DDI_SUCCESS) { 42412f080e7Smrj kmem_free(rootnex_state, sizeof (rootnex_state_t)); 42512f080e7Smrj return (DDI_FAILURE); 42612f080e7Smrj } 42712f080e7Smrj 42812f080e7Smrj /* Add static root node properties */ 42912f080e7Smrj rootnex_add_props(dip); 43012f080e7Smrj 43112f080e7Smrj /* since we can't call ddi_report_dev() */ 43212f080e7Smrj cmn_err(CE_CONT, "?root nexus = %s\n", ddi_get_name(dip)); 43312f080e7Smrj 43412f080e7Smrj /* Initialize rootnex event handle */ 43512f080e7Smrj i_ddi_rootnex_init_events(dip); 43612f080e7Smrj 437*86c1f4dcSVikram Hegde #if defined(__amd64) 438*86c1f4dcSVikram Hegde /* probe intel iommu */ 439*86c1f4dcSVikram Hegde intel_iommu_probe_and_parse(); 440*86c1f4dcSVikram Hegde 441*86c1f4dcSVikram Hegde /* attach the iommu nodes */ 442*86c1f4dcSVikram Hegde if (intel_iommu_support) { 443*86c1f4dcSVikram Hegde if (intel_iommu_attach_dmar_nodes() == DDI_SUCCESS) { 444*86c1f4dcSVikram Hegde rootnex_state->r_intel_iommu_enabled = B_TRUE; 445*86c1f4dcSVikram Hegde } else { 446*86c1f4dcSVikram Hegde intel_iommu_release_dmar_info(); 447*86c1f4dcSVikram Hegde } 448*86c1f4dcSVikram Hegde } 449*86c1f4dcSVikram Hegde #endif 450*86c1f4dcSVikram Hegde 45112f080e7Smrj return (DDI_SUCCESS); 45212f080e7Smrj } 45312f080e7Smrj 45412f080e7Smrj 45512f080e7Smrj /* 45612f080e7Smrj * rootnex_detach() 45712f080e7Smrj * 45812f080e7Smrj */ 4597c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 4607c478bd9Sstevel@tonic-gate static int 46112f080e7Smrj rootnex_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 4627c478bd9Sstevel@tonic-gate { 46312f080e7Smrj switch (cmd) { 46412f080e7Smrj case DDI_SUSPEND: 46512f080e7Smrj break; 46612f080e7Smrj default: 46712f080e7Smrj return (DDI_FAILURE); 46812f080e7Smrj } 4697c478bd9Sstevel@tonic-gate 47012f080e7Smrj return (DDI_SUCCESS); 47112f080e7Smrj } 4727c478bd9Sstevel@tonic-gate 4737c478bd9Sstevel@tonic-gate 47412f080e7Smrj /* 47512f080e7Smrj * rootnex_dma_init() 47612f080e7Smrj * 47712f080e7Smrj */ 47812f080e7Smrj /*ARGSUSED*/ 47912f080e7Smrj static int 48012f080e7Smrj rootnex_dma_init() 48112f080e7Smrj { 48212f080e7Smrj size_t bufsize; 48312f080e7Smrj 48412f080e7Smrj 48512f080e7Smrj /* 48612f080e7Smrj * size of our cookie/window/copybuf state needed in dma bind that we 48712f080e7Smrj * pre-alloc in dma_alloc_handle 48812f080e7Smrj */ 48912f080e7Smrj rootnex_state->r_prealloc_cookies = rootnex_prealloc_cookies; 49012f080e7Smrj rootnex_state->r_prealloc_size = 49112f080e7Smrj (rootnex_state->r_prealloc_cookies * sizeof (ddi_dma_cookie_t)) + 49212f080e7Smrj (rootnex_prealloc_windows * sizeof (rootnex_window_t)) + 49312f080e7Smrj (rootnex_prealloc_copybuf * sizeof (rootnex_pgmap_t)); 49412f080e7Smrj 49512f080e7Smrj /* 49612f080e7Smrj * setup DDI DMA handle kmem cache, align each handle on 64 bytes, 49712f080e7Smrj * allocate 16 extra bytes for struct pointer alignment 49812f080e7Smrj * (p->dmai_private & dma->dp_prealloc_buffer) 49912f080e7Smrj */ 50012f080e7Smrj bufsize = sizeof (ddi_dma_impl_t) + sizeof (rootnex_dma_t) + 50112f080e7Smrj rootnex_state->r_prealloc_size + 0x10; 50212f080e7Smrj rootnex_state->r_dmahdl_cache = kmem_cache_create("rootnex_dmahdl", 50312f080e7Smrj bufsize, 64, NULL, NULL, NULL, NULL, NULL, 0); 50412f080e7Smrj if (rootnex_state->r_dmahdl_cache == NULL) { 50512f080e7Smrj return (DDI_FAILURE); 50612f080e7Smrj } 5077c478bd9Sstevel@tonic-gate 5087c478bd9Sstevel@tonic-gate /* 5097c478bd9Sstevel@tonic-gate * allocate array to track which major numbers we have printed warnings 5107c478bd9Sstevel@tonic-gate * for. 5117c478bd9Sstevel@tonic-gate */ 5127c478bd9Sstevel@tonic-gate rootnex_warn_list = kmem_zalloc(devcnt * sizeof (*rootnex_warn_list), 5137c478bd9Sstevel@tonic-gate KM_SLEEP); 5147c478bd9Sstevel@tonic-gate 5157c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5167c478bd9Sstevel@tonic-gate } 5177c478bd9Sstevel@tonic-gate 5187c478bd9Sstevel@tonic-gate 5197c478bd9Sstevel@tonic-gate /* 52012f080e7Smrj * rootnex_add_props() 52112f080e7Smrj * 5227c478bd9Sstevel@tonic-gate */ 5237c478bd9Sstevel@tonic-gate static void 52412f080e7Smrj rootnex_add_props(dev_info_t *dip) 5257c478bd9Sstevel@tonic-gate { 52612f080e7Smrj rootnex_intprop_t *rpp; 5277c478bd9Sstevel@tonic-gate int i; 5287c478bd9Sstevel@tonic-gate 52912f080e7Smrj /* Add static integer/boolean properties to the root node */ 53012f080e7Smrj rpp = rootnex_intprp; 53112f080e7Smrj for (i = 0; i < NROOT_INTPROPS; i++) { 53212f080e7Smrj (void) e_ddi_prop_update_int(DDI_DEV_T_NONE, dip, 53312f080e7Smrj rpp[i].prop_name, rpp[i].prop_value); 53412f080e7Smrj } 5357c478bd9Sstevel@tonic-gate } 5367c478bd9Sstevel@tonic-gate 53712f080e7Smrj 53812f080e7Smrj 5397c478bd9Sstevel@tonic-gate /* 54012f080e7Smrj * ************************* 54112f080e7Smrj * ctlops related routines 54212f080e7Smrj * ************************* 54312f080e7Smrj */ 54412f080e7Smrj 54512f080e7Smrj /* 54612f080e7Smrj * rootnex_ctlops() 5477c478bd9Sstevel@tonic-gate * 5487c478bd9Sstevel@tonic-gate */ 549a195726fSgovinda /*ARGSUSED*/ 5507c478bd9Sstevel@tonic-gate static int 55112f080e7Smrj rootnex_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop, 55212f080e7Smrj void *arg, void *result) 5537c478bd9Sstevel@tonic-gate { 55412f080e7Smrj int n, *ptr; 55512f080e7Smrj struct ddi_parent_private_data *pdp; 5567c478bd9Sstevel@tonic-gate 55712f080e7Smrj switch (ctlop) { 55812f080e7Smrj case DDI_CTLOPS_DMAPMAPC: 5597c478bd9Sstevel@tonic-gate /* 56012f080e7Smrj * Return 'partial' to indicate that dma mapping 56112f080e7Smrj * has to be done in the main MMU. 5627c478bd9Sstevel@tonic-gate */ 56312f080e7Smrj return (DDI_DMA_PARTIAL); 5647c478bd9Sstevel@tonic-gate 56512f080e7Smrj case DDI_CTLOPS_BTOP: 5667c478bd9Sstevel@tonic-gate /* 56712f080e7Smrj * Convert byte count input to physical page units. 56812f080e7Smrj * (byte counts that are not a page-size multiple 56912f080e7Smrj * are rounded down) 5707c478bd9Sstevel@tonic-gate */ 57112f080e7Smrj *(ulong_t *)result = btop(*(ulong_t *)arg); 5727c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5737c478bd9Sstevel@tonic-gate 57412f080e7Smrj case DDI_CTLOPS_PTOB: 5757c478bd9Sstevel@tonic-gate /* 57612f080e7Smrj * Convert size in physical pages to bytes 5777c478bd9Sstevel@tonic-gate */ 57812f080e7Smrj *(ulong_t *)result = ptob(*(ulong_t *)arg); 5797c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5807c478bd9Sstevel@tonic-gate 58112f080e7Smrj case DDI_CTLOPS_BTOPR: 5827c478bd9Sstevel@tonic-gate /* 58312f080e7Smrj * Convert byte count input to physical page units 58412f080e7Smrj * (byte counts that are not a page-size multiple 58512f080e7Smrj * are rounded up) 5867c478bd9Sstevel@tonic-gate */ 58712f080e7Smrj *(ulong_t *)result = btopr(*(ulong_t *)arg); 58812f080e7Smrj return (DDI_SUCCESS); 58912f080e7Smrj 59012f080e7Smrj case DDI_CTLOPS_INITCHILD: 59112f080e7Smrj return (impl_ddi_sunbus_initchild(arg)); 59212f080e7Smrj 59312f080e7Smrj case DDI_CTLOPS_UNINITCHILD: 59412f080e7Smrj impl_ddi_sunbus_removechild(arg); 59512f080e7Smrj return (DDI_SUCCESS); 59612f080e7Smrj 59712f080e7Smrj case DDI_CTLOPS_REPORTDEV: 59812f080e7Smrj return (rootnex_ctl_reportdev(rdip)); 59912f080e7Smrj 60012f080e7Smrj case DDI_CTLOPS_IOMIN: 6017c478bd9Sstevel@tonic-gate /* 60212f080e7Smrj * Nothing to do here but reflect back.. 6037c478bd9Sstevel@tonic-gate */ 6047c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 6057c478bd9Sstevel@tonic-gate 60612f080e7Smrj case DDI_CTLOPS_REGSIZE: 60712f080e7Smrj case DDI_CTLOPS_NREGS: 60812f080e7Smrj break; 6097c478bd9Sstevel@tonic-gate 61012f080e7Smrj case DDI_CTLOPS_SIDDEV: 61112f080e7Smrj if (ndi_dev_is_prom_node(rdip)) 6127c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 61312f080e7Smrj if (ndi_dev_is_persistent_node(rdip)) 61412f080e7Smrj return (DDI_SUCCESS); 6157c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 6167c478bd9Sstevel@tonic-gate 61712f080e7Smrj case DDI_CTLOPS_POWER: 61812f080e7Smrj return ((*pm_platform_power)((power_req_t *)arg)); 61912f080e7Smrj 620a195726fSgovinda case DDI_CTLOPS_RESERVED0: /* Was DDI_CTLOPS_NINTRS, obsolete */ 62112f080e7Smrj case DDI_CTLOPS_RESERVED1: /* Was DDI_CTLOPS_POKE_INIT, obsolete */ 62212f080e7Smrj case DDI_CTLOPS_RESERVED2: /* Was DDI_CTLOPS_POKE_FLUSH, obsolete */ 62312f080e7Smrj case DDI_CTLOPS_RESERVED3: /* Was DDI_CTLOPS_POKE_FINI, obsolete */ 624a195726fSgovinda case DDI_CTLOPS_RESERVED4: /* Was DDI_CTLOPS_INTR_HILEVEL, obsolete */ 625a195726fSgovinda case DDI_CTLOPS_RESERVED5: /* Was DDI_CTLOPS_XLATE_INTRS, obsolete */ 62612f080e7Smrj if (!rootnex_state->r_reserved_msg_printed) { 62712f080e7Smrj rootnex_state->r_reserved_msg_printed = B_TRUE; 62812f080e7Smrj cmn_err(CE_WARN, "Failing ddi_ctlops call(s) for " 62912f080e7Smrj "1 or more reserved/obsolete operations."); 6307c478bd9Sstevel@tonic-gate } 63112f080e7Smrj return (DDI_FAILURE); 6327c478bd9Sstevel@tonic-gate 6337c478bd9Sstevel@tonic-gate default: 6347c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 6357c478bd9Sstevel@tonic-gate } 63612f080e7Smrj /* 63712f080e7Smrj * The rest are for "hardware" properties 63812f080e7Smrj */ 63912f080e7Smrj if ((pdp = ddi_get_parent_data(rdip)) == NULL) 64012f080e7Smrj return (DDI_FAILURE); 6417c478bd9Sstevel@tonic-gate 64212f080e7Smrj if (ctlop == DDI_CTLOPS_NREGS) { 64312f080e7Smrj ptr = (int *)result; 64412f080e7Smrj *ptr = pdp->par_nreg; 64512f080e7Smrj } else { 64612f080e7Smrj off_t *size = (off_t *)result; 6477c478bd9Sstevel@tonic-gate 64812f080e7Smrj ptr = (int *)arg; 64912f080e7Smrj n = *ptr; 65012f080e7Smrj if (n >= pdp->par_nreg) { 65112f080e7Smrj return (DDI_FAILURE); 65212f080e7Smrj } 65312f080e7Smrj *size = (off_t)pdp->par_reg[n].regspec_size; 65412f080e7Smrj } 6557c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 6567c478bd9Sstevel@tonic-gate } 6577c478bd9Sstevel@tonic-gate 65812f080e7Smrj 65912f080e7Smrj /* 66012f080e7Smrj * rootnex_ctl_reportdev() 66112f080e7Smrj * 66212f080e7Smrj */ 6637c478bd9Sstevel@tonic-gate static int 66412f080e7Smrj rootnex_ctl_reportdev(dev_info_t *dev) 66512f080e7Smrj { 66612f080e7Smrj int i, n, len, f_len = 0; 66712f080e7Smrj char *buf; 66812f080e7Smrj 66912f080e7Smrj buf = kmem_alloc(REPORTDEV_BUFSIZE, KM_SLEEP); 67012f080e7Smrj f_len += snprintf(buf, REPORTDEV_BUFSIZE, 67112f080e7Smrj "%s%d at root", ddi_driver_name(dev), ddi_get_instance(dev)); 67212f080e7Smrj len = strlen(buf); 67312f080e7Smrj 67412f080e7Smrj for (i = 0; i < sparc_pd_getnreg(dev); i++) { 67512f080e7Smrj 67612f080e7Smrj struct regspec *rp = sparc_pd_getreg(dev, i); 67712f080e7Smrj 67812f080e7Smrj if (i == 0) 67912f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 68012f080e7Smrj ": "); 68112f080e7Smrj else 68212f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 68312f080e7Smrj " and "); 68412f080e7Smrj len = strlen(buf); 68512f080e7Smrj 68612f080e7Smrj switch (rp->regspec_bustype) { 68712f080e7Smrj 68812f080e7Smrj case BTEISA: 68912f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 69012f080e7Smrj "%s 0x%x", DEVI_EISA_NEXNAME, rp->regspec_addr); 69112f080e7Smrj break; 69212f080e7Smrj 69312f080e7Smrj case BTISA: 69412f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 69512f080e7Smrj "%s 0x%x", DEVI_ISA_NEXNAME, rp->regspec_addr); 69612f080e7Smrj break; 69712f080e7Smrj 69812f080e7Smrj default: 69912f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 70012f080e7Smrj "space %x offset %x", 70112f080e7Smrj rp->regspec_bustype, rp->regspec_addr); 70212f080e7Smrj break; 70312f080e7Smrj } 70412f080e7Smrj len = strlen(buf); 70512f080e7Smrj } 70612f080e7Smrj for (i = 0, n = sparc_pd_getnintr(dev); i < n; i++) { 70712f080e7Smrj int pri; 70812f080e7Smrj 70912f080e7Smrj if (i != 0) { 71012f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 71112f080e7Smrj ","); 71212f080e7Smrj len = strlen(buf); 71312f080e7Smrj } 71412f080e7Smrj pri = INT_IPL(sparc_pd_getintr(dev, i)->intrspec_pri); 71512f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 71612f080e7Smrj " sparc ipl %d", pri); 71712f080e7Smrj len = strlen(buf); 71812f080e7Smrj } 71912f080e7Smrj #ifdef DEBUG 72012f080e7Smrj if (f_len + 1 >= REPORTDEV_BUFSIZE) { 72112f080e7Smrj cmn_err(CE_NOTE, "next message is truncated: " 72212f080e7Smrj "printed length 1024, real length %d", f_len); 72312f080e7Smrj } 72412f080e7Smrj #endif /* DEBUG */ 72512f080e7Smrj cmn_err(CE_CONT, "?%s\n", buf); 72612f080e7Smrj kmem_free(buf, REPORTDEV_BUFSIZE); 72712f080e7Smrj return (DDI_SUCCESS); 72812f080e7Smrj } 72912f080e7Smrj 73012f080e7Smrj 73112f080e7Smrj /* 73212f080e7Smrj * ****************** 73312f080e7Smrj * map related code 73412f080e7Smrj * ****************** 73512f080e7Smrj */ 73612f080e7Smrj 73712f080e7Smrj /* 73812f080e7Smrj * rootnex_map() 73912f080e7Smrj * 74012f080e7Smrj */ 74112f080e7Smrj static int 74212f080e7Smrj rootnex_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, off_t offset, 74312f080e7Smrj off_t len, caddr_t *vaddrp) 7447c478bd9Sstevel@tonic-gate { 7457c478bd9Sstevel@tonic-gate struct regspec *rp, tmp_reg; 7467c478bd9Sstevel@tonic-gate ddi_map_req_t mr = *mp; /* Get private copy of request */ 7477c478bd9Sstevel@tonic-gate int error; 7487c478bd9Sstevel@tonic-gate 7497c478bd9Sstevel@tonic-gate mp = &mr; 7507c478bd9Sstevel@tonic-gate 7517c478bd9Sstevel@tonic-gate switch (mp->map_op) { 7527c478bd9Sstevel@tonic-gate case DDI_MO_MAP_LOCKED: 7537c478bd9Sstevel@tonic-gate case DDI_MO_UNMAP: 7547c478bd9Sstevel@tonic-gate case DDI_MO_MAP_HANDLE: 7557c478bd9Sstevel@tonic-gate break; 7567c478bd9Sstevel@tonic-gate default: 7577c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 7587c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "rootnex_map: unimplemented map op %d.", 7597c478bd9Sstevel@tonic-gate mp->map_op); 7607c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 7617c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED); 7627c478bd9Sstevel@tonic-gate } 7637c478bd9Sstevel@tonic-gate 7647c478bd9Sstevel@tonic-gate if (mp->map_flags & DDI_MF_USER_MAPPING) { 7657c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 7667c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "rootnex_map: unimplemented map type: user."); 7677c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 7687c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED); 7697c478bd9Sstevel@tonic-gate } 7707c478bd9Sstevel@tonic-gate 7717c478bd9Sstevel@tonic-gate /* 7727c478bd9Sstevel@tonic-gate * First, if given an rnumber, convert it to a regspec... 7737c478bd9Sstevel@tonic-gate * (Presumably, this is on behalf of a child of the root node?) 7747c478bd9Sstevel@tonic-gate */ 7757c478bd9Sstevel@tonic-gate 7767c478bd9Sstevel@tonic-gate if (mp->map_type == DDI_MT_RNUMBER) { 7777c478bd9Sstevel@tonic-gate 7787c478bd9Sstevel@tonic-gate int rnumber = mp->map_obj.rnumber; 7797c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 7807c478bd9Sstevel@tonic-gate static char *out_of_range = 7817c478bd9Sstevel@tonic-gate "rootnex_map: Out of range rnumber <%d>, device <%s>"; 7827c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 7837c478bd9Sstevel@tonic-gate 7847c478bd9Sstevel@tonic-gate rp = i_ddi_rnumber_to_regspec(rdip, rnumber); 7857c478bd9Sstevel@tonic-gate if (rp == NULL) { 7867c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 7877c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, out_of_range, rnumber, 7887c478bd9Sstevel@tonic-gate ddi_get_name(rdip)); 7897c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 7907c478bd9Sstevel@tonic-gate return (DDI_ME_RNUMBER_RANGE); 7917c478bd9Sstevel@tonic-gate } 7927c478bd9Sstevel@tonic-gate 7937c478bd9Sstevel@tonic-gate /* 7947c478bd9Sstevel@tonic-gate * Convert the given ddi_map_req_t from rnumber to regspec... 7957c478bd9Sstevel@tonic-gate */ 7967c478bd9Sstevel@tonic-gate 7977c478bd9Sstevel@tonic-gate mp->map_type = DDI_MT_REGSPEC; 7987c478bd9Sstevel@tonic-gate mp->map_obj.rp = rp; 7997c478bd9Sstevel@tonic-gate } 8007c478bd9Sstevel@tonic-gate 8017c478bd9Sstevel@tonic-gate /* 8027c478bd9Sstevel@tonic-gate * Adjust offset and length correspnding to called values... 8037c478bd9Sstevel@tonic-gate * XXX: A non-zero length means override the one in the regspec 8047c478bd9Sstevel@tonic-gate * XXX: (regardless of what's in the parent's range?) 8057c478bd9Sstevel@tonic-gate */ 8067c478bd9Sstevel@tonic-gate 8077c478bd9Sstevel@tonic-gate tmp_reg = *(mp->map_obj.rp); /* Preserve underlying data */ 8087c478bd9Sstevel@tonic-gate rp = mp->map_obj.rp = &tmp_reg; /* Use tmp_reg in request */ 8097c478bd9Sstevel@tonic-gate 8107c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 811843e1988Sjohnlev cmn_err(CE_CONT, "rootnex: <%s,%s> <0x%x, 0x%x, 0x%d> offset %d len %d " 812843e1988Sjohnlev "handle 0x%x\n", ddi_get_name(dip), ddi_get_name(rdip), 813843e1988Sjohnlev rp->regspec_bustype, rp->regspec_addr, rp->regspec_size, offset, 814843e1988Sjohnlev len, mp->map_handlep); 8157c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 8167c478bd9Sstevel@tonic-gate 8177c478bd9Sstevel@tonic-gate /* 8187c478bd9Sstevel@tonic-gate * I/O or memory mapping: 8197c478bd9Sstevel@tonic-gate * 8207c478bd9Sstevel@tonic-gate * <bustype=0, addr=x, len=x>: memory 8217c478bd9Sstevel@tonic-gate * <bustype=1, addr=x, len=x>: i/o 8227c478bd9Sstevel@tonic-gate * <bustype>1, addr=0, len=x>: x86-compatibility i/o 8237c478bd9Sstevel@tonic-gate */ 8247c478bd9Sstevel@tonic-gate 8257c478bd9Sstevel@tonic-gate if (rp->regspec_bustype > 1 && rp->regspec_addr != 0) { 8267c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "<%s,%s> invalid register spec" 8277c478bd9Sstevel@tonic-gate " <0x%x, 0x%x, 0x%x>", ddi_get_name(dip), 8287c478bd9Sstevel@tonic-gate ddi_get_name(rdip), rp->regspec_bustype, 8297c478bd9Sstevel@tonic-gate rp->regspec_addr, rp->regspec_size); 8307c478bd9Sstevel@tonic-gate return (DDI_ME_INVAL); 8317c478bd9Sstevel@tonic-gate } 8327c478bd9Sstevel@tonic-gate 8337c478bd9Sstevel@tonic-gate if (rp->regspec_bustype > 1 && rp->regspec_addr == 0) { 8347c478bd9Sstevel@tonic-gate /* 8357c478bd9Sstevel@tonic-gate * compatibility i/o mapping 8367c478bd9Sstevel@tonic-gate */ 8377c478bd9Sstevel@tonic-gate rp->regspec_bustype += (uint_t)offset; 8387c478bd9Sstevel@tonic-gate } else { 8397c478bd9Sstevel@tonic-gate /* 8407c478bd9Sstevel@tonic-gate * Normal memory or i/o mapping 8417c478bd9Sstevel@tonic-gate */ 8427c478bd9Sstevel@tonic-gate rp->regspec_addr += (uint_t)offset; 8437c478bd9Sstevel@tonic-gate } 8447c478bd9Sstevel@tonic-gate 8457c478bd9Sstevel@tonic-gate if (len != 0) 8467c478bd9Sstevel@tonic-gate rp->regspec_size = (uint_t)len; 8477c478bd9Sstevel@tonic-gate 8487c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 849843e1988Sjohnlev cmn_err(CE_CONT, " <%s,%s> <0x%x, 0x%x, 0x%d> offset %d " 850843e1988Sjohnlev "len %d handle 0x%x\n", ddi_get_name(dip), ddi_get_name(rdip), 8517c478bd9Sstevel@tonic-gate rp->regspec_bustype, rp->regspec_addr, rp->regspec_size, 8527c478bd9Sstevel@tonic-gate offset, len, mp->map_handlep); 8537c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 8547c478bd9Sstevel@tonic-gate 8557c478bd9Sstevel@tonic-gate /* 8567c478bd9Sstevel@tonic-gate * Apply any parent ranges at this level, if applicable. 8577c478bd9Sstevel@tonic-gate * (This is where nexus specific regspec translation takes place. 8587c478bd9Sstevel@tonic-gate * Use of this function is implicit agreement that translation is 8597c478bd9Sstevel@tonic-gate * provided via ddi_apply_range.) 8607c478bd9Sstevel@tonic-gate */ 8617c478bd9Sstevel@tonic-gate 8627c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 8637c478bd9Sstevel@tonic-gate ddi_map_debug("applying range of parent <%s> to child <%s>...\n", 8647c478bd9Sstevel@tonic-gate ddi_get_name(dip), ddi_get_name(rdip)); 8657c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 8667c478bd9Sstevel@tonic-gate 8677c478bd9Sstevel@tonic-gate if ((error = i_ddi_apply_range(dip, rdip, mp->map_obj.rp)) != 0) 8687c478bd9Sstevel@tonic-gate return (error); 8697c478bd9Sstevel@tonic-gate 8707c478bd9Sstevel@tonic-gate switch (mp->map_op) { 8717c478bd9Sstevel@tonic-gate case DDI_MO_MAP_LOCKED: 8727c478bd9Sstevel@tonic-gate 8737c478bd9Sstevel@tonic-gate /* 8747c478bd9Sstevel@tonic-gate * Set up the locked down kernel mapping to the regspec... 8757c478bd9Sstevel@tonic-gate */ 8767c478bd9Sstevel@tonic-gate 8777c478bd9Sstevel@tonic-gate return (rootnex_map_regspec(mp, vaddrp)); 8787c478bd9Sstevel@tonic-gate 8797c478bd9Sstevel@tonic-gate case DDI_MO_UNMAP: 8807c478bd9Sstevel@tonic-gate 8817c478bd9Sstevel@tonic-gate /* 8827c478bd9Sstevel@tonic-gate * Release mapping... 8837c478bd9Sstevel@tonic-gate */ 8847c478bd9Sstevel@tonic-gate 8857c478bd9Sstevel@tonic-gate return (rootnex_unmap_regspec(mp, vaddrp)); 8867c478bd9Sstevel@tonic-gate 8877c478bd9Sstevel@tonic-gate case DDI_MO_MAP_HANDLE: 8887c478bd9Sstevel@tonic-gate 8897c478bd9Sstevel@tonic-gate return (rootnex_map_handle(mp)); 8907c478bd9Sstevel@tonic-gate 8917c478bd9Sstevel@tonic-gate default: 8927c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED); 8937c478bd9Sstevel@tonic-gate } 8947c478bd9Sstevel@tonic-gate } 8957c478bd9Sstevel@tonic-gate 8967c478bd9Sstevel@tonic-gate 8977c478bd9Sstevel@tonic-gate /* 89812f080e7Smrj * rootnex_map_fault() 8997c478bd9Sstevel@tonic-gate * 9007c478bd9Sstevel@tonic-gate * fault in mappings for requestors 9017c478bd9Sstevel@tonic-gate */ 9027c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 9037c478bd9Sstevel@tonic-gate static int 90412f080e7Smrj rootnex_map_fault(dev_info_t *dip, dev_info_t *rdip, struct hat *hat, 90512f080e7Smrj struct seg *seg, caddr_t addr, struct devpage *dp, pfn_t pfn, uint_t prot, 90612f080e7Smrj uint_t lock) 9077c478bd9Sstevel@tonic-gate { 9087c478bd9Sstevel@tonic-gate 9097c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 9107c478bd9Sstevel@tonic-gate ddi_map_debug("rootnex_map_fault: address <%x> pfn <%x>", addr, pfn); 9117c478bd9Sstevel@tonic-gate ddi_map_debug(" Seg <%s>\n", 9127c478bd9Sstevel@tonic-gate seg->s_ops == &segdev_ops ? "segdev" : 9137c478bd9Sstevel@tonic-gate seg == &kvseg ? "segkmem" : "NONE!"); 9147c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 9157c478bd9Sstevel@tonic-gate 9167c478bd9Sstevel@tonic-gate /* 9177c478bd9Sstevel@tonic-gate * This is all terribly broken, but it is a start 9187c478bd9Sstevel@tonic-gate * 9197c478bd9Sstevel@tonic-gate * XXX Note that this test means that segdev_ops 9207c478bd9Sstevel@tonic-gate * must be exported from seg_dev.c. 9217c478bd9Sstevel@tonic-gate * XXX What about devices with their own segment drivers? 9227c478bd9Sstevel@tonic-gate */ 9237c478bd9Sstevel@tonic-gate if (seg->s_ops == &segdev_ops) { 924843e1988Sjohnlev struct segdev_data *sdp = (struct segdev_data *)seg->s_data; 9257c478bd9Sstevel@tonic-gate 9267c478bd9Sstevel@tonic-gate if (hat == NULL) { 9277c478bd9Sstevel@tonic-gate /* 9287c478bd9Sstevel@tonic-gate * This is one plausible interpretation of 9297c478bd9Sstevel@tonic-gate * a null hat i.e. use the first hat on the 9307c478bd9Sstevel@tonic-gate * address space hat list which by convention is 9317c478bd9Sstevel@tonic-gate * the hat of the system MMU. At alternative 9327c478bd9Sstevel@tonic-gate * would be to panic .. this might well be better .. 9337c478bd9Sstevel@tonic-gate */ 9347c478bd9Sstevel@tonic-gate ASSERT(AS_READ_HELD(seg->s_as, &seg->s_as->a_lock)); 9357c478bd9Sstevel@tonic-gate hat = seg->s_as->a_hat; 9367c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "rootnex_map_fault: nil hat"); 9377c478bd9Sstevel@tonic-gate } 9387c478bd9Sstevel@tonic-gate hat_devload(hat, addr, MMU_PAGESIZE, pfn, prot | sdp->hat_attr, 9397c478bd9Sstevel@tonic-gate (lock ? HAT_LOAD_LOCK : HAT_LOAD)); 9407c478bd9Sstevel@tonic-gate } else if (seg == &kvseg && dp == NULL) { 9417c478bd9Sstevel@tonic-gate hat_devload(kas.a_hat, addr, MMU_PAGESIZE, pfn, prot, 9427c478bd9Sstevel@tonic-gate HAT_LOAD_LOCK); 9437c478bd9Sstevel@tonic-gate } else 9447c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 9457c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 9467c478bd9Sstevel@tonic-gate } 9477c478bd9Sstevel@tonic-gate 9487c478bd9Sstevel@tonic-gate 9497c478bd9Sstevel@tonic-gate /* 95012f080e7Smrj * rootnex_map_regspec() 95112f080e7Smrj * we don't support mapping of I/O cards above 4Gb 9527c478bd9Sstevel@tonic-gate */ 9537c478bd9Sstevel@tonic-gate static int 95412f080e7Smrj rootnex_map_regspec(ddi_map_req_t *mp, caddr_t *vaddrp) 9557c478bd9Sstevel@tonic-gate { 956843e1988Sjohnlev rootnex_addr_t rbase; 95712f080e7Smrj void *cvaddr; 95812f080e7Smrj uint_t npages, pgoffset; 95912f080e7Smrj struct regspec *rp; 96012f080e7Smrj ddi_acc_hdl_t *hp; 96112f080e7Smrj ddi_acc_impl_t *ap; 96212f080e7Smrj uint_t hat_acc_flags; 963843e1988Sjohnlev paddr_t pbase; 9647c478bd9Sstevel@tonic-gate 96512f080e7Smrj rp = mp->map_obj.rp; 96612f080e7Smrj hp = mp->map_handlep; 96712f080e7Smrj 96812f080e7Smrj #ifdef DDI_MAP_DEBUG 96912f080e7Smrj ddi_map_debug( 97012f080e7Smrj "rootnex_map_regspec: <0x%x 0x%x 0x%x> handle 0x%x\n", 97112f080e7Smrj rp->regspec_bustype, rp->regspec_addr, 97212f080e7Smrj rp->regspec_size, mp->map_handlep); 97312f080e7Smrj #endif /* DDI_MAP_DEBUG */ 9747c478bd9Sstevel@tonic-gate 9757c478bd9Sstevel@tonic-gate /* 97612f080e7Smrj * I/O or memory mapping 97712f080e7Smrj * 97812f080e7Smrj * <bustype=0, addr=x, len=x>: memory 97912f080e7Smrj * <bustype=1, addr=x, len=x>: i/o 98012f080e7Smrj * <bustype>1, addr=0, len=x>: x86-compatibility i/o 9817c478bd9Sstevel@tonic-gate */ 98212f080e7Smrj 98312f080e7Smrj if (rp->regspec_bustype > 1 && rp->regspec_addr != 0) { 98412f080e7Smrj cmn_err(CE_WARN, "rootnex: invalid register spec" 98512f080e7Smrj " <0x%x, 0x%x, 0x%x>", rp->regspec_bustype, 98612f080e7Smrj rp->regspec_addr, rp->regspec_size); 98712f080e7Smrj return (DDI_FAILURE); 9887c478bd9Sstevel@tonic-gate } 98912f080e7Smrj 99012f080e7Smrj if (rp->regspec_bustype != 0) { 9917c478bd9Sstevel@tonic-gate /* 99212f080e7Smrj * I/O space - needs a handle. 9937c478bd9Sstevel@tonic-gate */ 9947c478bd9Sstevel@tonic-gate if (hp == NULL) { 99512f080e7Smrj return (DDI_FAILURE); 9967c478bd9Sstevel@tonic-gate } 99712f080e7Smrj ap = (ddi_acc_impl_t *)hp->ah_platform_private; 99812f080e7Smrj ap->ahi_acc_attr |= DDI_ACCATTR_IO_SPACE; 99912f080e7Smrj impl_acc_hdl_init(hp); 10007c478bd9Sstevel@tonic-gate 100112f080e7Smrj if (mp->map_flags & DDI_MF_DEVICE_MAPPING) { 100212f080e7Smrj #ifdef DDI_MAP_DEBUG 1003843e1988Sjohnlev ddi_map_debug("rootnex_map_regspec: mmap() " 1004843e1988Sjohnlev "to I/O space is not supported.\n"); 100512f080e7Smrj #endif /* DDI_MAP_DEBUG */ 100612f080e7Smrj return (DDI_ME_INVAL); 10077c478bd9Sstevel@tonic-gate } else { 10087c478bd9Sstevel@tonic-gate /* 100912f080e7Smrj * 1275-compliant vs. compatibility i/o mapping 10107c478bd9Sstevel@tonic-gate */ 101112f080e7Smrj *vaddrp = 101212f080e7Smrj (rp->regspec_bustype > 1 && rp->regspec_addr == 0) ? 101312f080e7Smrj ((caddr_t)(uintptr_t)rp->regspec_bustype) : 101412f080e7Smrj ((caddr_t)(uintptr_t)rp->regspec_addr); 1015843e1988Sjohnlev #ifdef __xpv 1016843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1017843e1988Sjohnlev hp->ah_pfn = xen_assign_pfn( 1018843e1988Sjohnlev mmu_btop((ulong_t)rp->regspec_addr & 1019843e1988Sjohnlev MMU_PAGEMASK)); 1020843e1988Sjohnlev } else { 1021843e1988Sjohnlev hp->ah_pfn = mmu_btop( 1022843e1988Sjohnlev (ulong_t)rp->regspec_addr & MMU_PAGEMASK); 1023843e1988Sjohnlev } 1024843e1988Sjohnlev #else 102500d0963fSdilpreet hp->ah_pfn = mmu_btop((ulong_t)rp->regspec_addr & 1026843e1988Sjohnlev MMU_PAGEMASK); 1027843e1988Sjohnlev #endif 102800d0963fSdilpreet hp->ah_pnum = mmu_btopr(rp->regspec_size + 102900d0963fSdilpreet (ulong_t)rp->regspec_addr & MMU_PAGEOFFSET); 10307c478bd9Sstevel@tonic-gate } 10317c478bd9Sstevel@tonic-gate 103212f080e7Smrj #ifdef DDI_MAP_DEBUG 103312f080e7Smrj ddi_map_debug( 103412f080e7Smrj "rootnex_map_regspec: \"Mapping\" %d bytes I/O space at 0x%x\n", 103512f080e7Smrj rp->regspec_size, *vaddrp); 103612f080e7Smrj #endif /* DDI_MAP_DEBUG */ 103712f080e7Smrj return (DDI_SUCCESS); 10387c478bd9Sstevel@tonic-gate } 10397c478bd9Sstevel@tonic-gate 10407c478bd9Sstevel@tonic-gate /* 104112f080e7Smrj * Memory space 104212f080e7Smrj */ 104312f080e7Smrj 104412f080e7Smrj if (hp != NULL) { 104512f080e7Smrj /* 104612f080e7Smrj * hat layer ignores 104712f080e7Smrj * hp->ah_acc.devacc_attr_endian_flags. 104812f080e7Smrj */ 104912f080e7Smrj switch (hp->ah_acc.devacc_attr_dataorder) { 105012f080e7Smrj case DDI_STRICTORDER_ACC: 105112f080e7Smrj hat_acc_flags = HAT_STRICTORDER; 105212f080e7Smrj break; 105312f080e7Smrj case DDI_UNORDERED_OK_ACC: 105412f080e7Smrj hat_acc_flags = HAT_UNORDERED_OK; 105512f080e7Smrj break; 105612f080e7Smrj case DDI_MERGING_OK_ACC: 105712f080e7Smrj hat_acc_flags = HAT_MERGING_OK; 105812f080e7Smrj break; 105912f080e7Smrj case DDI_LOADCACHING_OK_ACC: 106012f080e7Smrj hat_acc_flags = HAT_LOADCACHING_OK; 106112f080e7Smrj break; 106212f080e7Smrj case DDI_STORECACHING_OK_ACC: 106312f080e7Smrj hat_acc_flags = HAT_STORECACHING_OK; 106412f080e7Smrj break; 106512f080e7Smrj } 106612f080e7Smrj ap = (ddi_acc_impl_t *)hp->ah_platform_private; 106712f080e7Smrj ap->ahi_acc_attr |= DDI_ACCATTR_CPU_VADDR; 106812f080e7Smrj impl_acc_hdl_init(hp); 106912f080e7Smrj hp->ah_hat_flags = hat_acc_flags; 107012f080e7Smrj } else { 107112f080e7Smrj hat_acc_flags = HAT_STRICTORDER; 107212f080e7Smrj } 107312f080e7Smrj 1074843e1988Sjohnlev rbase = (rootnex_addr_t)(rp->regspec_addr & MMU_PAGEMASK); 1075843e1988Sjohnlev #ifdef __xpv 1076843e1988Sjohnlev /* 1077843e1988Sjohnlev * If we're dom0, we're using a real device so we need to translate 1078843e1988Sjohnlev * the MA to a PA. 1079843e1988Sjohnlev */ 1080843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1081843e1988Sjohnlev pbase = pfn_to_pa(xen_assign_pfn(mmu_btop(rbase))); 1082843e1988Sjohnlev } else { 1083843e1988Sjohnlev pbase = rbase; 1084843e1988Sjohnlev } 1085843e1988Sjohnlev #else 1086843e1988Sjohnlev pbase = rbase; 1087843e1988Sjohnlev #endif 1088843e1988Sjohnlev pgoffset = (ulong_t)rp->regspec_addr & MMU_PAGEOFFSET; 108912f080e7Smrj 109012f080e7Smrj if (rp->regspec_size == 0) { 109112f080e7Smrj #ifdef DDI_MAP_DEBUG 109212f080e7Smrj ddi_map_debug("rootnex_map_regspec: zero regspec_size\n"); 109312f080e7Smrj #endif /* DDI_MAP_DEBUG */ 109412f080e7Smrj return (DDI_ME_INVAL); 109512f080e7Smrj } 109612f080e7Smrj 109712f080e7Smrj if (mp->map_flags & DDI_MF_DEVICE_MAPPING) { 1098843e1988Sjohnlev /* extra cast to make gcc happy */ 1099843e1988Sjohnlev *vaddrp = (caddr_t)((uintptr_t)mmu_btop(pbase)); 110012f080e7Smrj } else { 110112f080e7Smrj npages = mmu_btopr(rp->regspec_size + pgoffset); 110212f080e7Smrj 110312f080e7Smrj #ifdef DDI_MAP_DEBUG 1104843e1988Sjohnlev ddi_map_debug("rootnex_map_regspec: Mapping %d pages " 1105843e1988Sjohnlev "physical %llx", npages, pbase); 110612f080e7Smrj #endif /* DDI_MAP_DEBUG */ 110712f080e7Smrj 110812f080e7Smrj cvaddr = device_arena_alloc(ptob(npages), VM_NOSLEEP); 110912f080e7Smrj if (cvaddr == NULL) 111012f080e7Smrj return (DDI_ME_NORESOURCES); 111112f080e7Smrj 111212f080e7Smrj /* 111312f080e7Smrj * Now map in the pages we've allocated... 111412f080e7Smrj */ 1115843e1988Sjohnlev hat_devload(kas.a_hat, cvaddr, mmu_ptob(npages), 1116843e1988Sjohnlev mmu_btop(pbase), mp->map_prot | hat_acc_flags, 1117843e1988Sjohnlev HAT_LOAD_LOCK); 111812f080e7Smrj *vaddrp = (caddr_t)cvaddr + pgoffset; 111900d0963fSdilpreet 112000d0963fSdilpreet /* save away pfn and npages for FMA */ 112100d0963fSdilpreet hp = mp->map_handlep; 112200d0963fSdilpreet if (hp) { 1123843e1988Sjohnlev hp->ah_pfn = mmu_btop(pbase); 112400d0963fSdilpreet hp->ah_pnum = npages; 112500d0963fSdilpreet } 112612f080e7Smrj } 112712f080e7Smrj 112812f080e7Smrj #ifdef DDI_MAP_DEBUG 112912f080e7Smrj ddi_map_debug("at virtual 0x%x\n", *vaddrp); 113012f080e7Smrj #endif /* DDI_MAP_DEBUG */ 113112f080e7Smrj return (DDI_SUCCESS); 113212f080e7Smrj } 113312f080e7Smrj 113412f080e7Smrj 113512f080e7Smrj /* 113612f080e7Smrj * rootnex_unmap_regspec() 11377c478bd9Sstevel@tonic-gate * 11387c478bd9Sstevel@tonic-gate */ 11397c478bd9Sstevel@tonic-gate static int 114012f080e7Smrj rootnex_unmap_regspec(ddi_map_req_t *mp, caddr_t *vaddrp) 11417c478bd9Sstevel@tonic-gate { 114212f080e7Smrj caddr_t addr = (caddr_t)*vaddrp; 114312f080e7Smrj uint_t npages, pgoffset; 114412f080e7Smrj struct regspec *rp; 11457c478bd9Sstevel@tonic-gate 114612f080e7Smrj if (mp->map_flags & DDI_MF_DEVICE_MAPPING) 114712f080e7Smrj return (0); 11487c478bd9Sstevel@tonic-gate 114912f080e7Smrj rp = mp->map_obj.rp; 11507c478bd9Sstevel@tonic-gate 115112f080e7Smrj if (rp->regspec_size == 0) { 115212f080e7Smrj #ifdef DDI_MAP_DEBUG 115312f080e7Smrj ddi_map_debug("rootnex_unmap_regspec: zero regspec_size\n"); 115412f080e7Smrj #endif /* DDI_MAP_DEBUG */ 115512f080e7Smrj return (DDI_ME_INVAL); 11567c478bd9Sstevel@tonic-gate } 11577c478bd9Sstevel@tonic-gate 11587c478bd9Sstevel@tonic-gate /* 115912f080e7Smrj * I/O or memory mapping: 11607c478bd9Sstevel@tonic-gate * 116112f080e7Smrj * <bustype=0, addr=x, len=x>: memory 116212f080e7Smrj * <bustype=1, addr=x, len=x>: i/o 116312f080e7Smrj * <bustype>1, addr=0, len=x>: x86-compatibility i/o 11647c478bd9Sstevel@tonic-gate */ 116512f080e7Smrj if (rp->regspec_bustype != 0) { 11667c478bd9Sstevel@tonic-gate /* 116712f080e7Smrj * This is I/O space, which requires no particular 116812f080e7Smrj * processing on unmap since it isn't mapped in the 116912f080e7Smrj * first place. 11707c478bd9Sstevel@tonic-gate */ 11717c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 11727c478bd9Sstevel@tonic-gate } 11737c478bd9Sstevel@tonic-gate 11747c478bd9Sstevel@tonic-gate /* 117512f080e7Smrj * Memory space 11767c478bd9Sstevel@tonic-gate */ 117712f080e7Smrj pgoffset = (uintptr_t)addr & MMU_PAGEOFFSET; 117812f080e7Smrj npages = mmu_btopr(rp->regspec_size + pgoffset); 117912f080e7Smrj hat_unload(kas.a_hat, addr - pgoffset, ptob(npages), HAT_UNLOAD_UNLOCK); 118012f080e7Smrj device_arena_free(addr - pgoffset, ptob(npages)); 11817c478bd9Sstevel@tonic-gate 11827c478bd9Sstevel@tonic-gate /* 118312f080e7Smrj * Destroy the pointer - the mapping has logically gone 11847c478bd9Sstevel@tonic-gate */ 118512f080e7Smrj *vaddrp = NULL; 11867c478bd9Sstevel@tonic-gate 11877c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 11887c478bd9Sstevel@tonic-gate } 11897c478bd9Sstevel@tonic-gate 119012f080e7Smrj 119112f080e7Smrj /* 119212f080e7Smrj * rootnex_map_handle() 119312f080e7Smrj * 119412f080e7Smrj */ 11957c478bd9Sstevel@tonic-gate static int 119612f080e7Smrj rootnex_map_handle(ddi_map_req_t *mp) 11977c478bd9Sstevel@tonic-gate { 1198843e1988Sjohnlev rootnex_addr_t rbase; 119912f080e7Smrj ddi_acc_hdl_t *hp; 120012f080e7Smrj uint_t pgoffset; 120112f080e7Smrj struct regspec *rp; 1202843e1988Sjohnlev paddr_t pbase; 12037c478bd9Sstevel@tonic-gate 120412f080e7Smrj rp = mp->map_obj.rp; 12057c478bd9Sstevel@tonic-gate 120612f080e7Smrj #ifdef DDI_MAP_DEBUG 120712f080e7Smrj ddi_map_debug( 120812f080e7Smrj "rootnex_map_handle: <0x%x 0x%x 0x%x> handle 0x%x\n", 120912f080e7Smrj rp->regspec_bustype, rp->regspec_addr, 121012f080e7Smrj rp->regspec_size, mp->map_handlep); 121112f080e7Smrj #endif /* DDI_MAP_DEBUG */ 12127c478bd9Sstevel@tonic-gate 12137c478bd9Sstevel@tonic-gate /* 121412f080e7Smrj * I/O or memory mapping: 121512f080e7Smrj * 121612f080e7Smrj * <bustype=0, addr=x, len=x>: memory 121712f080e7Smrj * <bustype=1, addr=x, len=x>: i/o 121812f080e7Smrj * <bustype>1, addr=0, len=x>: x86-compatibility i/o 12197c478bd9Sstevel@tonic-gate */ 122012f080e7Smrj if (rp->regspec_bustype != 0) { 122112f080e7Smrj /* 122212f080e7Smrj * This refers to I/O space, and we don't support "mapping" 122312f080e7Smrj * I/O space to a user. 122412f080e7Smrj */ 12257c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 12267c478bd9Sstevel@tonic-gate } 12277c478bd9Sstevel@tonic-gate 12287c478bd9Sstevel@tonic-gate /* 122912f080e7Smrj * Set up the hat_flags for the mapping. 12307c478bd9Sstevel@tonic-gate */ 123112f080e7Smrj hp = mp->map_handlep; 12327c478bd9Sstevel@tonic-gate 123312f080e7Smrj switch (hp->ah_acc.devacc_attr_endian_flags) { 123412f080e7Smrj case DDI_NEVERSWAP_ACC: 123512f080e7Smrj hp->ah_hat_flags = HAT_NEVERSWAP | HAT_STRICTORDER; 12367c478bd9Sstevel@tonic-gate break; 123712f080e7Smrj case DDI_STRUCTURE_LE_ACC: 123812f080e7Smrj hp->ah_hat_flags = HAT_STRUCTURE_LE; 12397c478bd9Sstevel@tonic-gate break; 124012f080e7Smrj case DDI_STRUCTURE_BE_ACC: 12417c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 12427c478bd9Sstevel@tonic-gate default: 124312f080e7Smrj return (DDI_REGS_ACC_CONFLICT); 12447c478bd9Sstevel@tonic-gate } 12457c478bd9Sstevel@tonic-gate 124612f080e7Smrj switch (hp->ah_acc.devacc_attr_dataorder) { 124712f080e7Smrj case DDI_STRICTORDER_ACC: 12487c478bd9Sstevel@tonic-gate break; 124912f080e7Smrj case DDI_UNORDERED_OK_ACC: 125012f080e7Smrj hp->ah_hat_flags |= HAT_UNORDERED_OK; 12517c478bd9Sstevel@tonic-gate break; 125212f080e7Smrj case DDI_MERGING_OK_ACC: 125312f080e7Smrj hp->ah_hat_flags |= HAT_MERGING_OK; 12547c478bd9Sstevel@tonic-gate break; 125512f080e7Smrj case DDI_LOADCACHING_OK_ACC: 125612f080e7Smrj hp->ah_hat_flags |= HAT_LOADCACHING_OK; 125712f080e7Smrj break; 125812f080e7Smrj case DDI_STORECACHING_OK_ACC: 125912f080e7Smrj hp->ah_hat_flags |= HAT_STORECACHING_OK; 126012f080e7Smrj break; 12617c478bd9Sstevel@tonic-gate default: 12627c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 12637c478bd9Sstevel@tonic-gate } 12647c478bd9Sstevel@tonic-gate 1265843e1988Sjohnlev rbase = (rootnex_addr_t)rp->regspec_addr & 1266843e1988Sjohnlev (~(rootnex_addr_t)MMU_PAGEOFFSET); 1267843e1988Sjohnlev pgoffset = (ulong_t)rp->regspec_addr & MMU_PAGEOFFSET; 12687c478bd9Sstevel@tonic-gate 126912f080e7Smrj if (rp->regspec_size == 0) 127012f080e7Smrj return (DDI_ME_INVAL); 12717c478bd9Sstevel@tonic-gate 1272843e1988Sjohnlev #ifdef __xpv 1273843e1988Sjohnlev /* 1274843e1988Sjohnlev * If we're dom0, we're using a real device so we need to translate 1275843e1988Sjohnlev * the MA to a PA. 1276843e1988Sjohnlev */ 1277843e1988Sjohnlev if (DOMAIN_IS_INITDOMAIN(xen_info)) { 1278843e1988Sjohnlev pbase = pfn_to_pa(xen_assign_pfn(mmu_btop(rbase))) | 1279843e1988Sjohnlev (rbase & MMU_PAGEOFFSET); 1280843e1988Sjohnlev } else { 1281843e1988Sjohnlev pbase = rbase; 1282843e1988Sjohnlev } 1283843e1988Sjohnlev #else 1284843e1988Sjohnlev pbase = rbase; 1285843e1988Sjohnlev #endif 1286843e1988Sjohnlev 1287843e1988Sjohnlev hp->ah_pfn = mmu_btop(pbase); 128812f080e7Smrj hp->ah_pnum = mmu_btopr(rp->regspec_size + pgoffset); 12897c478bd9Sstevel@tonic-gate 12907c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12917c478bd9Sstevel@tonic-gate } 12927c478bd9Sstevel@tonic-gate 129312f080e7Smrj 129412f080e7Smrj 12957c478bd9Sstevel@tonic-gate /* 129612f080e7Smrj * ************************ 129712f080e7Smrj * interrupt related code 129812f080e7Smrj * ************************ 12997c478bd9Sstevel@tonic-gate */ 13007c478bd9Sstevel@tonic-gate 13017c478bd9Sstevel@tonic-gate /* 130212f080e7Smrj * rootnex_intr_ops() 13037c478bd9Sstevel@tonic-gate * bus_intr_op() function for interrupt support 13047c478bd9Sstevel@tonic-gate */ 13057c478bd9Sstevel@tonic-gate /* ARGSUSED */ 13067c478bd9Sstevel@tonic-gate static int 13077c478bd9Sstevel@tonic-gate rootnex_intr_ops(dev_info_t *pdip, dev_info_t *rdip, ddi_intr_op_t intr_op, 13087c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 13097c478bd9Sstevel@tonic-gate { 13107c478bd9Sstevel@tonic-gate struct intrspec *ispec; 13117c478bd9Sstevel@tonic-gate struct ddi_parent_private_data *pdp; 13127c478bd9Sstevel@tonic-gate 13137c478bd9Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, 13147c478bd9Sstevel@tonic-gate "rootnex_intr_ops: pdip = %p, rdip = %p, intr_op = %x, hdlp = %p\n", 13157c478bd9Sstevel@tonic-gate (void *)pdip, (void *)rdip, intr_op, (void *)hdlp)); 13167c478bd9Sstevel@tonic-gate 13177c478bd9Sstevel@tonic-gate /* Process the interrupt operation */ 13187c478bd9Sstevel@tonic-gate switch (intr_op) { 13197c478bd9Sstevel@tonic-gate case DDI_INTROP_GETCAP: 13207c478bd9Sstevel@tonic-gate /* First check with pcplusmp */ 13217c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 13227c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13237c478bd9Sstevel@tonic-gate 13247c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_GET_CAP, result)) { 13257c478bd9Sstevel@tonic-gate *(int *)result = 0; 13267c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13277c478bd9Sstevel@tonic-gate } 13287c478bd9Sstevel@tonic-gate break; 13297c478bd9Sstevel@tonic-gate case DDI_INTROP_SETCAP: 13307c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 13317c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13327c478bd9Sstevel@tonic-gate 13337c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_CAP, result)) 13347c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13357c478bd9Sstevel@tonic-gate break; 13367c478bd9Sstevel@tonic-gate case DDI_INTROP_ALLOC: 13377c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 13387c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13397c478bd9Sstevel@tonic-gate hdlp->ih_pri = ispec->intrspec_pri; 13407c478bd9Sstevel@tonic-gate *(int *)result = hdlp->ih_scratch1; 13417c478bd9Sstevel@tonic-gate break; 13427c478bd9Sstevel@tonic-gate case DDI_INTROP_FREE: 13437c478bd9Sstevel@tonic-gate pdp = ddi_get_parent_data(rdip); 13447c478bd9Sstevel@tonic-gate /* 13457c478bd9Sstevel@tonic-gate * Special case for 'pcic' driver' only. 13467c478bd9Sstevel@tonic-gate * If an intrspec was created for it, clean it up here 13477c478bd9Sstevel@tonic-gate * See detailed comments on this in the function 13487c478bd9Sstevel@tonic-gate * rootnex_get_ispec(). 13497c478bd9Sstevel@tonic-gate */ 13507c478bd9Sstevel@tonic-gate if (pdp->par_intr && strcmp(ddi_get_name(rdip), "pcic") == 0) { 13517c478bd9Sstevel@tonic-gate kmem_free(pdp->par_intr, sizeof (struct intrspec) * 13527c478bd9Sstevel@tonic-gate pdp->par_nintr); 13537c478bd9Sstevel@tonic-gate /* 13547c478bd9Sstevel@tonic-gate * Set it to zero; so that 13557c478bd9Sstevel@tonic-gate * DDI framework doesn't free it again 13567c478bd9Sstevel@tonic-gate */ 13577c478bd9Sstevel@tonic-gate pdp->par_intr = NULL; 13587c478bd9Sstevel@tonic-gate pdp->par_nintr = 0; 13597c478bd9Sstevel@tonic-gate } 13607c478bd9Sstevel@tonic-gate break; 13617c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPRI: 13627c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 13637c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13647c478bd9Sstevel@tonic-gate *(int *)result = ispec->intrspec_pri; 13657c478bd9Sstevel@tonic-gate break; 13667c478bd9Sstevel@tonic-gate case DDI_INTROP_SETPRI: 13677c478bd9Sstevel@tonic-gate /* Validate the interrupt priority passed to us */ 13687c478bd9Sstevel@tonic-gate if (*(int *)result > LOCK_LEVEL) 13697c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13707c478bd9Sstevel@tonic-gate 13717c478bd9Sstevel@tonic-gate /* Ensure that PSM is all initialized and ispec is ok */ 13727c478bd9Sstevel@tonic-gate if ((psm_intr_ops == NULL) || 13737c478bd9Sstevel@tonic-gate ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)) 13747c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13757c478bd9Sstevel@tonic-gate 13767c478bd9Sstevel@tonic-gate /* Change the priority */ 13777c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_PRI, result) == 13787c478bd9Sstevel@tonic-gate PSM_FAILURE) 13797c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13807c478bd9Sstevel@tonic-gate 13817c478bd9Sstevel@tonic-gate /* update the ispec with the new priority */ 13827c478bd9Sstevel@tonic-gate ispec->intrspec_pri = *(int *)result; 13837c478bd9Sstevel@tonic-gate break; 13847c478bd9Sstevel@tonic-gate case DDI_INTROP_ADDISR: 13857c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 13867c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13877c478bd9Sstevel@tonic-gate ispec->intrspec_func = hdlp->ih_cb_func; 13887c478bd9Sstevel@tonic-gate break; 13897c478bd9Sstevel@tonic-gate case DDI_INTROP_REMISR: 13907c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 13917c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13927c478bd9Sstevel@tonic-gate ispec->intrspec_func = (uint_t (*)()) 0; 13937c478bd9Sstevel@tonic-gate break; 13947c478bd9Sstevel@tonic-gate case DDI_INTROP_ENABLE: 13957c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 13967c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13977c478bd9Sstevel@tonic-gate 13987c478bd9Sstevel@tonic-gate /* Call psmi to translate irq with the dip */ 13997c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14007c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14017c478bd9Sstevel@tonic-gate 14027a364d25Sschwartz ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec; 14037c478bd9Sstevel@tonic-gate (void) (*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_XLATE_VECTOR, 14047c478bd9Sstevel@tonic-gate (int *)&hdlp->ih_vector); 14057c478bd9Sstevel@tonic-gate 14067c478bd9Sstevel@tonic-gate /* Add the interrupt handler */ 14077c478bd9Sstevel@tonic-gate if (!add_avintr((void *)hdlp, ispec->intrspec_pri, 14087c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, DEVI(rdip)->devi_name, hdlp->ih_vector, 14097a364d25Sschwartz hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, NULL, rdip)) 14107c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14117c478bd9Sstevel@tonic-gate break; 14127c478bd9Sstevel@tonic-gate case DDI_INTROP_DISABLE: 14137c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 14147c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14157c478bd9Sstevel@tonic-gate 14167c478bd9Sstevel@tonic-gate /* Call psm_ops() to translate irq with the dip */ 14177c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14187c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14197c478bd9Sstevel@tonic-gate 14207a364d25Sschwartz ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec; 14217c478bd9Sstevel@tonic-gate (void) (*psm_intr_ops)(rdip, hdlp, 14227c478bd9Sstevel@tonic-gate PSM_INTR_OP_XLATE_VECTOR, (int *)&hdlp->ih_vector); 14237c478bd9Sstevel@tonic-gate 14247c478bd9Sstevel@tonic-gate /* Remove the interrupt handler */ 14257c478bd9Sstevel@tonic-gate rem_avintr((void *)hdlp, ispec->intrspec_pri, 14267c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_vector); 14277c478bd9Sstevel@tonic-gate break; 14287c478bd9Sstevel@tonic-gate case DDI_INTROP_SETMASK: 14297c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14307c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14317c478bd9Sstevel@tonic-gate 14327c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_MASK, NULL)) 14337c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14347c478bd9Sstevel@tonic-gate break; 14357c478bd9Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 14367c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14377c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14387c478bd9Sstevel@tonic-gate 14397c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_CLEAR_MASK, NULL)) 14407c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14417c478bd9Sstevel@tonic-gate break; 14427c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 14437c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14447c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14457c478bd9Sstevel@tonic-gate 14467c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_GET_PENDING, 14477c478bd9Sstevel@tonic-gate result)) { 14487c478bd9Sstevel@tonic-gate *(int *)result = 0; 14497c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14507c478bd9Sstevel@tonic-gate } 14517c478bd9Sstevel@tonic-gate break; 1452a54f81fbSanish case DDI_INTROP_NAVAIL: 14537c478bd9Sstevel@tonic-gate case DDI_INTROP_NINTRS: 1454a54f81fbSanish *(int *)result = i_ddi_get_intx_nintrs(rdip); 1455a54f81fbSanish if (*(int *)result == 0) { 14567c478bd9Sstevel@tonic-gate /* 14577c478bd9Sstevel@tonic-gate * Special case for 'pcic' driver' only. This driver 14587c478bd9Sstevel@tonic-gate * driver is a child of 'isa' and 'rootnex' drivers. 14597c478bd9Sstevel@tonic-gate * 14607c478bd9Sstevel@tonic-gate * See detailed comments on this in the function 14617c478bd9Sstevel@tonic-gate * rootnex_get_ispec(). 14627c478bd9Sstevel@tonic-gate * 14637c478bd9Sstevel@tonic-gate * Children of 'pcic' send 'NINITR' request all the 14647c478bd9Sstevel@tonic-gate * way to rootnex driver. But, the 'pdp->par_nintr' 14657c478bd9Sstevel@tonic-gate * field may not initialized. So, we fake it here 14667c478bd9Sstevel@tonic-gate * to return 1 (a la what PCMCIA nexus does). 14677c478bd9Sstevel@tonic-gate */ 14687c478bd9Sstevel@tonic-gate if (strcmp(ddi_get_name(rdip), "pcic") == 0) 14697c478bd9Sstevel@tonic-gate *(int *)result = 1; 1470a54f81fbSanish else 1471a54f81fbSanish return (DDI_FAILURE); 14727c478bd9Sstevel@tonic-gate } 14737c478bd9Sstevel@tonic-gate break; 14747c478bd9Sstevel@tonic-gate case DDI_INTROP_SUPPORTED_TYPES: 1475a54f81fbSanish *(int *)result = DDI_INTR_TYPE_FIXED; /* Always ... */ 14767c478bd9Sstevel@tonic-gate break; 14777c478bd9Sstevel@tonic-gate default: 14787c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14797c478bd9Sstevel@tonic-gate } 14807c478bd9Sstevel@tonic-gate 14817c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 14827c478bd9Sstevel@tonic-gate } 14837c478bd9Sstevel@tonic-gate 14847c478bd9Sstevel@tonic-gate 14857c478bd9Sstevel@tonic-gate /* 148612f080e7Smrj * rootnex_get_ispec() 148712f080e7Smrj * convert an interrupt number to an interrupt specification. 148812f080e7Smrj * The interrupt number determines which interrupt spec will be 148912f080e7Smrj * returned if more than one exists. 149012f080e7Smrj * 149112f080e7Smrj * Look into the parent private data area of the 'rdip' to find out 149212f080e7Smrj * the interrupt specification. First check to make sure there is 149312f080e7Smrj * one that matchs "inumber" and then return a pointer to it. 149412f080e7Smrj * 149512f080e7Smrj * Return NULL if one could not be found. 149612f080e7Smrj * 149712f080e7Smrj * NOTE: This is needed for rootnex_intr_ops() 14987c478bd9Sstevel@tonic-gate */ 149912f080e7Smrj static struct intrspec * 150012f080e7Smrj rootnex_get_ispec(dev_info_t *rdip, int inum) 15017c478bd9Sstevel@tonic-gate { 150212f080e7Smrj struct ddi_parent_private_data *pdp = ddi_get_parent_data(rdip); 15037c478bd9Sstevel@tonic-gate 15047c478bd9Sstevel@tonic-gate /* 150512f080e7Smrj * Special case handling for drivers that provide their own 150612f080e7Smrj * intrspec structures instead of relying on the DDI framework. 150712f080e7Smrj * 150812f080e7Smrj * A broken hardware driver in ON could potentially provide its 150912f080e7Smrj * own intrspec structure, instead of relying on the hardware. 151012f080e7Smrj * If these drivers are children of 'rootnex' then we need to 151112f080e7Smrj * continue to provide backward compatibility to them here. 151212f080e7Smrj * 151312f080e7Smrj * Following check is a special case for 'pcic' driver which 151412f080e7Smrj * was found to have broken hardwre andby provides its own intrspec. 151512f080e7Smrj * 151612f080e7Smrj * Verbatim comments from this driver are shown here: 151712f080e7Smrj * "Don't use the ddi_add_intr since we don't have a 151812f080e7Smrj * default intrspec in all cases." 151912f080e7Smrj * 152012f080e7Smrj * Since an 'ispec' may not be always created for it, 152112f080e7Smrj * check for that and create one if so. 152212f080e7Smrj * 152312f080e7Smrj * NOTE: Currently 'pcic' is the only driver found to do this. 15247c478bd9Sstevel@tonic-gate */ 152512f080e7Smrj if (!pdp->par_intr && strcmp(ddi_get_name(rdip), "pcic") == 0) { 152612f080e7Smrj pdp->par_nintr = 1; 152712f080e7Smrj pdp->par_intr = kmem_zalloc(sizeof (struct intrspec) * 152812f080e7Smrj pdp->par_nintr, KM_SLEEP); 152912f080e7Smrj } 153012f080e7Smrj 153112f080e7Smrj /* Validate the interrupt number */ 153212f080e7Smrj if (inum >= pdp->par_nintr) 153312f080e7Smrj return (NULL); 153412f080e7Smrj 153512f080e7Smrj /* Get the interrupt structure pointer and return that */ 153612f080e7Smrj return ((struct intrspec *)&pdp->par_intr[inum]); 153712f080e7Smrj } 153812f080e7Smrj 153912f080e7Smrj 154012f080e7Smrj /* 154112f080e7Smrj * ****************** 154212f080e7Smrj * dma related code 154312f080e7Smrj * ****************** 154412f080e7Smrj */ 154512f080e7Smrj 154612f080e7Smrj /* 154712f080e7Smrj * rootnex_dma_allochdl() 154812f080e7Smrj * called from ddi_dma_alloc_handle(). 154912f080e7Smrj */ 155012f080e7Smrj /*ARGSUSED*/ 155112f080e7Smrj static int 155212f080e7Smrj rootnex_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attr, 155312f080e7Smrj int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 155412f080e7Smrj { 155512f080e7Smrj uint64_t maxsegmentsize_ll; 155612f080e7Smrj uint_t maxsegmentsize; 155712f080e7Smrj ddi_dma_impl_t *hp; 155812f080e7Smrj rootnex_dma_t *dma; 155912f080e7Smrj uint64_t count_max; 156012f080e7Smrj uint64_t seg; 156112f080e7Smrj int kmflag; 156212f080e7Smrj int e; 156312f080e7Smrj 156412f080e7Smrj 156512f080e7Smrj /* convert our sleep flags */ 156612f080e7Smrj if (waitfp == DDI_DMA_SLEEP) { 156712f080e7Smrj kmflag = KM_SLEEP; 156812f080e7Smrj } else { 156912f080e7Smrj kmflag = KM_NOSLEEP; 157012f080e7Smrj } 157112f080e7Smrj 157212f080e7Smrj /* 157312f080e7Smrj * We try to do only one memory allocation here. We'll do a little 157412f080e7Smrj * pointer manipulation later. If the bind ends up taking more than 157512f080e7Smrj * our prealloc's space, we'll have to allocate more memory in the 157612f080e7Smrj * bind operation. Not great, but much better than before and the 157712f080e7Smrj * best we can do with the current bind interfaces. 157812f080e7Smrj */ 157912f080e7Smrj hp = kmem_cache_alloc(rootnex_state->r_dmahdl_cache, kmflag); 158012f080e7Smrj if (hp == NULL) { 158112f080e7Smrj if (waitfp != DDI_DMA_DONTWAIT) { 158212f080e7Smrj ddi_set_callback(waitfp, arg, 158312f080e7Smrj &rootnex_state->r_dvma_call_list_id); 158412f080e7Smrj } 158512f080e7Smrj return (DDI_DMA_NORESOURCES); 158612f080e7Smrj } 158712f080e7Smrj 158812f080e7Smrj /* Do our pointer manipulation now, align the structures */ 158912f080e7Smrj hp->dmai_private = (void *)(((uintptr_t)hp + 159012f080e7Smrj (uintptr_t)sizeof (ddi_dma_impl_t) + 0x7) & ~0x7); 159112f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 159212f080e7Smrj dma->dp_prealloc_buffer = (uchar_t *)(((uintptr_t)dma + 159312f080e7Smrj sizeof (rootnex_dma_t) + 0x7) & ~0x7); 159412f080e7Smrj 159512f080e7Smrj /* setup the handle */ 159612f080e7Smrj rootnex_clean_dmahdl(hp); 159712f080e7Smrj dma->dp_dip = rdip; 159812f080e7Smrj dma->dp_sglinfo.si_min_addr = attr->dma_attr_addr_lo; 159912f080e7Smrj dma->dp_sglinfo.si_max_addr = attr->dma_attr_addr_hi; 160012f080e7Smrj hp->dmai_minxfer = attr->dma_attr_minxfer; 160112f080e7Smrj hp->dmai_burstsizes = attr->dma_attr_burstsizes; 160212f080e7Smrj hp->dmai_rdip = rdip; 160312f080e7Smrj hp->dmai_attr = *attr; 160412f080e7Smrj 160512f080e7Smrj /* we don't need to worry about the SPL since we do a tryenter */ 160612f080e7Smrj mutex_init(&dma->dp_mutex, NULL, MUTEX_DRIVER, NULL); 160712f080e7Smrj 160812f080e7Smrj /* 160912f080e7Smrj * Figure out our maximum segment size. If the segment size is greater 161012f080e7Smrj * than 4G, we will limit it to (4G - 1) since the max size of a dma 161112f080e7Smrj * object (ddi_dma_obj_t.dmao_size) is 32 bits. dma_attr_seg and 161212f080e7Smrj * dma_attr_count_max are size-1 type values. 161312f080e7Smrj * 161412f080e7Smrj * Maximum segment size is the largest physically contiguous chunk of 161512f080e7Smrj * memory that we can return from a bind (i.e. the maximum size of a 161612f080e7Smrj * single cookie). 161712f080e7Smrj */ 161812f080e7Smrj 161912f080e7Smrj /* handle the rollover cases */ 162012f080e7Smrj seg = attr->dma_attr_seg + 1; 162112f080e7Smrj if (seg < attr->dma_attr_seg) { 162212f080e7Smrj seg = attr->dma_attr_seg; 162312f080e7Smrj } 162412f080e7Smrj count_max = attr->dma_attr_count_max + 1; 162512f080e7Smrj if (count_max < attr->dma_attr_count_max) { 162612f080e7Smrj count_max = attr->dma_attr_count_max; 162712f080e7Smrj } 162812f080e7Smrj 162912f080e7Smrj /* 163012f080e7Smrj * granularity may or may not be a power of two. If it isn't, we can't 163112f080e7Smrj * use a simple mask. 163212f080e7Smrj */ 163312f080e7Smrj if (attr->dma_attr_granular & (attr->dma_attr_granular - 1)) { 163412f080e7Smrj dma->dp_granularity_power_2 = B_FALSE; 163512f080e7Smrj } else { 163612f080e7Smrj dma->dp_granularity_power_2 = B_TRUE; 163712f080e7Smrj } 163812f080e7Smrj 163912f080e7Smrj /* 164012f080e7Smrj * maxxfer should be a whole multiple of granularity. If we're going to 164112f080e7Smrj * break up a window because we're greater than maxxfer, we might as 164212f080e7Smrj * well make sure it's maxxfer is a whole multiple so we don't have to 164312f080e7Smrj * worry about triming the window later on for this case. 164412f080e7Smrj */ 164512f080e7Smrj if (attr->dma_attr_granular > 1) { 164612f080e7Smrj if (dma->dp_granularity_power_2) { 164712f080e7Smrj dma->dp_maxxfer = attr->dma_attr_maxxfer - 164812f080e7Smrj (attr->dma_attr_maxxfer & 164912f080e7Smrj (attr->dma_attr_granular - 1)); 165012f080e7Smrj } else { 165112f080e7Smrj dma->dp_maxxfer = attr->dma_attr_maxxfer - 165212f080e7Smrj (attr->dma_attr_maxxfer % attr->dma_attr_granular); 165312f080e7Smrj } 165412f080e7Smrj } else { 165512f080e7Smrj dma->dp_maxxfer = attr->dma_attr_maxxfer; 165612f080e7Smrj } 165712f080e7Smrj 165812f080e7Smrj maxsegmentsize_ll = MIN(seg, dma->dp_maxxfer); 165912f080e7Smrj maxsegmentsize_ll = MIN(maxsegmentsize_ll, count_max); 166012f080e7Smrj if (maxsegmentsize_ll == 0 || (maxsegmentsize_ll > 0xFFFFFFFF)) { 166112f080e7Smrj maxsegmentsize = 0xFFFFFFFF; 166212f080e7Smrj } else { 166312f080e7Smrj maxsegmentsize = maxsegmentsize_ll; 166412f080e7Smrj } 166512f080e7Smrj dma->dp_sglinfo.si_max_cookie_size = maxsegmentsize; 166612f080e7Smrj dma->dp_sglinfo.si_segmask = attr->dma_attr_seg; 166712f080e7Smrj 166812f080e7Smrj /* check the ddi_dma_attr arg to make sure it makes a little sense */ 166912f080e7Smrj if (rootnex_alloc_check_parms) { 167012f080e7Smrj e = rootnex_valid_alloc_parms(attr, maxsegmentsize); 167112f080e7Smrj if (e != DDI_SUCCESS) { 167212f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ALLOC_FAIL]); 167312f080e7Smrj (void) rootnex_dma_freehdl(dip, rdip, 167412f080e7Smrj (ddi_dma_handle_t)hp); 167512f080e7Smrj return (e); 167612f080e7Smrj } 167712f080e7Smrj } 167812f080e7Smrj 167912f080e7Smrj *handlep = (ddi_dma_handle_t)hp; 168012f080e7Smrj 168112f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]); 168212f080e7Smrj DTRACE_PROBE1(rootnex__alloc__handle, uint64_t, 168312f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]); 168412f080e7Smrj 168512f080e7Smrj return (DDI_SUCCESS); 168612f080e7Smrj } 168712f080e7Smrj 168812f080e7Smrj 168912f080e7Smrj /* 169012f080e7Smrj * rootnex_dma_freehdl() 169112f080e7Smrj * called from ddi_dma_free_handle(). 169212f080e7Smrj */ 169312f080e7Smrj /*ARGSUSED*/ 169412f080e7Smrj static int 169512f080e7Smrj rootnex_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 169612f080e7Smrj { 169712f080e7Smrj ddi_dma_impl_t *hp; 169812f080e7Smrj rootnex_dma_t *dma; 169912f080e7Smrj 170012f080e7Smrj 170112f080e7Smrj hp = (ddi_dma_impl_t *)handle; 170212f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 170312f080e7Smrj 170412f080e7Smrj /* unbind should have been called first */ 170512f080e7Smrj ASSERT(!dma->dp_inuse); 170612f080e7Smrj 170712f080e7Smrj mutex_destroy(&dma->dp_mutex); 170812f080e7Smrj kmem_cache_free(rootnex_state->r_dmahdl_cache, hp); 170912f080e7Smrj 171012f080e7Smrj ROOTNEX_PROF_DEC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]); 171112f080e7Smrj DTRACE_PROBE1(rootnex__free__handle, uint64_t, 171212f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]); 171312f080e7Smrj 171412f080e7Smrj if (rootnex_state->r_dvma_call_list_id) 171512f080e7Smrj ddi_run_callback(&rootnex_state->r_dvma_call_list_id); 171612f080e7Smrj 171712f080e7Smrj return (DDI_SUCCESS); 171812f080e7Smrj } 171912f080e7Smrj 172012f080e7Smrj 172112f080e7Smrj /* 172212f080e7Smrj * rootnex_dma_bindhdl() 172312f080e7Smrj * called from ddi_dma_addr_bind_handle() and ddi_dma_buf_bind_handle(). 172412f080e7Smrj */ 172512f080e7Smrj /*ARGSUSED*/ 172612f080e7Smrj static int 172712f080e7Smrj rootnex_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 172812f080e7Smrj struct ddi_dma_req *dmareq, ddi_dma_cookie_t *cookiep, uint_t *ccountp) 172912f080e7Smrj { 173012f080e7Smrj rootnex_sglinfo_t *sinfo; 173112f080e7Smrj ddi_dma_attr_t *attr; 173212f080e7Smrj ddi_dma_impl_t *hp; 173312f080e7Smrj rootnex_dma_t *dma; 173412f080e7Smrj int kmflag; 173512f080e7Smrj int e; 173612f080e7Smrj 173712f080e7Smrj 173812f080e7Smrj hp = (ddi_dma_impl_t *)handle; 173912f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 174012f080e7Smrj sinfo = &dma->dp_sglinfo; 174112f080e7Smrj attr = &hp->dmai_attr; 174212f080e7Smrj 174312f080e7Smrj hp->dmai_rflags = dmareq->dmar_flags & DMP_DDIFLAGS; 174412f080e7Smrj 174512f080e7Smrj /* 174612f080e7Smrj * This is useful for debugging a driver. Not as useful in a production 174712f080e7Smrj * system. The only time this will fail is if you have a driver bug. 174812f080e7Smrj */ 174912f080e7Smrj if (rootnex_bind_check_inuse) { 175012f080e7Smrj /* 175112f080e7Smrj * No one else should ever have this lock unless someone else 175212f080e7Smrj * is trying to use this handle. So contention on the lock 175312f080e7Smrj * is the same as inuse being set. 175412f080e7Smrj */ 175512f080e7Smrj e = mutex_tryenter(&dma->dp_mutex); 175612f080e7Smrj if (e == 0) { 175712f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 175812f080e7Smrj return (DDI_DMA_INUSE); 175912f080e7Smrj } 176012f080e7Smrj if (dma->dp_inuse) { 176112f080e7Smrj mutex_exit(&dma->dp_mutex); 176212f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 176312f080e7Smrj return (DDI_DMA_INUSE); 176412f080e7Smrj } 176512f080e7Smrj dma->dp_inuse = B_TRUE; 176612f080e7Smrj mutex_exit(&dma->dp_mutex); 176712f080e7Smrj } 176812f080e7Smrj 176912f080e7Smrj /* check the ddi_dma_attr arg to make sure it makes a little sense */ 177012f080e7Smrj if (rootnex_bind_check_parms) { 177112f080e7Smrj e = rootnex_valid_bind_parms(dmareq, attr); 177212f080e7Smrj if (e != DDI_SUCCESS) { 177312f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 177412f080e7Smrj rootnex_clean_dmahdl(hp); 177512f080e7Smrj return (e); 177612f080e7Smrj } 177712f080e7Smrj } 177812f080e7Smrj 177912f080e7Smrj /* save away the original bind info */ 178012f080e7Smrj dma->dp_dma = dmareq->dmar_object; 178112f080e7Smrj 1782*86c1f4dcSVikram Hegde if (rootnex_state->r_intel_iommu_enabled) { 1783*86c1f4dcSVikram Hegde e = intel_iommu_map_sgl(handle, dmareq, 1784*86c1f4dcSVikram Hegde rootnex_state->r_prealloc_cookies); 1785*86c1f4dcSVikram Hegde 1786*86c1f4dcSVikram Hegde switch (e) { 1787*86c1f4dcSVikram Hegde case IOMMU_SGL_SUCCESS: 1788*86c1f4dcSVikram Hegde goto rootnex_sgl_end; 1789*86c1f4dcSVikram Hegde 1790*86c1f4dcSVikram Hegde case IOMMU_SGL_DISABLE: 1791*86c1f4dcSVikram Hegde goto rootnex_sgl_start; 1792*86c1f4dcSVikram Hegde 1793*86c1f4dcSVikram Hegde case IOMMU_SGL_NORESOURCES: 1794*86c1f4dcSVikram Hegde cmn_err(CE_WARN, "iommu map sgl failed for %s", 1795*86c1f4dcSVikram Hegde ddi_node_name(dma->dp_dip)); 1796*86c1f4dcSVikram Hegde rootnex_clean_dmahdl(hp); 1797*86c1f4dcSVikram Hegde return (DDI_DMA_NORESOURCES); 1798*86c1f4dcSVikram Hegde 1799*86c1f4dcSVikram Hegde default: 1800*86c1f4dcSVikram Hegde cmn_err(CE_WARN, 1801*86c1f4dcSVikram Hegde "undefined value returned from" 1802*86c1f4dcSVikram Hegde " intel_iommu_map_sgl: %d", 1803*86c1f4dcSVikram Hegde e); 1804*86c1f4dcSVikram Hegde rootnex_clean_dmahdl(hp); 1805*86c1f4dcSVikram Hegde return (DDI_DMA_NORESOURCES); 1806*86c1f4dcSVikram Hegde } 1807*86c1f4dcSVikram Hegde } 1808*86c1f4dcSVikram Hegde 1809*86c1f4dcSVikram Hegde rootnex_sgl_start: 181012f080e7Smrj /* 181112f080e7Smrj * Figure out a rough estimate of what maximum number of pages this 181212f080e7Smrj * buffer could use (a high estimate of course). 181312f080e7Smrj */ 181412f080e7Smrj sinfo->si_max_pages = mmu_btopr(dma->dp_dma.dmao_size) + 1; 181512f080e7Smrj 181612f080e7Smrj /* 181712f080e7Smrj * We'll use the pre-allocated cookies for any bind that will *always* 181812f080e7Smrj * fit (more important to be consistent, we don't want to create 181912f080e7Smrj * additional degenerate cases). 182012f080e7Smrj */ 182112f080e7Smrj if (sinfo->si_max_pages <= rootnex_state->r_prealloc_cookies) { 182212f080e7Smrj dma->dp_cookies = (ddi_dma_cookie_t *)dma->dp_prealloc_buffer; 182312f080e7Smrj dma->dp_need_to_free_cookie = B_FALSE; 182412f080e7Smrj DTRACE_PROBE2(rootnex__bind__prealloc, dev_info_t *, rdip, 182512f080e7Smrj uint_t, sinfo->si_max_pages); 182612f080e7Smrj 182712f080e7Smrj /* 182812f080e7Smrj * For anything larger than that, we'll go ahead and allocate the 182912f080e7Smrj * maximum number of pages we expect to see. Hopefuly, we won't be 183012f080e7Smrj * seeing this path in the fast path for high performance devices very 183112f080e7Smrj * frequently. 183212f080e7Smrj * 183312f080e7Smrj * a ddi bind interface that allowed the driver to provide storage to 183412f080e7Smrj * the bind interface would speed this case up. 183512f080e7Smrj */ 183612f080e7Smrj } else { 183712f080e7Smrj /* convert the sleep flags */ 183812f080e7Smrj if (dmareq->dmar_fp == DDI_DMA_SLEEP) { 183912f080e7Smrj kmflag = KM_SLEEP; 184012f080e7Smrj } else { 184112f080e7Smrj kmflag = KM_NOSLEEP; 184212f080e7Smrj } 184312f080e7Smrj 184412f080e7Smrj /* 184512f080e7Smrj * Save away how much memory we allocated. If we're doing a 184612f080e7Smrj * nosleep, the alloc could fail... 184712f080e7Smrj */ 184812f080e7Smrj dma->dp_cookie_size = sinfo->si_max_pages * 184912f080e7Smrj sizeof (ddi_dma_cookie_t); 185012f080e7Smrj dma->dp_cookies = kmem_alloc(dma->dp_cookie_size, kmflag); 185112f080e7Smrj if (dma->dp_cookies == NULL) { 185212f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 185312f080e7Smrj rootnex_clean_dmahdl(hp); 185412f080e7Smrj return (DDI_DMA_NORESOURCES); 185512f080e7Smrj } 185612f080e7Smrj dma->dp_need_to_free_cookie = B_TRUE; 185712f080e7Smrj DTRACE_PROBE2(rootnex__bind__alloc, dev_info_t *, rdip, uint_t, 185812f080e7Smrj sinfo->si_max_pages); 185912f080e7Smrj } 186012f080e7Smrj hp->dmai_cookie = dma->dp_cookies; 186112f080e7Smrj 186212f080e7Smrj /* 186312f080e7Smrj * Get the real sgl. rootnex_get_sgl will fill in cookie array while 186412f080e7Smrj * looking at the contraints in the dma structure. It will then put some 186512f080e7Smrj * additional state about the sgl in the dma struct (i.e. is the sgl 186612f080e7Smrj * clean, or do we need to do some munging; how many pages need to be 186712f080e7Smrj * copied, etc.) 186812f080e7Smrj */ 186912f080e7Smrj rootnex_get_sgl(&dmareq->dmar_object, dma->dp_cookies, 187012f080e7Smrj &dma->dp_sglinfo); 187112f080e7Smrj 1872*86c1f4dcSVikram Hegde rootnex_sgl_end: 1873*86c1f4dcSVikram Hegde ASSERT(sinfo->si_sgl_size <= sinfo->si_max_pages); 187412f080e7Smrj /* if we don't need a copy buffer, we don't need to sync */ 187512f080e7Smrj if (sinfo->si_copybuf_req == 0) { 187612f080e7Smrj hp->dmai_rflags |= DMP_NOSYNC; 187712f080e7Smrj } 187812f080e7Smrj 187912f080e7Smrj /* 188012f080e7Smrj * if we don't need the copybuf and we don't need to do a partial, we 188112f080e7Smrj * hit the fast path. All the high performance devices should be trying 188212f080e7Smrj * to hit this path. To hit this path, a device should be able to reach 188312f080e7Smrj * all of memory, shouldn't try to bind more than it can transfer, and 188412f080e7Smrj * the buffer shouldn't require more cookies than the driver/device can 188512f080e7Smrj * handle [sgllen]). 188612f080e7Smrj */ 188712f080e7Smrj if ((sinfo->si_copybuf_req == 0) && 188812f080e7Smrj (sinfo->si_sgl_size <= attr->dma_attr_sgllen) && 188912f080e7Smrj (dma->dp_dma.dmao_size < dma->dp_maxxfer)) { 189012f080e7Smrj /* 189185c8e0e8Sstephh * If the driver supports FMA, insert the handle in the FMA DMA 189285c8e0e8Sstephh * handle cache. 189385c8e0e8Sstephh */ 189485c8e0e8Sstephh if (attr->dma_attr_flags & DDI_DMA_FLAGERR) { 189585c8e0e8Sstephh hp->dmai_error.err_cf = rootnex_dma_check; 189685c8e0e8Sstephh (void) ndi_fmc_insert(rdip, DMA_HANDLE, hp, NULL); 189785c8e0e8Sstephh } 189885c8e0e8Sstephh 189985c8e0e8Sstephh /* 190012f080e7Smrj * copy out the first cookie and ccountp, set the cookie 190112f080e7Smrj * pointer to the second cookie. The first cookie is passed 190212f080e7Smrj * back on the stack. Additional cookies are accessed via 190312f080e7Smrj * ddi_dma_nextcookie() 190412f080e7Smrj */ 190512f080e7Smrj *cookiep = dma->dp_cookies[0]; 190612f080e7Smrj *ccountp = sinfo->si_sgl_size; 190712f080e7Smrj hp->dmai_cookie++; 190812f080e7Smrj hp->dmai_rflags &= ~DDI_DMA_PARTIAL; 190912f080e7Smrj hp->dmai_nwin = 1; 191012f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]); 191112f080e7Smrj DTRACE_PROBE3(rootnex__bind__fast, dev_info_t *, rdip, uint64_t, 191212f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS], uint_t, 191312f080e7Smrj dma->dp_dma.dmao_size); 191412f080e7Smrj return (DDI_DMA_MAPPED); 191512f080e7Smrj } 191612f080e7Smrj 191712f080e7Smrj /* 191812f080e7Smrj * go to the slow path, we may need to alloc more memory, create 191912f080e7Smrj * multiple windows, and munge up a sgl to make the device happy. 192012f080e7Smrj */ 192112f080e7Smrj e = rootnex_bind_slowpath(hp, dmareq, dma, attr, kmflag); 192212f080e7Smrj if ((e != DDI_DMA_MAPPED) && (e != DDI_DMA_PARTIAL_MAP)) { 192312f080e7Smrj if (dma->dp_need_to_free_cookie) { 192412f080e7Smrj kmem_free(dma->dp_cookies, dma->dp_cookie_size); 192512f080e7Smrj } 192612f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 192712f080e7Smrj rootnex_clean_dmahdl(hp); /* must be after free cookie */ 192812f080e7Smrj return (e); 192912f080e7Smrj } 193012f080e7Smrj 193185c8e0e8Sstephh /* 193285c8e0e8Sstephh * If the driver supports FMA, insert the handle in the FMA DMA handle 193385c8e0e8Sstephh * cache. 193485c8e0e8Sstephh */ 193585c8e0e8Sstephh if (attr->dma_attr_flags & DDI_DMA_FLAGERR) { 193685c8e0e8Sstephh hp->dmai_error.err_cf = rootnex_dma_check; 193785c8e0e8Sstephh (void) ndi_fmc_insert(rdip, DMA_HANDLE, hp, NULL); 193885c8e0e8Sstephh } 193985c8e0e8Sstephh 194012f080e7Smrj /* if the first window uses the copy buffer, sync it for the device */ 194112f080e7Smrj if ((dma->dp_window[dma->dp_current_win].wd_dosync) && 194212f080e7Smrj (hp->dmai_rflags & DDI_DMA_WRITE)) { 194312f080e7Smrj (void) rootnex_dma_sync(dip, rdip, handle, 0, 0, 194412f080e7Smrj DDI_DMA_SYNC_FORDEV); 194512f080e7Smrj } 194612f080e7Smrj 194712f080e7Smrj /* 194812f080e7Smrj * copy out the first cookie and ccountp, set the cookie pointer to the 194912f080e7Smrj * second cookie. Make sure the partial flag is set/cleared correctly. 195012f080e7Smrj * If we have a partial map (i.e. multiple windows), the number of 195112f080e7Smrj * cookies we return is the number of cookies in the first window. 195212f080e7Smrj */ 195312f080e7Smrj if (e == DDI_DMA_MAPPED) { 195412f080e7Smrj hp->dmai_rflags &= ~DDI_DMA_PARTIAL; 195512f080e7Smrj *ccountp = sinfo->si_sgl_size; 195612f080e7Smrj } else { 195712f080e7Smrj hp->dmai_rflags |= DDI_DMA_PARTIAL; 195812f080e7Smrj *ccountp = dma->dp_window[dma->dp_current_win].wd_cookie_cnt; 195912f080e7Smrj ASSERT(hp->dmai_nwin <= dma->dp_max_win); 196012f080e7Smrj } 196112f080e7Smrj *cookiep = dma->dp_cookies[0]; 196212f080e7Smrj hp->dmai_cookie++; 196312f080e7Smrj 196412f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]); 196512f080e7Smrj DTRACE_PROBE3(rootnex__bind__slow, dev_info_t *, rdip, uint64_t, 196612f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS], uint_t, 196712f080e7Smrj dma->dp_dma.dmao_size); 196812f080e7Smrj return (e); 196912f080e7Smrj } 197012f080e7Smrj 197112f080e7Smrj 197212f080e7Smrj /* 197312f080e7Smrj * rootnex_dma_unbindhdl() 197412f080e7Smrj * called from ddi_dma_unbind_handle() 197512f080e7Smrj */ 197612f080e7Smrj /*ARGSUSED*/ 197712f080e7Smrj static int 197812f080e7Smrj rootnex_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 197912f080e7Smrj ddi_dma_handle_t handle) 198012f080e7Smrj { 198112f080e7Smrj ddi_dma_impl_t *hp; 198212f080e7Smrj rootnex_dma_t *dma; 198312f080e7Smrj int e; 198412f080e7Smrj 198512f080e7Smrj 198612f080e7Smrj hp = (ddi_dma_impl_t *)handle; 198712f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 198812f080e7Smrj 198912f080e7Smrj /* make sure the buffer wasn't free'd before calling unbind */ 199012f080e7Smrj if (rootnex_unbind_verify_buffer) { 199112f080e7Smrj e = rootnex_verify_buffer(dma); 199212f080e7Smrj if (e != DDI_SUCCESS) { 199312f080e7Smrj ASSERT(0); 199412f080e7Smrj return (DDI_FAILURE); 199512f080e7Smrj } 199612f080e7Smrj } 199712f080e7Smrj 199812f080e7Smrj /* sync the current window before unbinding the buffer */ 199912f080e7Smrj if (dma->dp_window && dma->dp_window[dma->dp_current_win].wd_dosync && 200012f080e7Smrj (hp->dmai_rflags & DDI_DMA_READ)) { 200112f080e7Smrj (void) rootnex_dma_sync(dip, rdip, handle, 0, 0, 200212f080e7Smrj DDI_DMA_SYNC_FORCPU); 200312f080e7Smrj } 200412f080e7Smrj 200512f080e7Smrj /* 200600d0963fSdilpreet * If the driver supports FMA, remove the handle in the FMA DMA handle 200700d0963fSdilpreet * cache. 200800d0963fSdilpreet */ 200900d0963fSdilpreet if (hp->dmai_attr.dma_attr_flags & DDI_DMA_FLAGERR) { 201000d0963fSdilpreet if ((DEVI(rdip)->devi_fmhdl != NULL) && 201100d0963fSdilpreet (DDI_FM_DMA_ERR_CAP(DEVI(rdip)->devi_fmhdl->fh_cap))) { 201200d0963fSdilpreet (void) ndi_fmc_remove(rdip, DMA_HANDLE, hp); 201300d0963fSdilpreet } 201400d0963fSdilpreet } 201500d0963fSdilpreet 201600d0963fSdilpreet /* 201712f080e7Smrj * cleanup and copy buffer or window state. if we didn't use the copy 201812f080e7Smrj * buffer or windows, there won't be much to do :-) 201912f080e7Smrj */ 202012f080e7Smrj rootnex_teardown_copybuf(dma); 202112f080e7Smrj rootnex_teardown_windows(dma); 202212f080e7Smrj 202312f080e7Smrj /* 2024*86c1f4dcSVikram Hegde * If intel iommu enabled, clean up the page tables and free the dvma 2025*86c1f4dcSVikram Hegde */ 2026*86c1f4dcSVikram Hegde if (rootnex_state->r_intel_iommu_enabled) { 2027*86c1f4dcSVikram Hegde intel_iommu_unmap_sgl(handle); 2028*86c1f4dcSVikram Hegde } 2029*86c1f4dcSVikram Hegde 2030*86c1f4dcSVikram Hegde /* 203112f080e7Smrj * If we had to allocate space to for the worse case sgl (it didn't 203212f080e7Smrj * fit into our pre-allocate buffer), free that up now 203312f080e7Smrj */ 203412f080e7Smrj if (dma->dp_need_to_free_cookie) { 203512f080e7Smrj kmem_free(dma->dp_cookies, dma->dp_cookie_size); 203612f080e7Smrj } 203712f080e7Smrj 203812f080e7Smrj /* 203912f080e7Smrj * clean up the handle so it's ready for the next bind (i.e. if the 204012f080e7Smrj * handle is reused). 204112f080e7Smrj */ 204212f080e7Smrj rootnex_clean_dmahdl(hp); 204312f080e7Smrj 204412f080e7Smrj if (rootnex_state->r_dvma_call_list_id) 204512f080e7Smrj ddi_run_callback(&rootnex_state->r_dvma_call_list_id); 204612f080e7Smrj 204712f080e7Smrj ROOTNEX_PROF_DEC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]); 204812f080e7Smrj DTRACE_PROBE1(rootnex__unbind, uint64_t, 204912f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]); 205012f080e7Smrj 205112f080e7Smrj return (DDI_SUCCESS); 205212f080e7Smrj } 205312f080e7Smrj 205412f080e7Smrj 205512f080e7Smrj /* 205612f080e7Smrj * rootnex_verify_buffer() 205712f080e7Smrj * verify buffer wasn't free'd 205812f080e7Smrj */ 205912f080e7Smrj static int 206012f080e7Smrj rootnex_verify_buffer(rootnex_dma_t *dma) 206112f080e7Smrj { 206212f080e7Smrj page_t **pplist; 206312f080e7Smrj caddr_t vaddr; 206412f080e7Smrj uint_t pcnt; 206512f080e7Smrj uint_t poff; 206612f080e7Smrj page_t *pp; 206700d0963fSdilpreet char b; 206812f080e7Smrj int i; 206912f080e7Smrj 207012f080e7Smrj /* Figure out how many pages this buffer occupies */ 207112f080e7Smrj if (dma->dp_dma.dmao_type == DMA_OTYP_PAGES) { 207212f080e7Smrj poff = dma->dp_dma.dmao_obj.pp_obj.pp_offset & MMU_PAGEOFFSET; 207312f080e7Smrj } else { 207412f080e7Smrj vaddr = dma->dp_dma.dmao_obj.virt_obj.v_addr; 207512f080e7Smrj poff = (uintptr_t)vaddr & MMU_PAGEOFFSET; 207612f080e7Smrj } 207712f080e7Smrj pcnt = mmu_btopr(dma->dp_dma.dmao_size + poff); 207812f080e7Smrj 207912f080e7Smrj switch (dma->dp_dma.dmao_type) { 208012f080e7Smrj case DMA_OTYP_PAGES: 208112f080e7Smrj /* 208212f080e7Smrj * for a linked list of pp's walk through them to make sure 208312f080e7Smrj * they're locked and not free. 208412f080e7Smrj */ 208512f080e7Smrj pp = dma->dp_dma.dmao_obj.pp_obj.pp_pp; 208612f080e7Smrj for (i = 0; i < pcnt; i++) { 208712f080e7Smrj if (PP_ISFREE(pp) || !PAGE_LOCKED(pp)) { 208812f080e7Smrj return (DDI_FAILURE); 208912f080e7Smrj } 20907c478bd9Sstevel@tonic-gate pp = pp->p_next; 20917c478bd9Sstevel@tonic-gate } 20927c478bd9Sstevel@tonic-gate break; 209312f080e7Smrj 20947c478bd9Sstevel@tonic-gate case DMA_OTYP_VADDR: 20957c478bd9Sstevel@tonic-gate case DMA_OTYP_BUFVADDR: 209612f080e7Smrj pplist = dma->dp_dma.dmao_obj.virt_obj.v_priv; 209712f080e7Smrj /* 209812f080e7Smrj * for an array of pp's walk through them to make sure they're 209912f080e7Smrj * not free. It's possible that they may not be locked. 210012f080e7Smrj */ 210112f080e7Smrj if (pplist) { 210212f080e7Smrj for (i = 0; i < pcnt; i++) { 210312f080e7Smrj if (PP_ISFREE(pplist[i])) { 210412f080e7Smrj return (DDI_FAILURE); 210512f080e7Smrj } 210612f080e7Smrj } 210712f080e7Smrj 210812f080e7Smrj /* For a virtual address, try to peek at each page */ 210912f080e7Smrj } else { 211012f080e7Smrj if (dma->dp_sglinfo.si_asp == &kas) { 211112f080e7Smrj for (i = 0; i < pcnt; i++) { 211200d0963fSdilpreet if (ddi_peek8(NULL, vaddr, &b) == 211300d0963fSdilpreet DDI_FAILURE) 211412f080e7Smrj return (DDI_FAILURE); 211500d0963fSdilpreet vaddr += MMU_PAGESIZE; 211612f080e7Smrj } 211712f080e7Smrj } 211812f080e7Smrj } 211912f080e7Smrj break; 212012f080e7Smrj 212112f080e7Smrj default: 212212f080e7Smrj ASSERT(0); 212312f080e7Smrj break; 212412f080e7Smrj } 212512f080e7Smrj 212612f080e7Smrj return (DDI_SUCCESS); 212712f080e7Smrj } 212812f080e7Smrj 212912f080e7Smrj 213012f080e7Smrj /* 213112f080e7Smrj * rootnex_clean_dmahdl() 213212f080e7Smrj * Clean the dma handle. This should be called on a handle alloc and an 213312f080e7Smrj * unbind handle. Set the handle state to the default settings. 213412f080e7Smrj */ 213512f080e7Smrj static void 213612f080e7Smrj rootnex_clean_dmahdl(ddi_dma_impl_t *hp) 213712f080e7Smrj { 213812f080e7Smrj rootnex_dma_t *dma; 213912f080e7Smrj 214012f080e7Smrj 214112f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 214212f080e7Smrj 214312f080e7Smrj hp->dmai_nwin = 0; 214412f080e7Smrj dma->dp_current_cookie = 0; 214512f080e7Smrj dma->dp_copybuf_size = 0; 214612f080e7Smrj dma->dp_window = NULL; 214712f080e7Smrj dma->dp_cbaddr = NULL; 214812f080e7Smrj dma->dp_inuse = B_FALSE; 214912f080e7Smrj dma->dp_need_to_free_cookie = B_FALSE; 215012f080e7Smrj dma->dp_need_to_free_window = B_FALSE; 215112f080e7Smrj dma->dp_partial_required = B_FALSE; 215212f080e7Smrj dma->dp_trim_required = B_FALSE; 215312f080e7Smrj dma->dp_sglinfo.si_copybuf_req = 0; 215412f080e7Smrj #if !defined(__amd64) 215512f080e7Smrj dma->dp_cb_remaping = B_FALSE; 215612f080e7Smrj dma->dp_kva = NULL; 215712f080e7Smrj #endif 215812f080e7Smrj 215912f080e7Smrj /* FMA related initialization */ 216012f080e7Smrj hp->dmai_fault = 0; 216112f080e7Smrj hp->dmai_fault_check = NULL; 216212f080e7Smrj hp->dmai_fault_notify = NULL; 216312f080e7Smrj hp->dmai_error.err_ena = 0; 216412f080e7Smrj hp->dmai_error.err_status = DDI_FM_OK; 216512f080e7Smrj hp->dmai_error.err_expected = DDI_FM_ERR_UNEXPECTED; 216612f080e7Smrj hp->dmai_error.err_ontrap = NULL; 216712f080e7Smrj hp->dmai_error.err_fep = NULL; 216800d0963fSdilpreet hp->dmai_error.err_cf = NULL; 216912f080e7Smrj } 217012f080e7Smrj 217112f080e7Smrj 217212f080e7Smrj /* 217312f080e7Smrj * rootnex_valid_alloc_parms() 217412f080e7Smrj * Called in ddi_dma_alloc_handle path to validate its parameters. 217512f080e7Smrj */ 217612f080e7Smrj static int 217712f080e7Smrj rootnex_valid_alloc_parms(ddi_dma_attr_t *attr, uint_t maxsegmentsize) 217812f080e7Smrj { 217912f080e7Smrj if ((attr->dma_attr_seg < MMU_PAGEOFFSET) || 218012f080e7Smrj (attr->dma_attr_count_max < MMU_PAGEOFFSET) || 218112f080e7Smrj (attr->dma_attr_granular > MMU_PAGESIZE) || 218212f080e7Smrj (attr->dma_attr_maxxfer < MMU_PAGESIZE)) { 218312f080e7Smrj return (DDI_DMA_BADATTR); 218412f080e7Smrj } 218512f080e7Smrj 218612f080e7Smrj if (attr->dma_attr_addr_hi <= attr->dma_attr_addr_lo) { 218712f080e7Smrj return (DDI_DMA_BADATTR); 218812f080e7Smrj } 218912f080e7Smrj 219012f080e7Smrj if ((attr->dma_attr_seg & MMU_PAGEOFFSET) != MMU_PAGEOFFSET || 219112f080e7Smrj MMU_PAGESIZE & (attr->dma_attr_granular - 1) || 219212f080e7Smrj attr->dma_attr_sgllen <= 0) { 219312f080e7Smrj return (DDI_DMA_BADATTR); 219412f080e7Smrj } 219512f080e7Smrj 219612f080e7Smrj /* We should be able to DMA into every byte offset in a page */ 219712f080e7Smrj if (maxsegmentsize < MMU_PAGESIZE) { 219812f080e7Smrj return (DDI_DMA_BADATTR); 219912f080e7Smrj } 220012f080e7Smrj 220112f080e7Smrj return (DDI_SUCCESS); 220212f080e7Smrj } 220312f080e7Smrj 220412f080e7Smrj 220512f080e7Smrj /* 220612f080e7Smrj * rootnex_valid_bind_parms() 220712f080e7Smrj * Called in ddi_dma_*_bind_handle path to validate its parameters. 220812f080e7Smrj */ 220912f080e7Smrj /* ARGSUSED */ 221012f080e7Smrj static int 221112f080e7Smrj rootnex_valid_bind_parms(ddi_dma_req_t *dmareq, ddi_dma_attr_t *attr) 221212f080e7Smrj { 221312f080e7Smrj #if !defined(__amd64) 221412f080e7Smrj /* 221512f080e7Smrj * we only support up to a 2G-1 transfer size on 32-bit kernels so 221612f080e7Smrj * we can track the offset for the obsoleted interfaces. 221712f080e7Smrj */ 221812f080e7Smrj if (dmareq->dmar_object.dmao_size > 0x7FFFFFFF) { 221912f080e7Smrj return (DDI_DMA_TOOBIG); 222012f080e7Smrj } 222112f080e7Smrj #endif 222212f080e7Smrj 222312f080e7Smrj return (DDI_SUCCESS); 222412f080e7Smrj } 222512f080e7Smrj 222612f080e7Smrj 222712f080e7Smrj /* 222812f080e7Smrj * rootnex_get_sgl() 222912f080e7Smrj * Called in bind fastpath to get the sgl. Most of this will be replaced 223012f080e7Smrj * with a call to the vm layer when vm2.0 comes around... 223112f080e7Smrj */ 223212f080e7Smrj static void 223312f080e7Smrj rootnex_get_sgl(ddi_dma_obj_t *dmar_object, ddi_dma_cookie_t *sgl, 223412f080e7Smrj rootnex_sglinfo_t *sglinfo) 223512f080e7Smrj { 223612f080e7Smrj ddi_dma_atyp_t buftype; 2237843e1988Sjohnlev rootnex_addr_t raddr; 223812f080e7Smrj uint64_t last_page; 223912f080e7Smrj uint64_t offset; 224012f080e7Smrj uint64_t addrhi; 224112f080e7Smrj uint64_t addrlo; 224212f080e7Smrj uint64_t maxseg; 224312f080e7Smrj page_t **pplist; 224412f080e7Smrj uint64_t paddr; 224512f080e7Smrj uint32_t psize; 224612f080e7Smrj uint32_t size; 224712f080e7Smrj caddr_t vaddr; 224812f080e7Smrj uint_t pcnt; 224912f080e7Smrj page_t *pp; 225012f080e7Smrj uint_t cnt; 225112f080e7Smrj 225212f080e7Smrj 225312f080e7Smrj /* shortcuts */ 225412f080e7Smrj pplist = dmar_object->dmao_obj.virt_obj.v_priv; 225512f080e7Smrj vaddr = dmar_object->dmao_obj.virt_obj.v_addr; 225612f080e7Smrj maxseg = sglinfo->si_max_cookie_size; 225712f080e7Smrj buftype = dmar_object->dmao_type; 225812f080e7Smrj addrhi = sglinfo->si_max_addr; 225912f080e7Smrj addrlo = sglinfo->si_min_addr; 226012f080e7Smrj size = dmar_object->dmao_size; 226112f080e7Smrj 226212f080e7Smrj pcnt = 0; 226312f080e7Smrj cnt = 0; 226412f080e7Smrj 226512f080e7Smrj /* 226612f080e7Smrj * if we were passed down a linked list of pages, i.e. pointer to 226712f080e7Smrj * page_t, use this to get our physical address and buf offset. 226812f080e7Smrj */ 226912f080e7Smrj if (buftype == DMA_OTYP_PAGES) { 227012f080e7Smrj pp = dmar_object->dmao_obj.pp_obj.pp_pp; 227112f080e7Smrj ASSERT(!PP_ISFREE(pp) && PAGE_LOCKED(pp)); 227212f080e7Smrj offset = dmar_object->dmao_obj.pp_obj.pp_offset & 227312f080e7Smrj MMU_PAGEOFFSET; 2274843e1988Sjohnlev paddr = pfn_to_pa(pp->p_pagenum) + offset; 227512f080e7Smrj psize = MIN(size, (MMU_PAGESIZE - offset)); 227612f080e7Smrj pp = pp->p_next; 227712f080e7Smrj sglinfo->si_asp = NULL; 227812f080e7Smrj 227912f080e7Smrj /* 228012f080e7Smrj * We weren't passed down a linked list of pages, but if we were passed 228112f080e7Smrj * down an array of pages, use this to get our physical address and buf 228212f080e7Smrj * offset. 228312f080e7Smrj */ 228412f080e7Smrj } else if (pplist != NULL) { 228512f080e7Smrj ASSERT((buftype == DMA_OTYP_VADDR) || 228612f080e7Smrj (buftype == DMA_OTYP_BUFVADDR)); 228712f080e7Smrj 228812f080e7Smrj offset = (uintptr_t)vaddr & MMU_PAGEOFFSET; 228912f080e7Smrj sglinfo->si_asp = dmar_object->dmao_obj.virt_obj.v_as; 229012f080e7Smrj if (sglinfo->si_asp == NULL) { 229112f080e7Smrj sglinfo->si_asp = &kas; 229212f080e7Smrj } 229312f080e7Smrj 229412f080e7Smrj ASSERT(!PP_ISFREE(pplist[pcnt])); 2295843e1988Sjohnlev paddr = pfn_to_pa(pplist[pcnt]->p_pagenum); 229612f080e7Smrj paddr += offset; 229712f080e7Smrj psize = MIN(size, (MMU_PAGESIZE - offset)); 229812f080e7Smrj pcnt++; 229912f080e7Smrj 230012f080e7Smrj /* 230112f080e7Smrj * All we have is a virtual address, we'll need to call into the VM 230212f080e7Smrj * to get the physical address. 230312f080e7Smrj */ 230412f080e7Smrj } else { 230512f080e7Smrj ASSERT((buftype == DMA_OTYP_VADDR) || 230612f080e7Smrj (buftype == DMA_OTYP_BUFVADDR)); 230712f080e7Smrj 230812f080e7Smrj offset = (uintptr_t)vaddr & MMU_PAGEOFFSET; 230912f080e7Smrj sglinfo->si_asp = dmar_object->dmao_obj.virt_obj.v_as; 231012f080e7Smrj if (sglinfo->si_asp == NULL) { 231112f080e7Smrj sglinfo->si_asp = &kas; 231212f080e7Smrj } 231312f080e7Smrj 2314843e1988Sjohnlev paddr = pfn_to_pa(hat_getpfnum(sglinfo->si_asp->a_hat, vaddr)); 231512f080e7Smrj paddr += offset; 231612f080e7Smrj psize = MIN(size, (MMU_PAGESIZE - offset)); 231712f080e7Smrj vaddr += psize; 231812f080e7Smrj } 231912f080e7Smrj 2320843e1988Sjohnlev #ifdef __xpv 2321843e1988Sjohnlev /* 2322843e1988Sjohnlev * If we're dom0, we're using a real device so we need to load 2323843e1988Sjohnlev * the cookies with MFNs instead of PFNs. 2324843e1988Sjohnlev */ 2325843e1988Sjohnlev raddr = ROOTNEX_PADDR_TO_RBASE(xen_info, paddr); 2326843e1988Sjohnlev #else 2327843e1988Sjohnlev raddr = paddr; 2328843e1988Sjohnlev #endif 2329843e1988Sjohnlev 233012f080e7Smrj /* 233112f080e7Smrj * Setup the first cookie with the physical address of the page and the 233212f080e7Smrj * size of the page (which takes into account the initial offset into 233312f080e7Smrj * the page. 233412f080e7Smrj */ 2335843e1988Sjohnlev sgl[cnt].dmac_laddress = raddr; 233612f080e7Smrj sgl[cnt].dmac_size = psize; 233712f080e7Smrj sgl[cnt].dmac_type = 0; 233812f080e7Smrj 233912f080e7Smrj /* 234012f080e7Smrj * Save away the buffer offset into the page. We'll need this later in 234112f080e7Smrj * the copy buffer code to help figure out the page index within the 234212f080e7Smrj * buffer and the offset into the current page. 234312f080e7Smrj */ 234412f080e7Smrj sglinfo->si_buf_offset = offset; 234512f080e7Smrj 234612f080e7Smrj /* 234712f080e7Smrj * If the DMA engine can't reach the physical address, increase how 234812f080e7Smrj * much copy buffer we need. We always increase by pagesize so we don't 234912f080e7Smrj * have to worry about converting offsets. Set a flag in the cookies 235012f080e7Smrj * dmac_type to indicate that it uses the copy buffer. If this isn't the 235112f080e7Smrj * last cookie, go to the next cookie (since we separate each page which 235212f080e7Smrj * uses the copy buffer in case the copy buffer is not physically 235312f080e7Smrj * contiguous. 235412f080e7Smrj */ 2355843e1988Sjohnlev if ((raddr < addrlo) || ((raddr + psize) > addrhi)) { 235612f080e7Smrj sglinfo->si_copybuf_req += MMU_PAGESIZE; 235712f080e7Smrj sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF; 235812f080e7Smrj if ((cnt + 1) < sglinfo->si_max_pages) { 235912f080e7Smrj cnt++; 236012f080e7Smrj sgl[cnt].dmac_laddress = 0; 236112f080e7Smrj sgl[cnt].dmac_size = 0; 236212f080e7Smrj sgl[cnt].dmac_type = 0; 236312f080e7Smrj } 236412f080e7Smrj } 236512f080e7Smrj 236612f080e7Smrj /* 236712f080e7Smrj * save this page's physical address so we can figure out if the next 236812f080e7Smrj * page is physically contiguous. Keep decrementing size until we are 236912f080e7Smrj * done with the buffer. 237012f080e7Smrj */ 2371843e1988Sjohnlev last_page = raddr & MMU_PAGEMASK; 237212f080e7Smrj size -= psize; 237312f080e7Smrj 237412f080e7Smrj while (size > 0) { 237512f080e7Smrj /* Get the size for this page (i.e. partial or full page) */ 237612f080e7Smrj psize = MIN(size, MMU_PAGESIZE); 237712f080e7Smrj 237812f080e7Smrj if (buftype == DMA_OTYP_PAGES) { 237912f080e7Smrj /* get the paddr from the page_t */ 238012f080e7Smrj ASSERT(!PP_ISFREE(pp) && PAGE_LOCKED(pp)); 2381843e1988Sjohnlev paddr = pfn_to_pa(pp->p_pagenum); 238212f080e7Smrj pp = pp->p_next; 238312f080e7Smrj } else if (pplist != NULL) { 238412f080e7Smrj /* index into the array of page_t's to get the paddr */ 238512f080e7Smrj ASSERT(!PP_ISFREE(pplist[pcnt])); 2386843e1988Sjohnlev paddr = pfn_to_pa(pplist[pcnt]->p_pagenum); 238712f080e7Smrj pcnt++; 238812f080e7Smrj } else { 238912f080e7Smrj /* call into the VM to get the paddr */ 2390843e1988Sjohnlev paddr = pfn_to_pa(hat_getpfnum(sglinfo->si_asp->a_hat, 239112f080e7Smrj vaddr)); 239212f080e7Smrj vaddr += psize; 239312f080e7Smrj } 239412f080e7Smrj 2395843e1988Sjohnlev #ifdef __xpv 2396843e1988Sjohnlev /* 2397843e1988Sjohnlev * If we're dom0, we're using a real device so we need to load 2398843e1988Sjohnlev * the cookies with MFNs instead of PFNs. 2399843e1988Sjohnlev */ 2400843e1988Sjohnlev raddr = ROOTNEX_PADDR_TO_RBASE(xen_info, paddr); 2401843e1988Sjohnlev #else 2402843e1988Sjohnlev raddr = paddr; 2403843e1988Sjohnlev #endif 2404843e1988Sjohnlev 240512f080e7Smrj /* check to see if this page needs the copy buffer */ 2406843e1988Sjohnlev if ((raddr < addrlo) || ((raddr + psize) > addrhi)) { 240712f080e7Smrj sglinfo->si_copybuf_req += MMU_PAGESIZE; 240812f080e7Smrj 240912f080e7Smrj /* 241012f080e7Smrj * if there is something in the current cookie, go to 241112f080e7Smrj * the next one. We only want one page in a cookie which 241212f080e7Smrj * uses the copybuf since the copybuf doesn't have to 241312f080e7Smrj * be physically contiguous. 241412f080e7Smrj */ 241512f080e7Smrj if (sgl[cnt].dmac_size != 0) { 241612f080e7Smrj cnt++; 241712f080e7Smrj } 2418843e1988Sjohnlev sgl[cnt].dmac_laddress = raddr; 241912f080e7Smrj sgl[cnt].dmac_size = psize; 242012f080e7Smrj #if defined(__amd64) 242112f080e7Smrj sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF; 242212f080e7Smrj #else 242312f080e7Smrj /* 242412f080e7Smrj * save the buf offset for 32-bit kernel. used in the 242512f080e7Smrj * obsoleted interfaces. 242612f080e7Smrj */ 242712f080e7Smrj sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF | 242812f080e7Smrj (dmar_object->dmao_size - size); 242912f080e7Smrj #endif 243012f080e7Smrj /* if this isn't the last cookie, go to the next one */ 243112f080e7Smrj if ((cnt + 1) < sglinfo->si_max_pages) { 243212f080e7Smrj cnt++; 243312f080e7Smrj sgl[cnt].dmac_laddress = 0; 243412f080e7Smrj sgl[cnt].dmac_size = 0; 243512f080e7Smrj sgl[cnt].dmac_type = 0; 243612f080e7Smrj } 243712f080e7Smrj 243812f080e7Smrj /* 243912f080e7Smrj * this page didn't need the copy buffer, if it's not physically 244012f080e7Smrj * contiguous, or it would put us over a segment boundary, or it 244112f080e7Smrj * puts us over the max cookie size, or the current sgl doesn't 244212f080e7Smrj * have anything in it. 244312f080e7Smrj */ 2444843e1988Sjohnlev } else if (((last_page + MMU_PAGESIZE) != raddr) || 2445843e1988Sjohnlev !(raddr & sglinfo->si_segmask) || 244612f080e7Smrj ((sgl[cnt].dmac_size + psize) > maxseg) || 244712f080e7Smrj (sgl[cnt].dmac_size == 0)) { 244812f080e7Smrj /* 244912f080e7Smrj * if we're not already in a new cookie, go to the next 245012f080e7Smrj * cookie. 245112f080e7Smrj */ 245212f080e7Smrj if (sgl[cnt].dmac_size != 0) { 245312f080e7Smrj cnt++; 245412f080e7Smrj } 245512f080e7Smrj 245612f080e7Smrj /* save the cookie information */ 2457843e1988Sjohnlev sgl[cnt].dmac_laddress = raddr; 245812f080e7Smrj sgl[cnt].dmac_size = psize; 245912f080e7Smrj #if defined(__amd64) 246012f080e7Smrj sgl[cnt].dmac_type = 0; 246112f080e7Smrj #else 246212f080e7Smrj /* 246312f080e7Smrj * save the buf offset for 32-bit kernel. used in the 246412f080e7Smrj * obsoleted interfaces. 246512f080e7Smrj */ 246612f080e7Smrj sgl[cnt].dmac_type = dmar_object->dmao_size - size; 246712f080e7Smrj #endif 246812f080e7Smrj 246912f080e7Smrj /* 247012f080e7Smrj * this page didn't need the copy buffer, it is physically 247112f080e7Smrj * contiguous with the last page, and it's <= the max cookie 247212f080e7Smrj * size. 247312f080e7Smrj */ 247412f080e7Smrj } else { 247512f080e7Smrj sgl[cnt].dmac_size += psize; 247612f080e7Smrj 247712f080e7Smrj /* 247812f080e7Smrj * if this exactly == the maximum cookie size, and 247912f080e7Smrj * it isn't the last cookie, go to the next cookie. 248012f080e7Smrj */ 248112f080e7Smrj if (((sgl[cnt].dmac_size + psize) == maxseg) && 248212f080e7Smrj ((cnt + 1) < sglinfo->si_max_pages)) { 248312f080e7Smrj cnt++; 248412f080e7Smrj sgl[cnt].dmac_laddress = 0; 248512f080e7Smrj sgl[cnt].dmac_size = 0; 248612f080e7Smrj sgl[cnt].dmac_type = 0; 248712f080e7Smrj } 248812f080e7Smrj } 248912f080e7Smrj 249012f080e7Smrj /* 249112f080e7Smrj * save this page's physical address so we can figure out if the 249212f080e7Smrj * next page is physically contiguous. Keep decrementing size 249312f080e7Smrj * until we are done with the buffer. 249412f080e7Smrj */ 2495843e1988Sjohnlev last_page = raddr; 249612f080e7Smrj size -= psize; 249712f080e7Smrj } 249812f080e7Smrj 249912f080e7Smrj /* we're done, save away how many cookies the sgl has */ 250012f080e7Smrj if (sgl[cnt].dmac_size == 0) { 250112f080e7Smrj ASSERT(cnt < sglinfo->si_max_pages); 250212f080e7Smrj sglinfo->si_sgl_size = cnt; 250312f080e7Smrj } else { 250412f080e7Smrj sglinfo->si_sgl_size = cnt + 1; 250512f080e7Smrj } 250612f080e7Smrj } 250712f080e7Smrj 250812f080e7Smrj 250912f080e7Smrj /* 251012f080e7Smrj * rootnex_bind_slowpath() 251112f080e7Smrj * Call in the bind path if the calling driver can't use the sgl without 251212f080e7Smrj * modifying it. We either need to use the copy buffer and/or we will end up 251312f080e7Smrj * with a partial bind. 251412f080e7Smrj */ 251512f080e7Smrj static int 251612f080e7Smrj rootnex_bind_slowpath(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq, 251712f080e7Smrj rootnex_dma_t *dma, ddi_dma_attr_t *attr, int kmflag) 251812f080e7Smrj { 251912f080e7Smrj rootnex_sglinfo_t *sinfo; 252012f080e7Smrj rootnex_window_t *window; 252112f080e7Smrj ddi_dma_cookie_t *cookie; 252212f080e7Smrj size_t copybuf_used; 252312f080e7Smrj size_t dmac_size; 252412f080e7Smrj boolean_t partial; 252512f080e7Smrj off_t cur_offset; 252612f080e7Smrj page_t *cur_pp; 252712f080e7Smrj major_t mnum; 252812f080e7Smrj int e; 252912f080e7Smrj int i; 253012f080e7Smrj 253112f080e7Smrj 253212f080e7Smrj sinfo = &dma->dp_sglinfo; 253312f080e7Smrj copybuf_used = 0; 253412f080e7Smrj partial = B_FALSE; 253512f080e7Smrj 253612f080e7Smrj /* 253712f080e7Smrj * If we're using the copybuf, set the copybuf state in dma struct. 253812f080e7Smrj * Needs to be first since it sets the copy buffer size. 253912f080e7Smrj */ 254012f080e7Smrj if (sinfo->si_copybuf_req != 0) { 254112f080e7Smrj e = rootnex_setup_copybuf(hp, dmareq, dma, attr); 254212f080e7Smrj if (e != DDI_SUCCESS) { 254312f080e7Smrj return (e); 254412f080e7Smrj } 254512f080e7Smrj } else { 254612f080e7Smrj dma->dp_copybuf_size = 0; 254712f080e7Smrj } 254812f080e7Smrj 254912f080e7Smrj /* 255012f080e7Smrj * Figure out if we need to do a partial mapping. If so, figure out 255112f080e7Smrj * if we need to trim the buffers when we munge the sgl. 255212f080e7Smrj */ 255312f080e7Smrj if ((dma->dp_copybuf_size < sinfo->si_copybuf_req) || 255412f080e7Smrj (dma->dp_dma.dmao_size > dma->dp_maxxfer) || 255512f080e7Smrj (attr->dma_attr_sgllen < sinfo->si_sgl_size)) { 255612f080e7Smrj dma->dp_partial_required = B_TRUE; 255712f080e7Smrj if (attr->dma_attr_granular != 1) { 255812f080e7Smrj dma->dp_trim_required = B_TRUE; 255912f080e7Smrj } 256012f080e7Smrj } else { 256112f080e7Smrj dma->dp_partial_required = B_FALSE; 256212f080e7Smrj dma->dp_trim_required = B_FALSE; 256312f080e7Smrj } 256412f080e7Smrj 256512f080e7Smrj /* If we need to do a partial bind, make sure the driver supports it */ 256612f080e7Smrj if (dma->dp_partial_required && 256712f080e7Smrj !(dmareq->dmar_flags & DDI_DMA_PARTIAL)) { 256812f080e7Smrj 256912f080e7Smrj mnum = ddi_driver_major(dma->dp_dip); 257012f080e7Smrj /* 257112f080e7Smrj * patchable which allows us to print one warning per major 257212f080e7Smrj * number. 257312f080e7Smrj */ 257412f080e7Smrj if ((rootnex_bind_warn) && 257512f080e7Smrj ((rootnex_warn_list[mnum] & ROOTNEX_BIND_WARNING) == 0)) { 257612f080e7Smrj rootnex_warn_list[mnum] |= ROOTNEX_BIND_WARNING; 257712f080e7Smrj cmn_err(CE_WARN, "!%s: coding error detected, the " 257812f080e7Smrj "driver is using ddi_dma_attr(9S) incorrectly. " 257912f080e7Smrj "There is a small risk of data corruption in " 258012f080e7Smrj "particular with large I/Os. The driver should be " 258112f080e7Smrj "replaced with a corrected version for proper " 258212f080e7Smrj "system operation. To disable this warning, add " 258312f080e7Smrj "'set rootnex:rootnex_bind_warn=0' to " 258412f080e7Smrj "/etc/system(4).", ddi_driver_name(dma->dp_dip)); 258512f080e7Smrj } 258612f080e7Smrj return (DDI_DMA_TOOBIG); 258712f080e7Smrj } 258812f080e7Smrj 258912f080e7Smrj /* 259012f080e7Smrj * we might need multiple windows, setup state to handle them. In this 259112f080e7Smrj * code path, we will have at least one window. 259212f080e7Smrj */ 259312f080e7Smrj e = rootnex_setup_windows(hp, dma, attr, kmflag); 259412f080e7Smrj if (e != DDI_SUCCESS) { 259512f080e7Smrj rootnex_teardown_copybuf(dma); 259612f080e7Smrj return (e); 259712f080e7Smrj } 259812f080e7Smrj 259912f080e7Smrj window = &dma->dp_window[0]; 260012f080e7Smrj cookie = &dma->dp_cookies[0]; 260112f080e7Smrj cur_offset = 0; 260212f080e7Smrj rootnex_init_win(hp, dma, window, cookie, cur_offset); 260312f080e7Smrj if (dmareq->dmar_object.dmao_type == DMA_OTYP_PAGES) { 260412f080e7Smrj cur_pp = dmareq->dmar_object.dmao_obj.pp_obj.pp_pp; 260512f080e7Smrj } 260612f080e7Smrj 260712f080e7Smrj /* loop though all the cookies we got back from get_sgl() */ 260812f080e7Smrj for (i = 0; i < sinfo->si_sgl_size; i++) { 260912f080e7Smrj /* 261012f080e7Smrj * If we're using the copy buffer, check this cookie and setup 261112f080e7Smrj * its associated copy buffer state. If this cookie uses the 261212f080e7Smrj * copy buffer, make sure we sync this window during dma_sync. 261312f080e7Smrj */ 261412f080e7Smrj if (dma->dp_copybuf_size > 0) { 261512f080e7Smrj rootnex_setup_cookie(&dmareq->dmar_object, dma, cookie, 261612f080e7Smrj cur_offset, ©buf_used, &cur_pp); 261712f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 261812f080e7Smrj window->wd_dosync = B_TRUE; 261912f080e7Smrj } 262012f080e7Smrj } 262112f080e7Smrj 262212f080e7Smrj /* 262312f080e7Smrj * save away the cookie size, since it could be modified in 262412f080e7Smrj * the windowing code. 262512f080e7Smrj */ 262612f080e7Smrj dmac_size = cookie->dmac_size; 262712f080e7Smrj 262812f080e7Smrj /* if we went over max copybuf size */ 262912f080e7Smrj if (dma->dp_copybuf_size && 263012f080e7Smrj (copybuf_used > dma->dp_copybuf_size)) { 263112f080e7Smrj partial = B_TRUE; 263212f080e7Smrj e = rootnex_copybuf_window_boundary(hp, dma, &window, 263312f080e7Smrj cookie, cur_offset, ©buf_used); 263412f080e7Smrj if (e != DDI_SUCCESS) { 263512f080e7Smrj rootnex_teardown_copybuf(dma); 263612f080e7Smrj rootnex_teardown_windows(dma); 263712f080e7Smrj return (e); 263812f080e7Smrj } 263912f080e7Smrj 264012f080e7Smrj /* 264112f080e7Smrj * if the coookie uses the copy buffer, make sure the 264212f080e7Smrj * new window we just moved to is set to sync. 264312f080e7Smrj */ 264412f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 264512f080e7Smrj window->wd_dosync = B_TRUE; 264612f080e7Smrj } 264712f080e7Smrj DTRACE_PROBE1(rootnex__copybuf__window, dev_info_t *, 264812f080e7Smrj dma->dp_dip); 264912f080e7Smrj 265012f080e7Smrj /* if the cookie cnt == max sgllen, move to the next window */ 265112f080e7Smrj } else if (window->wd_cookie_cnt >= attr->dma_attr_sgllen) { 265212f080e7Smrj partial = B_TRUE; 265312f080e7Smrj ASSERT(window->wd_cookie_cnt == attr->dma_attr_sgllen); 265412f080e7Smrj e = rootnex_sgllen_window_boundary(hp, dma, &window, 265512f080e7Smrj cookie, attr, cur_offset); 265612f080e7Smrj if (e != DDI_SUCCESS) { 265712f080e7Smrj rootnex_teardown_copybuf(dma); 265812f080e7Smrj rootnex_teardown_windows(dma); 265912f080e7Smrj return (e); 266012f080e7Smrj } 266112f080e7Smrj 266212f080e7Smrj /* 266312f080e7Smrj * if the coookie uses the copy buffer, make sure the 266412f080e7Smrj * new window we just moved to is set to sync. 266512f080e7Smrj */ 266612f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 266712f080e7Smrj window->wd_dosync = B_TRUE; 266812f080e7Smrj } 266912f080e7Smrj DTRACE_PROBE1(rootnex__sgllen__window, dev_info_t *, 267012f080e7Smrj dma->dp_dip); 267112f080e7Smrj 267212f080e7Smrj /* else if we will be over maxxfer */ 267312f080e7Smrj } else if ((window->wd_size + dmac_size) > 267412f080e7Smrj dma->dp_maxxfer) { 267512f080e7Smrj partial = B_TRUE; 267612f080e7Smrj e = rootnex_maxxfer_window_boundary(hp, dma, &window, 267712f080e7Smrj cookie); 267812f080e7Smrj if (e != DDI_SUCCESS) { 267912f080e7Smrj rootnex_teardown_copybuf(dma); 268012f080e7Smrj rootnex_teardown_windows(dma); 268112f080e7Smrj return (e); 268212f080e7Smrj } 268312f080e7Smrj 268412f080e7Smrj /* 268512f080e7Smrj * if the coookie uses the copy buffer, make sure the 268612f080e7Smrj * new window we just moved to is set to sync. 268712f080e7Smrj */ 268812f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 268912f080e7Smrj window->wd_dosync = B_TRUE; 269012f080e7Smrj } 269112f080e7Smrj DTRACE_PROBE1(rootnex__maxxfer__window, dev_info_t *, 269212f080e7Smrj dma->dp_dip); 269312f080e7Smrj 269412f080e7Smrj /* else this cookie fits in the current window */ 269512f080e7Smrj } else { 269612f080e7Smrj window->wd_cookie_cnt++; 269712f080e7Smrj window->wd_size += dmac_size; 269812f080e7Smrj } 269912f080e7Smrj 270012f080e7Smrj /* track our offset into the buffer, go to the next cookie */ 270112f080e7Smrj ASSERT(dmac_size <= dma->dp_dma.dmao_size); 270212f080e7Smrj ASSERT(cookie->dmac_size <= dmac_size); 270312f080e7Smrj cur_offset += dmac_size; 270412f080e7Smrj cookie++; 270512f080e7Smrj } 270612f080e7Smrj 270712f080e7Smrj /* if we ended up with a zero sized window in the end, clean it up */ 270812f080e7Smrj if (window->wd_size == 0) { 270912f080e7Smrj hp->dmai_nwin--; 271012f080e7Smrj window--; 271112f080e7Smrj } 271212f080e7Smrj 271312f080e7Smrj ASSERT(window->wd_trim.tr_trim_last == B_FALSE); 271412f080e7Smrj 271512f080e7Smrj if (!partial) { 271612f080e7Smrj return (DDI_DMA_MAPPED); 271712f080e7Smrj } 271812f080e7Smrj 271912f080e7Smrj ASSERT(dma->dp_partial_required); 272012f080e7Smrj return (DDI_DMA_PARTIAL_MAP); 272112f080e7Smrj } 272212f080e7Smrj 272312f080e7Smrj 272412f080e7Smrj /* 272512f080e7Smrj * rootnex_setup_copybuf() 272612f080e7Smrj * Called in bind slowpath. Figures out if we're going to use the copy 272712f080e7Smrj * buffer, and if we do, sets up the basic state to handle it. 272812f080e7Smrj */ 272912f080e7Smrj static int 273012f080e7Smrj rootnex_setup_copybuf(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq, 273112f080e7Smrj rootnex_dma_t *dma, ddi_dma_attr_t *attr) 273212f080e7Smrj { 273312f080e7Smrj rootnex_sglinfo_t *sinfo; 273412f080e7Smrj ddi_dma_attr_t lattr; 273512f080e7Smrj size_t max_copybuf; 273612f080e7Smrj int cansleep; 273712f080e7Smrj int e; 273812f080e7Smrj #if !defined(__amd64) 273912f080e7Smrj int vmflag; 274012f080e7Smrj #endif 274112f080e7Smrj 274212f080e7Smrj 274312f080e7Smrj sinfo = &dma->dp_sglinfo; 274412f080e7Smrj 274536945f79Smrj /* read this first so it's consistent through the routine */ 274636945f79Smrj max_copybuf = i_ddi_copybuf_size() & MMU_PAGEMASK; 274712f080e7Smrj 274812f080e7Smrj /* We need to call into the rootnex on ddi_dma_sync() */ 274912f080e7Smrj hp->dmai_rflags &= ~DMP_NOSYNC; 275012f080e7Smrj 275112f080e7Smrj /* make sure the copybuf size <= the max size */ 275212f080e7Smrj dma->dp_copybuf_size = MIN(sinfo->si_copybuf_req, max_copybuf); 275312f080e7Smrj ASSERT((dma->dp_copybuf_size & MMU_PAGEOFFSET) == 0); 275412f080e7Smrj 275512f080e7Smrj #if !defined(__amd64) 275612f080e7Smrj /* 275712f080e7Smrj * if we don't have kva space to copy to/from, allocate the KVA space 275812f080e7Smrj * now. We only do this for the 32-bit kernel. We use seg kpm space for 275912f080e7Smrj * the 64-bit kernel. 276012f080e7Smrj */ 276112f080e7Smrj if ((dmareq->dmar_object.dmao_type == DMA_OTYP_PAGES) || 276212f080e7Smrj (dmareq->dmar_object.dmao_obj.virt_obj.v_as != NULL)) { 276312f080e7Smrj 276412f080e7Smrj /* convert the sleep flags */ 276512f080e7Smrj if (dmareq->dmar_fp == DDI_DMA_SLEEP) { 276612f080e7Smrj vmflag = VM_SLEEP; 276712f080e7Smrj } else { 276812f080e7Smrj vmflag = VM_NOSLEEP; 276912f080e7Smrj } 277012f080e7Smrj 277112f080e7Smrj /* allocate Kernel VA space that we can bcopy to/from */ 277212f080e7Smrj dma->dp_kva = vmem_alloc(heap_arena, dma->dp_copybuf_size, 277312f080e7Smrj vmflag); 277412f080e7Smrj if (dma->dp_kva == NULL) { 277512f080e7Smrj return (DDI_DMA_NORESOURCES); 277612f080e7Smrj } 277712f080e7Smrj } 277812f080e7Smrj #endif 277912f080e7Smrj 278012f080e7Smrj /* convert the sleep flags */ 278112f080e7Smrj if (dmareq->dmar_fp == DDI_DMA_SLEEP) { 278212f080e7Smrj cansleep = 1; 278312f080e7Smrj } else { 278412f080e7Smrj cansleep = 0; 278512f080e7Smrj } 278612f080e7Smrj 278712f080e7Smrj /* 2788d21b39ddSmrj * Allocate the actual copy buffer. This needs to fit within the DMA 2789d21b39ddSmrj * engine limits, so we can't use kmem_alloc... We don't need 2790d21b39ddSmrj * contiguous memory (sgllen) since we will be forcing windows on 2791d21b39ddSmrj * sgllen anyway. 279212f080e7Smrj */ 279312f080e7Smrj lattr = *attr; 279412f080e7Smrj lattr.dma_attr_align = MMU_PAGESIZE; 2795d21b39ddSmrj /* 2796d21b39ddSmrj * this should be < 0 to indicate no limit, but due to a bug in 2797d21b39ddSmrj * the rootnex, we'll set it to the maximum positive int. 2798d21b39ddSmrj */ 2799d21b39ddSmrj lattr.dma_attr_sgllen = 0x7fffffff; 280012f080e7Smrj e = i_ddi_mem_alloc(dma->dp_dip, &lattr, dma->dp_copybuf_size, cansleep, 280112f080e7Smrj 0, NULL, &dma->dp_cbaddr, &dma->dp_cbsize, NULL); 280212f080e7Smrj if (e != DDI_SUCCESS) { 280312f080e7Smrj #if !defined(__amd64) 280412f080e7Smrj if (dma->dp_kva != NULL) { 280512f080e7Smrj vmem_free(heap_arena, dma->dp_kva, 280612f080e7Smrj dma->dp_copybuf_size); 280712f080e7Smrj } 280812f080e7Smrj #endif 280912f080e7Smrj return (DDI_DMA_NORESOURCES); 281012f080e7Smrj } 281112f080e7Smrj 281212f080e7Smrj DTRACE_PROBE2(rootnex__alloc__copybuf, dev_info_t *, dma->dp_dip, 281312f080e7Smrj size_t, dma->dp_copybuf_size); 281412f080e7Smrj 281512f080e7Smrj return (DDI_SUCCESS); 281612f080e7Smrj } 281712f080e7Smrj 281812f080e7Smrj 281912f080e7Smrj /* 282012f080e7Smrj * rootnex_setup_windows() 282112f080e7Smrj * Called in bind slowpath to setup the window state. We always have windows 282212f080e7Smrj * in the slowpath. Even if the window count = 1. 282312f080e7Smrj */ 282412f080e7Smrj static int 282512f080e7Smrj rootnex_setup_windows(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 282612f080e7Smrj ddi_dma_attr_t *attr, int kmflag) 282712f080e7Smrj { 282812f080e7Smrj rootnex_window_t *windowp; 282912f080e7Smrj rootnex_sglinfo_t *sinfo; 283012f080e7Smrj size_t copy_state_size; 283112f080e7Smrj size_t win_state_size; 283212f080e7Smrj size_t state_available; 283312f080e7Smrj size_t space_needed; 283412f080e7Smrj uint_t copybuf_win; 283512f080e7Smrj uint_t maxxfer_win; 283612f080e7Smrj size_t space_used; 283712f080e7Smrj uint_t sglwin; 283812f080e7Smrj 283912f080e7Smrj 284012f080e7Smrj sinfo = &dma->dp_sglinfo; 284112f080e7Smrj 284212f080e7Smrj dma->dp_current_win = 0; 284312f080e7Smrj hp->dmai_nwin = 0; 284412f080e7Smrj 284512f080e7Smrj /* If we don't need to do a partial, we only have one window */ 284612f080e7Smrj if (!dma->dp_partial_required) { 284712f080e7Smrj dma->dp_max_win = 1; 284812f080e7Smrj 284912f080e7Smrj /* 285012f080e7Smrj * we need multiple windows, need to figure out the worse case number 285112f080e7Smrj * of windows. 285212f080e7Smrj */ 28537c478bd9Sstevel@tonic-gate } else { 28547c478bd9Sstevel@tonic-gate /* 285512f080e7Smrj * if we need windows because we need more copy buffer that 285612f080e7Smrj * we allow, the worse case number of windows we could need 285712f080e7Smrj * here would be (copybuf space required / copybuf space that 285812f080e7Smrj * we have) plus one for remainder, and plus 2 to handle the 285912f080e7Smrj * extra pages on the trim for the first and last pages of the 286012f080e7Smrj * buffer (a page is the minimum window size so under the right 286112f080e7Smrj * attr settings, you could have a window for each page). 286212f080e7Smrj * The last page will only be hit here if the size is not a 286312f080e7Smrj * multiple of the granularity (which theoretically shouldn't 286412f080e7Smrj * be the case but never has been enforced, so we could have 286512f080e7Smrj * broken things without it). 28667c478bd9Sstevel@tonic-gate */ 286712f080e7Smrj if (sinfo->si_copybuf_req > dma->dp_copybuf_size) { 286812f080e7Smrj ASSERT(dma->dp_copybuf_size > 0); 286912f080e7Smrj copybuf_win = (sinfo->si_copybuf_req / 287012f080e7Smrj dma->dp_copybuf_size) + 1 + 2; 28717c478bd9Sstevel@tonic-gate } else { 287212f080e7Smrj copybuf_win = 0; 28737c478bd9Sstevel@tonic-gate } 287412f080e7Smrj 287512f080e7Smrj /* 287612f080e7Smrj * if we need windows because we have more cookies than the H/W 287712f080e7Smrj * can handle, the number of windows we would need here would 287812f080e7Smrj * be (cookie count / cookies count H/W supports) plus one for 287912f080e7Smrj * remainder, and plus 2 to handle the extra pages on the trim 288012f080e7Smrj * (see above comment about trim) 288112f080e7Smrj */ 288212f080e7Smrj if (attr->dma_attr_sgllen < sinfo->si_sgl_size) { 288312f080e7Smrj sglwin = ((sinfo->si_sgl_size / attr->dma_attr_sgllen) 288412f080e7Smrj + 1) + 2; 28857c478bd9Sstevel@tonic-gate } else { 288612f080e7Smrj sglwin = 0; 28877c478bd9Sstevel@tonic-gate } 288812f080e7Smrj 288912f080e7Smrj /* 289012f080e7Smrj * if we need windows because we're binding more memory than the 289112f080e7Smrj * H/W can transfer at once, the number of windows we would need 289212f080e7Smrj * here would be (xfer count / max xfer H/W supports) plus one 289312f080e7Smrj * for remainder, and plus 2 to handle the extra pages on the 289412f080e7Smrj * trim (see above comment about trim) 289512f080e7Smrj */ 289612f080e7Smrj if (dma->dp_dma.dmao_size > dma->dp_maxxfer) { 289712f080e7Smrj maxxfer_win = (dma->dp_dma.dmao_size / 289812f080e7Smrj dma->dp_maxxfer) + 1 + 2; 289912f080e7Smrj } else { 290012f080e7Smrj maxxfer_win = 0; 29017c478bd9Sstevel@tonic-gate } 290212f080e7Smrj dma->dp_max_win = copybuf_win + sglwin + maxxfer_win; 290312f080e7Smrj ASSERT(dma->dp_max_win > 0); 290412f080e7Smrj } 290512f080e7Smrj win_state_size = dma->dp_max_win * sizeof (rootnex_window_t); 290612f080e7Smrj 290712f080e7Smrj /* 290812f080e7Smrj * Get space for window and potential copy buffer state. Before we 290912f080e7Smrj * go and allocate memory, see if we can get away with using what's 291012f080e7Smrj * left in the pre-allocted state or the dynamically allocated sgl. 291112f080e7Smrj */ 291212f080e7Smrj space_used = (uintptr_t)(sinfo->si_sgl_size * 291312f080e7Smrj sizeof (ddi_dma_cookie_t)); 291412f080e7Smrj 291512f080e7Smrj /* if we dynamically allocated space for the cookies */ 291612f080e7Smrj if (dma->dp_need_to_free_cookie) { 291712f080e7Smrj /* if we have more space in the pre-allocted buffer, use it */ 291812f080e7Smrj ASSERT(space_used <= dma->dp_cookie_size); 291912f080e7Smrj if ((dma->dp_cookie_size - space_used) <= 292012f080e7Smrj rootnex_state->r_prealloc_size) { 292112f080e7Smrj state_available = rootnex_state->r_prealloc_size; 292212f080e7Smrj windowp = (rootnex_window_t *)dma->dp_prealloc_buffer; 292312f080e7Smrj 292412f080e7Smrj /* 292512f080e7Smrj * else, we have more free space in the dynamically allocated 292612f080e7Smrj * buffer, i.e. the buffer wasn't worse case fragmented so we 292712f080e7Smrj * didn't need a lot of cookies. 292812f080e7Smrj */ 292912f080e7Smrj } else { 293012f080e7Smrj state_available = dma->dp_cookie_size - space_used; 293112f080e7Smrj windowp = (rootnex_window_t *) 293212f080e7Smrj &dma->dp_cookies[sinfo->si_sgl_size]; 293312f080e7Smrj } 293412f080e7Smrj 293512f080e7Smrj /* we used the pre-alloced buffer */ 293612f080e7Smrj } else { 293712f080e7Smrj ASSERT(space_used <= rootnex_state->r_prealloc_size); 293812f080e7Smrj state_available = rootnex_state->r_prealloc_size - space_used; 293912f080e7Smrj windowp = (rootnex_window_t *) 294012f080e7Smrj &dma->dp_cookies[sinfo->si_sgl_size]; 294112f080e7Smrj } 294212f080e7Smrj 294312f080e7Smrj /* 294412f080e7Smrj * figure out how much state we need to track the copy buffer. Add an 294512f080e7Smrj * addition 8 bytes for pointer alignemnt later. 294612f080e7Smrj */ 294712f080e7Smrj if (dma->dp_copybuf_size > 0) { 294812f080e7Smrj copy_state_size = sinfo->si_max_pages * 294912f080e7Smrj sizeof (rootnex_pgmap_t); 295012f080e7Smrj } else { 295112f080e7Smrj copy_state_size = 0; 295212f080e7Smrj } 295312f080e7Smrj /* add an additional 8 bytes for pointer alignment */ 295412f080e7Smrj space_needed = win_state_size + copy_state_size + 0x8; 295512f080e7Smrj 295612f080e7Smrj /* if we have enough space already, use it */ 295712f080e7Smrj if (state_available >= space_needed) { 295812f080e7Smrj dma->dp_window = windowp; 295912f080e7Smrj dma->dp_need_to_free_window = B_FALSE; 296012f080e7Smrj 296112f080e7Smrj /* not enough space, need to allocate more. */ 296212f080e7Smrj } else { 296312f080e7Smrj dma->dp_window = kmem_alloc(space_needed, kmflag); 296412f080e7Smrj if (dma->dp_window == NULL) { 296512f080e7Smrj return (DDI_DMA_NORESOURCES); 296612f080e7Smrj } 296712f080e7Smrj dma->dp_need_to_free_window = B_TRUE; 296812f080e7Smrj dma->dp_window_size = space_needed; 296912f080e7Smrj DTRACE_PROBE2(rootnex__bind__sp__alloc, dev_info_t *, 297012f080e7Smrj dma->dp_dip, size_t, space_needed); 297112f080e7Smrj } 297212f080e7Smrj 297312f080e7Smrj /* 297412f080e7Smrj * we allocate copy buffer state and window state at the same time. 297512f080e7Smrj * setup our copy buffer state pointers. Make sure it's aligned. 297612f080e7Smrj */ 297712f080e7Smrj if (dma->dp_copybuf_size > 0) { 297812f080e7Smrj dma->dp_pgmap = (rootnex_pgmap_t *)(((uintptr_t) 297912f080e7Smrj &dma->dp_window[dma->dp_max_win] + 0x7) & ~0x7); 298012f080e7Smrj 298112f080e7Smrj #if !defined(__amd64) 298212f080e7Smrj /* 298312f080e7Smrj * make sure all pm_mapped, pm_vaddr, and pm_pp are set to 298412f080e7Smrj * false/NULL. Should be quicker to bzero vs loop and set. 298512f080e7Smrj */ 298612f080e7Smrj bzero(dma->dp_pgmap, copy_state_size); 298712f080e7Smrj #endif 298812f080e7Smrj } else { 298912f080e7Smrj dma->dp_pgmap = NULL; 299012f080e7Smrj } 299112f080e7Smrj 299212f080e7Smrj return (DDI_SUCCESS); 299312f080e7Smrj } 299412f080e7Smrj 299512f080e7Smrj 299612f080e7Smrj /* 299712f080e7Smrj * rootnex_teardown_copybuf() 299812f080e7Smrj * cleans up after rootnex_setup_copybuf() 299912f080e7Smrj */ 300012f080e7Smrj static void 300112f080e7Smrj rootnex_teardown_copybuf(rootnex_dma_t *dma) 300212f080e7Smrj { 300312f080e7Smrj #if !defined(__amd64) 300412f080e7Smrj int i; 300512f080e7Smrj 300612f080e7Smrj /* 300712f080e7Smrj * if we allocated kernel heap VMEM space, go through all the pages and 300812f080e7Smrj * map out any of the ones that we're mapped into the kernel heap VMEM 300912f080e7Smrj * arena. Then free the VMEM space. 301012f080e7Smrj */ 301112f080e7Smrj if (dma->dp_kva != NULL) { 301212f080e7Smrj for (i = 0; i < dma->dp_sglinfo.si_max_pages; i++) { 301312f080e7Smrj if (dma->dp_pgmap[i].pm_mapped) { 301412f080e7Smrj hat_unload(kas.a_hat, dma->dp_pgmap[i].pm_kaddr, 301512f080e7Smrj MMU_PAGESIZE, HAT_UNLOAD); 301612f080e7Smrj dma->dp_pgmap[i].pm_mapped = B_FALSE; 301712f080e7Smrj } 301812f080e7Smrj } 301912f080e7Smrj 302012f080e7Smrj vmem_free(heap_arena, dma->dp_kva, dma->dp_copybuf_size); 302112f080e7Smrj } 302212f080e7Smrj 302312f080e7Smrj #endif 302412f080e7Smrj 302512f080e7Smrj /* if we allocated a copy buffer, free it */ 302612f080e7Smrj if (dma->dp_cbaddr != NULL) { 30277b93957cSeota i_ddi_mem_free(dma->dp_cbaddr, NULL); 302812f080e7Smrj } 302912f080e7Smrj } 303012f080e7Smrj 303112f080e7Smrj 303212f080e7Smrj /* 303312f080e7Smrj * rootnex_teardown_windows() 303412f080e7Smrj * cleans up after rootnex_setup_windows() 303512f080e7Smrj */ 303612f080e7Smrj static void 303712f080e7Smrj rootnex_teardown_windows(rootnex_dma_t *dma) 303812f080e7Smrj { 303912f080e7Smrj /* 304012f080e7Smrj * if we had to allocate window state on the last bind (because we 304112f080e7Smrj * didn't have enough pre-allocated space in the handle), free it. 304212f080e7Smrj */ 304312f080e7Smrj if (dma->dp_need_to_free_window) { 304412f080e7Smrj kmem_free(dma->dp_window, dma->dp_window_size); 304512f080e7Smrj } 304612f080e7Smrj } 304712f080e7Smrj 304812f080e7Smrj 304912f080e7Smrj /* 305012f080e7Smrj * rootnex_init_win() 305112f080e7Smrj * Called in bind slow path during creation of a new window. Initializes 305212f080e7Smrj * window state to default values. 305312f080e7Smrj */ 305412f080e7Smrj /*ARGSUSED*/ 305512f080e7Smrj static void 305612f080e7Smrj rootnex_init_win(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 305712f080e7Smrj rootnex_window_t *window, ddi_dma_cookie_t *cookie, off_t cur_offset) 305812f080e7Smrj { 305912f080e7Smrj hp->dmai_nwin++; 306012f080e7Smrj window->wd_dosync = B_FALSE; 306112f080e7Smrj window->wd_offset = cur_offset; 306212f080e7Smrj window->wd_size = 0; 306312f080e7Smrj window->wd_first_cookie = cookie; 306412f080e7Smrj window->wd_cookie_cnt = 0; 306512f080e7Smrj window->wd_trim.tr_trim_first = B_FALSE; 306612f080e7Smrj window->wd_trim.tr_trim_last = B_FALSE; 306712f080e7Smrj window->wd_trim.tr_first_copybuf_win = B_FALSE; 306812f080e7Smrj window->wd_trim.tr_last_copybuf_win = B_FALSE; 306912f080e7Smrj #if !defined(__amd64) 307012f080e7Smrj window->wd_remap_copybuf = dma->dp_cb_remaping; 307112f080e7Smrj #endif 307212f080e7Smrj } 307312f080e7Smrj 307412f080e7Smrj 307512f080e7Smrj /* 307612f080e7Smrj * rootnex_setup_cookie() 307712f080e7Smrj * Called in the bind slow path when the sgl uses the copy buffer. If any of 307812f080e7Smrj * the sgl uses the copy buffer, we need to go through each cookie, figure 307912f080e7Smrj * out if it uses the copy buffer, and if it does, save away everything we'll 308012f080e7Smrj * need during sync. 308112f080e7Smrj */ 308212f080e7Smrj static void 308312f080e7Smrj rootnex_setup_cookie(ddi_dma_obj_t *dmar_object, rootnex_dma_t *dma, 308412f080e7Smrj ddi_dma_cookie_t *cookie, off_t cur_offset, size_t *copybuf_used, 308512f080e7Smrj page_t **cur_pp) 308612f080e7Smrj { 308712f080e7Smrj boolean_t copybuf_sz_power_2; 308812f080e7Smrj rootnex_sglinfo_t *sinfo; 3089843e1988Sjohnlev paddr_t paddr; 309012f080e7Smrj uint_t pidx; 309112f080e7Smrj uint_t pcnt; 309212f080e7Smrj off_t poff; 309312f080e7Smrj #if defined(__amd64) 309412f080e7Smrj pfn_t pfn; 309512f080e7Smrj #else 309612f080e7Smrj page_t **pplist; 309712f080e7Smrj #endif 309812f080e7Smrj 309912f080e7Smrj sinfo = &dma->dp_sglinfo; 310012f080e7Smrj 310112f080e7Smrj /* 310212f080e7Smrj * Calculate the page index relative to the start of the buffer. The 310312f080e7Smrj * index to the current page for our buffer is the offset into the 310412f080e7Smrj * first page of the buffer plus our current offset into the buffer 310512f080e7Smrj * itself, shifted of course... 310612f080e7Smrj */ 310712f080e7Smrj pidx = (sinfo->si_buf_offset + cur_offset) >> MMU_PAGESHIFT; 310812f080e7Smrj ASSERT(pidx < sinfo->si_max_pages); 310912f080e7Smrj 311012f080e7Smrj /* if this cookie uses the copy buffer */ 311112f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 311212f080e7Smrj /* 311312f080e7Smrj * NOTE: we know that since this cookie uses the copy buffer, it 311412f080e7Smrj * is <= MMU_PAGESIZE. 311512f080e7Smrj */ 311612f080e7Smrj 311712f080e7Smrj /* 311812f080e7Smrj * get the offset into the page. For the 64-bit kernel, get the 311912f080e7Smrj * pfn which we'll use with seg kpm. 312012f080e7Smrj */ 3121843e1988Sjohnlev poff = cookie->dmac_laddress & MMU_PAGEOFFSET; 312212f080e7Smrj #if defined(__amd64) 3123843e1988Sjohnlev /* mfn_to_pfn() is a NOP on i86pc */ 3124843e1988Sjohnlev pfn = mfn_to_pfn(cookie->dmac_laddress >> MMU_PAGESHIFT); 3125843e1988Sjohnlev #endif /* __amd64 */ 312612f080e7Smrj 312712f080e7Smrj /* figure out if the copybuf size is a power of 2 */ 312812f080e7Smrj if (dma->dp_copybuf_size & (dma->dp_copybuf_size - 1)) { 312912f080e7Smrj copybuf_sz_power_2 = B_FALSE; 313012f080e7Smrj } else { 313112f080e7Smrj copybuf_sz_power_2 = B_TRUE; 313212f080e7Smrj } 313312f080e7Smrj 313412f080e7Smrj /* This page uses the copy buffer */ 313512f080e7Smrj dma->dp_pgmap[pidx].pm_uses_copybuf = B_TRUE; 313612f080e7Smrj 313712f080e7Smrj /* 313812f080e7Smrj * save the copy buffer KVA that we'll use with this page. 313912f080e7Smrj * if we still fit within the copybuf, it's a simple add. 314012f080e7Smrj * otherwise, we need to wrap over using & or % accordingly. 314112f080e7Smrj */ 314212f080e7Smrj if ((*copybuf_used + MMU_PAGESIZE) <= dma->dp_copybuf_size) { 314312f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr = dma->dp_cbaddr + 314412f080e7Smrj *copybuf_used; 314512f080e7Smrj } else { 314612f080e7Smrj if (copybuf_sz_power_2) { 314712f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr = (caddr_t)( 314812f080e7Smrj (uintptr_t)dma->dp_cbaddr + 314912f080e7Smrj (*copybuf_used & 315012f080e7Smrj (dma->dp_copybuf_size - 1))); 315112f080e7Smrj } else { 315212f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr = (caddr_t)( 315312f080e7Smrj (uintptr_t)dma->dp_cbaddr + 315412f080e7Smrj (*copybuf_used % dma->dp_copybuf_size)); 315512f080e7Smrj } 315612f080e7Smrj } 315712f080e7Smrj 315812f080e7Smrj /* 315912f080e7Smrj * over write the cookie physical address with the address of 316012f080e7Smrj * the physical address of the copy buffer page that we will 316112f080e7Smrj * use. 316212f080e7Smrj */ 3163843e1988Sjohnlev paddr = pfn_to_pa(hat_getpfnum(kas.a_hat, 316412f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr)) + poff; 316512f080e7Smrj 3166843e1988Sjohnlev #ifdef __xpv 3167843e1988Sjohnlev /* 3168843e1988Sjohnlev * If we're dom0, we're using a real device so we need to load 3169843e1988Sjohnlev * the cookies with MAs instead of PAs. 3170843e1988Sjohnlev */ 3171843e1988Sjohnlev cookie->dmac_laddress = ROOTNEX_PADDR_TO_RBASE(xen_info, paddr); 3172843e1988Sjohnlev #else 3173843e1988Sjohnlev cookie->dmac_laddress = paddr; 3174843e1988Sjohnlev #endif 3175843e1988Sjohnlev 317612f080e7Smrj /* if we have a kernel VA, it's easy, just save that address */ 317712f080e7Smrj if ((dmar_object->dmao_type != DMA_OTYP_PAGES) && 317812f080e7Smrj (sinfo->si_asp == &kas)) { 317912f080e7Smrj /* 318012f080e7Smrj * save away the page aligned virtual address of the 318112f080e7Smrj * driver buffer. Offsets are handled in the sync code. 318212f080e7Smrj */ 318312f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = (caddr_t)(((uintptr_t) 318412f080e7Smrj dmar_object->dmao_obj.virt_obj.v_addr + cur_offset) 318512f080e7Smrj & MMU_PAGEMASK); 318612f080e7Smrj #if !defined(__amd64) 318712f080e7Smrj /* 318812f080e7Smrj * we didn't need to, and will never need to map this 318912f080e7Smrj * page. 319012f080e7Smrj */ 319112f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_FALSE; 319212f080e7Smrj #endif 319312f080e7Smrj 319412f080e7Smrj /* we don't have a kernel VA. We need one for the bcopy. */ 319512f080e7Smrj } else { 319612f080e7Smrj #if defined(__amd64) 319712f080e7Smrj /* 319812f080e7Smrj * for the 64-bit kernel, it's easy. We use seg kpm to 319912f080e7Smrj * get a Kernel VA for the corresponding pfn. 320012f080e7Smrj */ 320112f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = hat_kpm_pfn2va(pfn); 320212f080e7Smrj #else 320312f080e7Smrj /* 320412f080e7Smrj * for the 32-bit kernel, this is a pain. First we'll 320512f080e7Smrj * save away the page_t or user VA for this page. This 320612f080e7Smrj * is needed in rootnex_dma_win() when we switch to a 320712f080e7Smrj * new window which requires us to re-map the copy 320812f080e7Smrj * buffer. 320912f080e7Smrj */ 321012f080e7Smrj pplist = dmar_object->dmao_obj.virt_obj.v_priv; 321112f080e7Smrj if (dmar_object->dmao_type == DMA_OTYP_PAGES) { 321212f080e7Smrj dma->dp_pgmap[pidx].pm_pp = *cur_pp; 321312f080e7Smrj dma->dp_pgmap[pidx].pm_vaddr = NULL; 321412f080e7Smrj } else if (pplist != NULL) { 321512f080e7Smrj dma->dp_pgmap[pidx].pm_pp = pplist[pidx]; 321612f080e7Smrj dma->dp_pgmap[pidx].pm_vaddr = NULL; 321712f080e7Smrj } else { 321812f080e7Smrj dma->dp_pgmap[pidx].pm_pp = NULL; 321912f080e7Smrj dma->dp_pgmap[pidx].pm_vaddr = (caddr_t) 322012f080e7Smrj (((uintptr_t) 322112f080e7Smrj dmar_object->dmao_obj.virt_obj.v_addr + 322212f080e7Smrj cur_offset) & MMU_PAGEMASK); 322312f080e7Smrj } 322412f080e7Smrj 322512f080e7Smrj /* 322612f080e7Smrj * save away the page aligned virtual address which was 322712f080e7Smrj * allocated from the kernel heap arena (taking into 322812f080e7Smrj * account if we need more copy buffer than we alloced 322912f080e7Smrj * and use multiple windows to handle this, i.e. &,%). 323012f080e7Smrj * NOTE: there isn't and physical memory backing up this 323112f080e7Smrj * virtual address space currently. 323212f080e7Smrj */ 323312f080e7Smrj if ((*copybuf_used + MMU_PAGESIZE) <= 323412f080e7Smrj dma->dp_copybuf_size) { 323512f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = (caddr_t) 323612f080e7Smrj (((uintptr_t)dma->dp_kva + *copybuf_used) & 323712f080e7Smrj MMU_PAGEMASK); 323812f080e7Smrj } else { 323912f080e7Smrj if (copybuf_sz_power_2) { 324012f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = (caddr_t) 324112f080e7Smrj (((uintptr_t)dma->dp_kva + 324212f080e7Smrj (*copybuf_used & 324312f080e7Smrj (dma->dp_copybuf_size - 1))) & 324412f080e7Smrj MMU_PAGEMASK); 324512f080e7Smrj } else { 324612f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = (caddr_t) 324712f080e7Smrj (((uintptr_t)dma->dp_kva + 324812f080e7Smrj (*copybuf_used % 324912f080e7Smrj dma->dp_copybuf_size)) & 325012f080e7Smrj MMU_PAGEMASK); 325112f080e7Smrj } 325212f080e7Smrj } 325312f080e7Smrj 325412f080e7Smrj /* 325512f080e7Smrj * if we haven't used up the available copy buffer yet, 325612f080e7Smrj * map the kva to the physical page. 325712f080e7Smrj */ 325812f080e7Smrj if (!dma->dp_cb_remaping && ((*copybuf_used + 325912f080e7Smrj MMU_PAGESIZE) <= dma->dp_copybuf_size)) { 326012f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_TRUE; 326112f080e7Smrj if (dma->dp_pgmap[pidx].pm_pp != NULL) { 326212f080e7Smrj i86_pp_map(dma->dp_pgmap[pidx].pm_pp, 326312f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr); 326412f080e7Smrj } else { 326512f080e7Smrj i86_va_map(dma->dp_pgmap[pidx].pm_vaddr, 326612f080e7Smrj sinfo->si_asp, 326712f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr); 326812f080e7Smrj } 326912f080e7Smrj 327012f080e7Smrj /* 327112f080e7Smrj * we've used up the available copy buffer, this page 327212f080e7Smrj * will have to be mapped during rootnex_dma_win() when 327312f080e7Smrj * we switch to a new window which requires a re-map 327412f080e7Smrj * the copy buffer. (32-bit kernel only) 327512f080e7Smrj */ 327612f080e7Smrj } else { 327712f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_FALSE; 327812f080e7Smrj } 327912f080e7Smrj #endif 328012f080e7Smrj /* go to the next page_t */ 328112f080e7Smrj if (dmar_object->dmao_type == DMA_OTYP_PAGES) { 328212f080e7Smrj *cur_pp = (*cur_pp)->p_next; 328312f080e7Smrj } 328412f080e7Smrj } 328512f080e7Smrj 328612f080e7Smrj /* add to the copy buffer count */ 328712f080e7Smrj *copybuf_used += MMU_PAGESIZE; 328812f080e7Smrj 328912f080e7Smrj /* 329012f080e7Smrj * This cookie doesn't use the copy buffer. Walk through the pages this 329112f080e7Smrj * cookie occupies to reflect this. 329212f080e7Smrj */ 329312f080e7Smrj } else { 329412f080e7Smrj /* 329512f080e7Smrj * figure out how many pages the cookie occupies. We need to 329612f080e7Smrj * use the original page offset of the buffer and the cookies 329712f080e7Smrj * offset in the buffer to do this. 329812f080e7Smrj */ 329912f080e7Smrj poff = (sinfo->si_buf_offset + cur_offset) & MMU_PAGEOFFSET; 330012f080e7Smrj pcnt = mmu_btopr(cookie->dmac_size + poff); 330112f080e7Smrj 330212f080e7Smrj while (pcnt > 0) { 330312f080e7Smrj #if !defined(__amd64) 330412f080e7Smrj /* 330512f080e7Smrj * the 32-bit kernel doesn't have seg kpm, so we need 330612f080e7Smrj * to map in the driver buffer (if it didn't come down 330712f080e7Smrj * with a kernel VA) on the fly. Since this page doesn't 330812f080e7Smrj * use the copy buffer, it's not, or will it ever, have 330912f080e7Smrj * to be mapped in. 331012f080e7Smrj */ 331112f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_FALSE; 331212f080e7Smrj #endif 331312f080e7Smrj dma->dp_pgmap[pidx].pm_uses_copybuf = B_FALSE; 331412f080e7Smrj 331512f080e7Smrj /* 331612f080e7Smrj * we need to update pidx and cur_pp or we'll loose 331712f080e7Smrj * track of where we are. 331812f080e7Smrj */ 331912f080e7Smrj if (dmar_object->dmao_type == DMA_OTYP_PAGES) { 332012f080e7Smrj *cur_pp = (*cur_pp)->p_next; 332112f080e7Smrj } 332212f080e7Smrj pidx++; 332312f080e7Smrj pcnt--; 332412f080e7Smrj } 332512f080e7Smrj } 332612f080e7Smrj } 332712f080e7Smrj 332812f080e7Smrj 332912f080e7Smrj /* 333012f080e7Smrj * rootnex_sgllen_window_boundary() 333112f080e7Smrj * Called in the bind slow path when the next cookie causes us to exceed (in 333212f080e7Smrj * this case == since we start at 0 and sgllen starts at 1) the maximum sgl 333312f080e7Smrj * length supported by the DMA H/W. 333412f080e7Smrj */ 333512f080e7Smrj static int 333612f080e7Smrj rootnex_sgllen_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 333712f080e7Smrj rootnex_window_t **windowp, ddi_dma_cookie_t *cookie, ddi_dma_attr_t *attr, 333812f080e7Smrj off_t cur_offset) 333912f080e7Smrj { 334012f080e7Smrj off_t new_offset; 334112f080e7Smrj size_t trim_sz; 334212f080e7Smrj off_t coffset; 334312f080e7Smrj 334412f080e7Smrj 334512f080e7Smrj /* 334612f080e7Smrj * if we know we'll never have to trim, it's pretty easy. Just move to 334712f080e7Smrj * the next window and init it. We're done. 334812f080e7Smrj */ 334912f080e7Smrj if (!dma->dp_trim_required) { 335012f080e7Smrj (*windowp)++; 335112f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, cur_offset); 335212f080e7Smrj (*windowp)->wd_cookie_cnt++; 335312f080e7Smrj (*windowp)->wd_size = cookie->dmac_size; 335412f080e7Smrj return (DDI_SUCCESS); 335512f080e7Smrj } 335612f080e7Smrj 335712f080e7Smrj /* figure out how much we need to trim from the window */ 335812f080e7Smrj ASSERT(attr->dma_attr_granular != 0); 335912f080e7Smrj if (dma->dp_granularity_power_2) { 336012f080e7Smrj trim_sz = (*windowp)->wd_size & (attr->dma_attr_granular - 1); 336112f080e7Smrj } else { 336212f080e7Smrj trim_sz = (*windowp)->wd_size % attr->dma_attr_granular; 336312f080e7Smrj } 336412f080e7Smrj 336512f080e7Smrj /* The window's a whole multiple of granularity. We're done */ 336612f080e7Smrj if (trim_sz == 0) { 336712f080e7Smrj (*windowp)++; 336812f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, cur_offset); 336912f080e7Smrj (*windowp)->wd_cookie_cnt++; 337012f080e7Smrj (*windowp)->wd_size = cookie->dmac_size; 337112f080e7Smrj return (DDI_SUCCESS); 337212f080e7Smrj } 337312f080e7Smrj 337412f080e7Smrj /* 337512f080e7Smrj * The window's not a whole multiple of granularity, since we know this 337612f080e7Smrj * is due to the sgllen, we need to go back to the last cookie and trim 337712f080e7Smrj * that one, add the left over part of the old cookie into the new 337812f080e7Smrj * window, and then add in the new cookie into the new window. 337912f080e7Smrj */ 338012f080e7Smrj 338112f080e7Smrj /* 338212f080e7Smrj * make sure the driver isn't making us do something bad... Trimming and 338312f080e7Smrj * sgllen == 1 don't go together. 338412f080e7Smrj */ 338512f080e7Smrj if (attr->dma_attr_sgllen == 1) { 338612f080e7Smrj return (DDI_DMA_NOMAPPING); 338712f080e7Smrj } 338812f080e7Smrj 338912f080e7Smrj /* 339012f080e7Smrj * first, setup the current window to account for the trim. Need to go 339112f080e7Smrj * back to the last cookie for this. 339212f080e7Smrj */ 339312f080e7Smrj cookie--; 339412f080e7Smrj (*windowp)->wd_trim.tr_trim_last = B_TRUE; 339512f080e7Smrj (*windowp)->wd_trim.tr_last_cookie = cookie; 3396843e1988Sjohnlev (*windowp)->wd_trim.tr_last_paddr = cookie->dmac_laddress; 339712f080e7Smrj ASSERT(cookie->dmac_size > trim_sz); 339812f080e7Smrj (*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz; 339912f080e7Smrj (*windowp)->wd_size -= trim_sz; 340012f080e7Smrj 340112f080e7Smrj /* save the buffer offsets for the next window */ 340212f080e7Smrj coffset = cookie->dmac_size - trim_sz; 340312f080e7Smrj new_offset = (*windowp)->wd_offset + (*windowp)->wd_size; 340412f080e7Smrj 340512f080e7Smrj /* 340612f080e7Smrj * set this now in case this is the first window. all other cases are 340712f080e7Smrj * set in dma_win() 340812f080e7Smrj */ 340912f080e7Smrj cookie->dmac_size = (*windowp)->wd_trim.tr_last_size; 341012f080e7Smrj 341112f080e7Smrj /* 341212f080e7Smrj * initialize the next window using what's left over in the previous 341312f080e7Smrj * cookie. 341412f080e7Smrj */ 341512f080e7Smrj (*windowp)++; 341612f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, new_offset); 341712f080e7Smrj (*windowp)->wd_cookie_cnt++; 341812f080e7Smrj (*windowp)->wd_trim.tr_trim_first = B_TRUE; 3419843e1988Sjohnlev (*windowp)->wd_trim.tr_first_paddr = cookie->dmac_laddress + coffset; 342012f080e7Smrj (*windowp)->wd_trim.tr_first_size = trim_sz; 342112f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 342212f080e7Smrj (*windowp)->wd_dosync = B_TRUE; 342312f080e7Smrj } 342412f080e7Smrj 342512f080e7Smrj /* 342612f080e7Smrj * now go back to the current cookie and add it to the new window. set 342712f080e7Smrj * the new window size to the what was left over from the previous 342812f080e7Smrj * cookie and what's in the current cookie. 342912f080e7Smrj */ 343012f080e7Smrj cookie++; 343112f080e7Smrj (*windowp)->wd_cookie_cnt++; 343212f080e7Smrj (*windowp)->wd_size = trim_sz + cookie->dmac_size; 343312f080e7Smrj 343412f080e7Smrj /* 343512f080e7Smrj * trim plus the next cookie could put us over maxxfer (a cookie can be 343612f080e7Smrj * a max size of maxxfer). Handle that case. 343712f080e7Smrj */ 343812f080e7Smrj if ((*windowp)->wd_size > dma->dp_maxxfer) { 343912f080e7Smrj /* 344012f080e7Smrj * maxxfer is already a whole multiple of granularity, and this 344112f080e7Smrj * trim will be <= the previous trim (since a cookie can't be 344212f080e7Smrj * larger than maxxfer). Make things simple here. 344312f080e7Smrj */ 344412f080e7Smrj trim_sz = (*windowp)->wd_size - dma->dp_maxxfer; 344512f080e7Smrj (*windowp)->wd_trim.tr_trim_last = B_TRUE; 344612f080e7Smrj (*windowp)->wd_trim.tr_last_cookie = cookie; 3447843e1988Sjohnlev (*windowp)->wd_trim.tr_last_paddr = cookie->dmac_laddress; 344812f080e7Smrj (*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz; 344912f080e7Smrj (*windowp)->wd_size -= trim_sz; 345012f080e7Smrj ASSERT((*windowp)->wd_size == dma->dp_maxxfer); 345112f080e7Smrj 345212f080e7Smrj /* save the buffer offsets for the next window */ 345312f080e7Smrj coffset = cookie->dmac_size - trim_sz; 345412f080e7Smrj new_offset = (*windowp)->wd_offset + (*windowp)->wd_size; 345512f080e7Smrj 345612f080e7Smrj /* setup the next window */ 345712f080e7Smrj (*windowp)++; 345812f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, new_offset); 345912f080e7Smrj (*windowp)->wd_cookie_cnt++; 346012f080e7Smrj (*windowp)->wd_trim.tr_trim_first = B_TRUE; 3461843e1988Sjohnlev (*windowp)->wd_trim.tr_first_paddr = cookie->dmac_laddress + 346212f080e7Smrj coffset; 346312f080e7Smrj (*windowp)->wd_trim.tr_first_size = trim_sz; 346412f080e7Smrj } 346512f080e7Smrj 346612f080e7Smrj return (DDI_SUCCESS); 346712f080e7Smrj } 346812f080e7Smrj 346912f080e7Smrj 347012f080e7Smrj /* 347112f080e7Smrj * rootnex_copybuf_window_boundary() 347212f080e7Smrj * Called in bind slowpath when we get to a window boundary because we used 347312f080e7Smrj * up all the copy buffer that we have. 347412f080e7Smrj */ 347512f080e7Smrj static int 347612f080e7Smrj rootnex_copybuf_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 347712f080e7Smrj rootnex_window_t **windowp, ddi_dma_cookie_t *cookie, off_t cur_offset, 347812f080e7Smrj size_t *copybuf_used) 347912f080e7Smrj { 348012f080e7Smrj rootnex_sglinfo_t *sinfo; 348112f080e7Smrj off_t new_offset; 348212f080e7Smrj size_t trim_sz; 3483843e1988Sjohnlev paddr_t paddr; 348412f080e7Smrj off_t coffset; 348512f080e7Smrj uint_t pidx; 348612f080e7Smrj off_t poff; 348712f080e7Smrj 348812f080e7Smrj 348912f080e7Smrj sinfo = &dma->dp_sglinfo; 349012f080e7Smrj 349112f080e7Smrj /* 349212f080e7Smrj * the copy buffer should be a whole multiple of page size. We know that 349312f080e7Smrj * this cookie is <= MMU_PAGESIZE. 349412f080e7Smrj */ 349512f080e7Smrj ASSERT(cookie->dmac_size <= MMU_PAGESIZE); 349612f080e7Smrj 349712f080e7Smrj /* 349812f080e7Smrj * from now on, all new windows in this bind need to be re-mapped during 349912f080e7Smrj * ddi_dma_getwin() (32-bit kernel only). i.e. we ran out out copybuf 350012f080e7Smrj * space... 350112f080e7Smrj */ 350212f080e7Smrj #if !defined(__amd64) 350312f080e7Smrj dma->dp_cb_remaping = B_TRUE; 350412f080e7Smrj #endif 350512f080e7Smrj 350612f080e7Smrj /* reset copybuf used */ 350712f080e7Smrj *copybuf_used = 0; 350812f080e7Smrj 350912f080e7Smrj /* 351012f080e7Smrj * if we don't have to trim (since granularity is set to 1), go to the 351112f080e7Smrj * next window and add the current cookie to it. We know the current 351212f080e7Smrj * cookie uses the copy buffer since we're in this code path. 351312f080e7Smrj */ 351412f080e7Smrj if (!dma->dp_trim_required) { 351512f080e7Smrj (*windowp)++; 351612f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, cur_offset); 351712f080e7Smrj 351812f080e7Smrj /* Add this cookie to the new window */ 351912f080e7Smrj (*windowp)->wd_cookie_cnt++; 352012f080e7Smrj (*windowp)->wd_size += cookie->dmac_size; 352112f080e7Smrj *copybuf_used += MMU_PAGESIZE; 352212f080e7Smrj return (DDI_SUCCESS); 352312f080e7Smrj } 352412f080e7Smrj 352512f080e7Smrj /* 352612f080e7Smrj * *** may need to trim, figure it out. 352712f080e7Smrj */ 352812f080e7Smrj 352912f080e7Smrj /* figure out how much we need to trim from the window */ 353012f080e7Smrj if (dma->dp_granularity_power_2) { 353112f080e7Smrj trim_sz = (*windowp)->wd_size & 353212f080e7Smrj (hp->dmai_attr.dma_attr_granular - 1); 353312f080e7Smrj } else { 353412f080e7Smrj trim_sz = (*windowp)->wd_size % hp->dmai_attr.dma_attr_granular; 353512f080e7Smrj } 353612f080e7Smrj 353712f080e7Smrj /* 353812f080e7Smrj * if the window's a whole multiple of granularity, go to the next 353912f080e7Smrj * window, init it, then add in the current cookie. We know the current 354012f080e7Smrj * cookie uses the copy buffer since we're in this code path. 354112f080e7Smrj */ 354212f080e7Smrj if (trim_sz == 0) { 354312f080e7Smrj (*windowp)++; 354412f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, cur_offset); 354512f080e7Smrj 354612f080e7Smrj /* Add this cookie to the new window */ 354712f080e7Smrj (*windowp)->wd_cookie_cnt++; 354812f080e7Smrj (*windowp)->wd_size += cookie->dmac_size; 354912f080e7Smrj *copybuf_used += MMU_PAGESIZE; 355012f080e7Smrj return (DDI_SUCCESS); 355112f080e7Smrj } 355212f080e7Smrj 355312f080e7Smrj /* 355412f080e7Smrj * *** We figured it out, we definitly need to trim 355512f080e7Smrj */ 355612f080e7Smrj 355712f080e7Smrj /* 355812f080e7Smrj * make sure the driver isn't making us do something bad... 355912f080e7Smrj * Trimming and sgllen == 1 don't go together. 356012f080e7Smrj */ 356112f080e7Smrj if (hp->dmai_attr.dma_attr_sgllen == 1) { 356212f080e7Smrj return (DDI_DMA_NOMAPPING); 356312f080e7Smrj } 356412f080e7Smrj 356512f080e7Smrj /* 356612f080e7Smrj * first, setup the current window to account for the trim. Need to go 356712f080e7Smrj * back to the last cookie for this. Some of the last cookie will be in 356812f080e7Smrj * the current window, and some of the last cookie will be in the new 356912f080e7Smrj * window. All of the current cookie will be in the new window. 357012f080e7Smrj */ 357112f080e7Smrj cookie--; 357212f080e7Smrj (*windowp)->wd_trim.tr_trim_last = B_TRUE; 357312f080e7Smrj (*windowp)->wd_trim.tr_last_cookie = cookie; 3574843e1988Sjohnlev (*windowp)->wd_trim.tr_last_paddr = cookie->dmac_laddress; 357512f080e7Smrj ASSERT(cookie->dmac_size > trim_sz); 357612f080e7Smrj (*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz; 357712f080e7Smrj (*windowp)->wd_size -= trim_sz; 357812f080e7Smrj 357912f080e7Smrj /* 358012f080e7Smrj * we're trimming the last cookie (not the current cookie). So that 358112f080e7Smrj * last cookie may have or may not have been using the copy buffer ( 358212f080e7Smrj * we know the cookie passed in uses the copy buffer since we're in 358312f080e7Smrj * this code path). 358412f080e7Smrj * 358512f080e7Smrj * If the last cookie doesn't use the copy buffer, nothing special to 358612f080e7Smrj * do. However, if it does uses the copy buffer, it will be both the 358712f080e7Smrj * last page in the current window and the first page in the next 358812f080e7Smrj * window. Since we are reusing the copy buffer (and KVA space on the 358912f080e7Smrj * 32-bit kernel), this page will use the end of the copy buffer in the 359012f080e7Smrj * current window, and the start of the copy buffer in the next window. 359112f080e7Smrj * Track that info... The cookie physical address was already set to 359212f080e7Smrj * the copy buffer physical address in setup_cookie.. 359312f080e7Smrj */ 359412f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 359512f080e7Smrj pidx = (sinfo->si_buf_offset + (*windowp)->wd_offset + 359612f080e7Smrj (*windowp)->wd_size) >> MMU_PAGESHIFT; 359712f080e7Smrj (*windowp)->wd_trim.tr_last_copybuf_win = B_TRUE; 359812f080e7Smrj (*windowp)->wd_trim.tr_last_pidx = pidx; 359912f080e7Smrj (*windowp)->wd_trim.tr_last_cbaddr = 360012f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr; 360112f080e7Smrj #if !defined(__amd64) 360212f080e7Smrj (*windowp)->wd_trim.tr_last_kaddr = 360312f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr; 360412f080e7Smrj #endif 360512f080e7Smrj } 360612f080e7Smrj 360712f080e7Smrj /* save the buffer offsets for the next window */ 360812f080e7Smrj coffset = cookie->dmac_size - trim_sz; 360912f080e7Smrj new_offset = (*windowp)->wd_offset + (*windowp)->wd_size; 361012f080e7Smrj 361112f080e7Smrj /* 361212f080e7Smrj * set this now in case this is the first window. all other cases are 361312f080e7Smrj * set in dma_win() 361412f080e7Smrj */ 361512f080e7Smrj cookie->dmac_size = (*windowp)->wd_trim.tr_last_size; 361612f080e7Smrj 361712f080e7Smrj /* 361812f080e7Smrj * initialize the next window using what's left over in the previous 361912f080e7Smrj * cookie. 362012f080e7Smrj */ 362112f080e7Smrj (*windowp)++; 362212f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, new_offset); 362312f080e7Smrj (*windowp)->wd_cookie_cnt++; 362412f080e7Smrj (*windowp)->wd_trim.tr_trim_first = B_TRUE; 3625843e1988Sjohnlev (*windowp)->wd_trim.tr_first_paddr = cookie->dmac_laddress + coffset; 362612f080e7Smrj (*windowp)->wd_trim.tr_first_size = trim_sz; 362712f080e7Smrj 362812f080e7Smrj /* 362912f080e7Smrj * again, we're tracking if the last cookie uses the copy buffer. 363012f080e7Smrj * read the comment above for more info on why we need to track 363112f080e7Smrj * additional state. 363212f080e7Smrj * 363312f080e7Smrj * For the first cookie in the new window, we need reset the physical 363412f080e7Smrj * address to DMA into to the start of the copy buffer plus any 363512f080e7Smrj * initial page offset which may be present. 363612f080e7Smrj */ 363712f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 363812f080e7Smrj (*windowp)->wd_dosync = B_TRUE; 363912f080e7Smrj (*windowp)->wd_trim.tr_first_copybuf_win = B_TRUE; 364012f080e7Smrj (*windowp)->wd_trim.tr_first_pidx = pidx; 364112f080e7Smrj (*windowp)->wd_trim.tr_first_cbaddr = dma->dp_cbaddr; 364212f080e7Smrj poff = (*windowp)->wd_trim.tr_first_paddr & MMU_PAGEOFFSET; 3643843e1988Sjohnlev 3644843e1988Sjohnlev paddr = pfn_to_pa(hat_getpfnum(kas.a_hat, dma->dp_cbaddr)) + 3645843e1988Sjohnlev poff; 3646843e1988Sjohnlev #ifdef __xpv 3647843e1988Sjohnlev /* 3648843e1988Sjohnlev * If we're dom0, we're using a real device so we need to load 3649843e1988Sjohnlev * the cookies with MAs instead of PAs. 3650843e1988Sjohnlev */ 3651843e1988Sjohnlev (*windowp)->wd_trim.tr_first_paddr = 3652843e1988Sjohnlev ROOTNEX_PADDR_TO_RBASE(xen_info, paddr); 3653843e1988Sjohnlev #else 3654843e1988Sjohnlev (*windowp)->wd_trim.tr_first_paddr = paddr; 3655843e1988Sjohnlev #endif 3656843e1988Sjohnlev 365712f080e7Smrj #if !defined(__amd64) 365812f080e7Smrj (*windowp)->wd_trim.tr_first_kaddr = dma->dp_kva; 365912f080e7Smrj #endif 366012f080e7Smrj /* account for the cookie copybuf usage in the new window */ 366112f080e7Smrj *copybuf_used += MMU_PAGESIZE; 366212f080e7Smrj 366312f080e7Smrj /* 366412f080e7Smrj * every piece of code has to have a hack, and here is this 366512f080e7Smrj * ones :-) 366612f080e7Smrj * 366712f080e7Smrj * There is a complex interaction between setup_cookie and the 366812f080e7Smrj * copybuf window boundary. The complexity had to be in either 366912f080e7Smrj * the maxxfer window, or the copybuf window, and I chose the 367012f080e7Smrj * copybuf code. 367112f080e7Smrj * 367212f080e7Smrj * So in this code path, we have taken the last cookie, 367312f080e7Smrj * virtually broken it in half due to the trim, and it happens 367412f080e7Smrj * to use the copybuf which further complicates life. At the 367512f080e7Smrj * same time, we have already setup the current cookie, which 367612f080e7Smrj * is now wrong. More background info: the current cookie uses 367712f080e7Smrj * the copybuf, so it is only a page long max. So we need to 367812f080e7Smrj * fix the current cookies copy buffer address, physical 367912f080e7Smrj * address, and kva for the 32-bit kernel. We due this by 368012f080e7Smrj * bumping them by page size (of course, we can't due this on 368112f080e7Smrj * the physical address since the copy buffer may not be 368212f080e7Smrj * physically contiguous). 368312f080e7Smrj */ 368412f080e7Smrj cookie++; 368512f080e7Smrj dma->dp_pgmap[pidx + 1].pm_cbaddr += MMU_PAGESIZE; 3686843e1988Sjohnlev poff = cookie->dmac_laddress & MMU_PAGEOFFSET; 3687843e1988Sjohnlev 3688843e1988Sjohnlev paddr = pfn_to_pa(hat_getpfnum(kas.a_hat, 368912f080e7Smrj dma->dp_pgmap[pidx + 1].pm_cbaddr)) + poff; 3690843e1988Sjohnlev #ifdef __xpv 3691843e1988Sjohnlev /* 3692843e1988Sjohnlev * If we're dom0, we're using a real device so we need to load 3693843e1988Sjohnlev * the cookies with MAs instead of PAs. 3694843e1988Sjohnlev */ 3695843e1988Sjohnlev cookie->dmac_laddress = ROOTNEX_PADDR_TO_RBASE(xen_info, paddr); 3696843e1988Sjohnlev #else 3697843e1988Sjohnlev cookie->dmac_laddress = paddr; 3698843e1988Sjohnlev #endif 3699843e1988Sjohnlev 370012f080e7Smrj #if !defined(__amd64) 370112f080e7Smrj ASSERT(dma->dp_pgmap[pidx + 1].pm_mapped == B_FALSE); 370212f080e7Smrj dma->dp_pgmap[pidx + 1].pm_kaddr += MMU_PAGESIZE; 370312f080e7Smrj #endif 370412f080e7Smrj } else { 370512f080e7Smrj /* go back to the current cookie */ 370612f080e7Smrj cookie++; 370712f080e7Smrj } 370812f080e7Smrj 370912f080e7Smrj /* 371012f080e7Smrj * add the current cookie to the new window. set the new window size to 371112f080e7Smrj * the what was left over from the previous cookie and what's in the 371212f080e7Smrj * current cookie. 371312f080e7Smrj */ 371412f080e7Smrj (*windowp)->wd_cookie_cnt++; 371512f080e7Smrj (*windowp)->wd_size = trim_sz + cookie->dmac_size; 371612f080e7Smrj ASSERT((*windowp)->wd_size < dma->dp_maxxfer); 371712f080e7Smrj 371812f080e7Smrj /* 371912f080e7Smrj * we know that the cookie passed in always uses the copy buffer. We 372012f080e7Smrj * wouldn't be here if it didn't. 372112f080e7Smrj */ 372212f080e7Smrj *copybuf_used += MMU_PAGESIZE; 372312f080e7Smrj 372412f080e7Smrj return (DDI_SUCCESS); 372512f080e7Smrj } 372612f080e7Smrj 372712f080e7Smrj 372812f080e7Smrj /* 372912f080e7Smrj * rootnex_maxxfer_window_boundary() 373012f080e7Smrj * Called in bind slowpath when we get to a window boundary because we will 373112f080e7Smrj * go over maxxfer. 373212f080e7Smrj */ 373312f080e7Smrj static int 373412f080e7Smrj rootnex_maxxfer_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 373512f080e7Smrj rootnex_window_t **windowp, ddi_dma_cookie_t *cookie) 373612f080e7Smrj { 373712f080e7Smrj size_t dmac_size; 373812f080e7Smrj off_t new_offset; 373912f080e7Smrj size_t trim_sz; 374012f080e7Smrj off_t coffset; 374112f080e7Smrj 374212f080e7Smrj 374312f080e7Smrj /* 374412f080e7Smrj * calculate how much we have to trim off of the current cookie to equal 374512f080e7Smrj * maxxfer. We don't have to account for granularity here since our 374612f080e7Smrj * maxxfer already takes that into account. 374712f080e7Smrj */ 374812f080e7Smrj trim_sz = ((*windowp)->wd_size + cookie->dmac_size) - dma->dp_maxxfer; 374912f080e7Smrj ASSERT(trim_sz <= cookie->dmac_size); 375012f080e7Smrj ASSERT(trim_sz <= dma->dp_maxxfer); 375112f080e7Smrj 375212f080e7Smrj /* save cookie size since we need it later and we might change it */ 375312f080e7Smrj dmac_size = cookie->dmac_size; 375412f080e7Smrj 375512f080e7Smrj /* 375612f080e7Smrj * if we're not trimming the entire cookie, setup the current window to 375712f080e7Smrj * account for the trim. 375812f080e7Smrj */ 375912f080e7Smrj if (trim_sz < cookie->dmac_size) { 376012f080e7Smrj (*windowp)->wd_cookie_cnt++; 376112f080e7Smrj (*windowp)->wd_trim.tr_trim_last = B_TRUE; 376212f080e7Smrj (*windowp)->wd_trim.tr_last_cookie = cookie; 3763843e1988Sjohnlev (*windowp)->wd_trim.tr_last_paddr = cookie->dmac_laddress; 376412f080e7Smrj (*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz; 376512f080e7Smrj (*windowp)->wd_size = dma->dp_maxxfer; 376612f080e7Smrj 376712f080e7Smrj /* 376812f080e7Smrj * set the adjusted cookie size now in case this is the first 376912f080e7Smrj * window. All other windows are taken care of in get win 377012f080e7Smrj */ 377112f080e7Smrj cookie->dmac_size = (*windowp)->wd_trim.tr_last_size; 377212f080e7Smrj } 377312f080e7Smrj 377412f080e7Smrj /* 377512f080e7Smrj * coffset is the current offset within the cookie, new_offset is the 377612f080e7Smrj * current offset with the entire buffer. 377712f080e7Smrj */ 377812f080e7Smrj coffset = dmac_size - trim_sz; 377912f080e7Smrj new_offset = (*windowp)->wd_offset + (*windowp)->wd_size; 378012f080e7Smrj 378112f080e7Smrj /* initialize the next window */ 378212f080e7Smrj (*windowp)++; 378312f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, new_offset); 378412f080e7Smrj (*windowp)->wd_cookie_cnt++; 378512f080e7Smrj (*windowp)->wd_size = trim_sz; 378612f080e7Smrj if (trim_sz < dmac_size) { 378712f080e7Smrj (*windowp)->wd_trim.tr_trim_first = B_TRUE; 3788843e1988Sjohnlev (*windowp)->wd_trim.tr_first_paddr = cookie->dmac_laddress + 378912f080e7Smrj coffset; 379012f080e7Smrj (*windowp)->wd_trim.tr_first_size = trim_sz; 379112f080e7Smrj } 379212f080e7Smrj 379312f080e7Smrj return (DDI_SUCCESS); 379412f080e7Smrj } 379512f080e7Smrj 379612f080e7Smrj 379712f080e7Smrj /* 379812f080e7Smrj * rootnex_dma_sync() 379912f080e7Smrj * called from ddi_dma_sync() if DMP_NOSYNC is not set in hp->dmai_rflags. 380012f080e7Smrj * We set DMP_NOSYNC if we're not using the copy buffer. If DMP_NOSYNC 380112f080e7Smrj * is set, ddi_dma_sync() returns immediately passing back success. 380212f080e7Smrj */ 380312f080e7Smrj /*ARGSUSED*/ 380412f080e7Smrj static int 380512f080e7Smrj rootnex_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 380612f080e7Smrj off_t off, size_t len, uint_t cache_flags) 380712f080e7Smrj { 380812f080e7Smrj rootnex_sglinfo_t *sinfo; 380912f080e7Smrj rootnex_pgmap_t *cbpage; 381012f080e7Smrj rootnex_window_t *win; 381112f080e7Smrj ddi_dma_impl_t *hp; 381212f080e7Smrj rootnex_dma_t *dma; 381312f080e7Smrj caddr_t fromaddr; 381412f080e7Smrj caddr_t toaddr; 381512f080e7Smrj uint_t psize; 381612f080e7Smrj off_t offset; 381712f080e7Smrj uint_t pidx; 381812f080e7Smrj size_t size; 381912f080e7Smrj off_t poff; 382012f080e7Smrj int e; 382112f080e7Smrj 382212f080e7Smrj 382312f080e7Smrj hp = (ddi_dma_impl_t *)handle; 382412f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 382512f080e7Smrj sinfo = &dma->dp_sglinfo; 382612f080e7Smrj 382712f080e7Smrj /* 382812f080e7Smrj * if we don't have any windows, we don't need to sync. A copybuf 382912f080e7Smrj * will cause us to have at least one window. 383012f080e7Smrj */ 383112f080e7Smrj if (dma->dp_window == NULL) { 383212f080e7Smrj return (DDI_SUCCESS); 383312f080e7Smrj } 383412f080e7Smrj 383512f080e7Smrj /* This window may not need to be sync'd */ 383612f080e7Smrj win = &dma->dp_window[dma->dp_current_win]; 383712f080e7Smrj if (!win->wd_dosync) { 383812f080e7Smrj return (DDI_SUCCESS); 383912f080e7Smrj } 384012f080e7Smrj 384112f080e7Smrj /* handle off and len special cases */ 384212f080e7Smrj if ((off == 0) || (rootnex_sync_ignore_params)) { 384312f080e7Smrj offset = win->wd_offset; 384412f080e7Smrj } else { 384512f080e7Smrj offset = off; 384612f080e7Smrj } 384712f080e7Smrj if ((len == 0) || (rootnex_sync_ignore_params)) { 384812f080e7Smrj size = win->wd_size; 384912f080e7Smrj } else { 385012f080e7Smrj size = len; 385112f080e7Smrj } 385212f080e7Smrj 385312f080e7Smrj /* check the sync args to make sure they make a little sense */ 385412f080e7Smrj if (rootnex_sync_check_parms) { 385512f080e7Smrj e = rootnex_valid_sync_parms(hp, win, offset, size, 385612f080e7Smrj cache_flags); 385712f080e7Smrj if (e != DDI_SUCCESS) { 385812f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_SYNC_FAIL]); 385912f080e7Smrj return (DDI_FAILURE); 386012f080e7Smrj } 386112f080e7Smrj } 386212f080e7Smrj 386312f080e7Smrj /* 386412f080e7Smrj * special case the first page to handle the offset into the page. The 386512f080e7Smrj * offset to the current page for our buffer is the offset into the 386612f080e7Smrj * first page of the buffer plus our current offset into the buffer 386712f080e7Smrj * itself, masked of course. 386812f080e7Smrj */ 386912f080e7Smrj poff = (sinfo->si_buf_offset + offset) & MMU_PAGEOFFSET; 387012f080e7Smrj psize = MIN((MMU_PAGESIZE - poff), size); 387112f080e7Smrj 387212f080e7Smrj /* go through all the pages that we want to sync */ 387312f080e7Smrj while (size > 0) { 387412f080e7Smrj /* 387512f080e7Smrj * Calculate the page index relative to the start of the buffer. 387612f080e7Smrj * The index to the current page for our buffer is the offset 387712f080e7Smrj * into the first page of the buffer plus our current offset 387812f080e7Smrj * into the buffer itself, shifted of course... 387912f080e7Smrj */ 388012f080e7Smrj pidx = (sinfo->si_buf_offset + offset) >> MMU_PAGESHIFT; 388112f080e7Smrj ASSERT(pidx < sinfo->si_max_pages); 388212f080e7Smrj 388312f080e7Smrj /* 388412f080e7Smrj * if this page uses the copy buffer, we need to sync it, 388512f080e7Smrj * otherwise, go on to the next page. 388612f080e7Smrj */ 388712f080e7Smrj cbpage = &dma->dp_pgmap[pidx]; 388812f080e7Smrj ASSERT((cbpage->pm_uses_copybuf == B_TRUE) || 388912f080e7Smrj (cbpage->pm_uses_copybuf == B_FALSE)); 389012f080e7Smrj if (cbpage->pm_uses_copybuf) { 389112f080e7Smrj /* cbaddr and kaddr should be page aligned */ 389212f080e7Smrj ASSERT(((uintptr_t)cbpage->pm_cbaddr & 389312f080e7Smrj MMU_PAGEOFFSET) == 0); 389412f080e7Smrj ASSERT(((uintptr_t)cbpage->pm_kaddr & 389512f080e7Smrj MMU_PAGEOFFSET) == 0); 389612f080e7Smrj 389712f080e7Smrj /* 389812f080e7Smrj * if we're copying for the device, we are going to 389912f080e7Smrj * copy from the drivers buffer and to the rootnex 390012f080e7Smrj * allocated copy buffer. 390112f080e7Smrj */ 390212f080e7Smrj if (cache_flags == DDI_DMA_SYNC_FORDEV) { 390312f080e7Smrj fromaddr = cbpage->pm_kaddr + poff; 390412f080e7Smrj toaddr = cbpage->pm_cbaddr + poff; 390512f080e7Smrj DTRACE_PROBE2(rootnex__sync__dev, 390612f080e7Smrj dev_info_t *, dma->dp_dip, size_t, psize); 390712f080e7Smrj 390812f080e7Smrj /* 390912f080e7Smrj * if we're copying for the cpu/kernel, we are going to 391012f080e7Smrj * copy from the rootnex allocated copy buffer to the 391112f080e7Smrj * drivers buffer. 391212f080e7Smrj */ 391312f080e7Smrj } else { 391412f080e7Smrj fromaddr = cbpage->pm_cbaddr + poff; 391512f080e7Smrj toaddr = cbpage->pm_kaddr + poff; 391612f080e7Smrj DTRACE_PROBE2(rootnex__sync__cpu, 391712f080e7Smrj dev_info_t *, dma->dp_dip, size_t, psize); 391812f080e7Smrj } 391912f080e7Smrj 392012f080e7Smrj bcopy(fromaddr, toaddr, psize); 392112f080e7Smrj } 392212f080e7Smrj 392312f080e7Smrj /* 392412f080e7Smrj * decrement size until we're done, update our offset into the 392512f080e7Smrj * buffer, and get the next page size. 392612f080e7Smrj */ 392712f080e7Smrj size -= psize; 392812f080e7Smrj offset += psize; 392912f080e7Smrj psize = MIN(MMU_PAGESIZE, size); 393012f080e7Smrj 393112f080e7Smrj /* page offset is zero for the rest of this loop */ 393212f080e7Smrj poff = 0; 393312f080e7Smrj } 393412f080e7Smrj 393512f080e7Smrj return (DDI_SUCCESS); 393612f080e7Smrj } 393712f080e7Smrj 393812f080e7Smrj 393912f080e7Smrj /* 394012f080e7Smrj * rootnex_valid_sync_parms() 394112f080e7Smrj * checks the parameters passed to sync to verify they are correct. 394212f080e7Smrj */ 394312f080e7Smrj static int 394412f080e7Smrj rootnex_valid_sync_parms(ddi_dma_impl_t *hp, rootnex_window_t *win, 394512f080e7Smrj off_t offset, size_t size, uint_t cache_flags) 394612f080e7Smrj { 394712f080e7Smrj off_t woffset; 394812f080e7Smrj 394912f080e7Smrj 395012f080e7Smrj /* 395112f080e7Smrj * the first part of the test to make sure the offset passed in is 395212f080e7Smrj * within the window. 395312f080e7Smrj */ 395412f080e7Smrj if (offset < win->wd_offset) { 395512f080e7Smrj return (DDI_FAILURE); 395612f080e7Smrj } 395712f080e7Smrj 395812f080e7Smrj /* 395912f080e7Smrj * second and last part of the test to make sure the offset and length 396012f080e7Smrj * passed in is within the window. 396112f080e7Smrj */ 396212f080e7Smrj woffset = offset - win->wd_offset; 396312f080e7Smrj if ((woffset + size) > win->wd_size) { 396412f080e7Smrj return (DDI_FAILURE); 396512f080e7Smrj } 396612f080e7Smrj 396712f080e7Smrj /* 396812f080e7Smrj * if we are sync'ing for the device, the DDI_DMA_WRITE flag should 396912f080e7Smrj * be set too. 397012f080e7Smrj */ 397112f080e7Smrj if ((cache_flags == DDI_DMA_SYNC_FORDEV) && 397212f080e7Smrj (hp->dmai_rflags & DDI_DMA_WRITE)) { 397312f080e7Smrj return (DDI_SUCCESS); 397412f080e7Smrj } 397512f080e7Smrj 397612f080e7Smrj /* 397712f080e7Smrj * at this point, either DDI_DMA_SYNC_FORCPU or DDI_DMA_SYNC_FORKERNEL 397812f080e7Smrj * should be set. Also DDI_DMA_READ should be set in the flags. 397912f080e7Smrj */ 398012f080e7Smrj if (((cache_flags == DDI_DMA_SYNC_FORCPU) || 398112f080e7Smrj (cache_flags == DDI_DMA_SYNC_FORKERNEL)) && 398212f080e7Smrj (hp->dmai_rflags & DDI_DMA_READ)) { 398312f080e7Smrj return (DDI_SUCCESS); 398412f080e7Smrj } 398512f080e7Smrj 398612f080e7Smrj return (DDI_FAILURE); 398712f080e7Smrj } 398812f080e7Smrj 398912f080e7Smrj 399012f080e7Smrj /* 399112f080e7Smrj * rootnex_dma_win() 399212f080e7Smrj * called from ddi_dma_getwin() 399312f080e7Smrj */ 399412f080e7Smrj /*ARGSUSED*/ 399512f080e7Smrj static int 399612f080e7Smrj rootnex_dma_win(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 399712f080e7Smrj uint_t win, off_t *offp, size_t *lenp, ddi_dma_cookie_t *cookiep, 399812f080e7Smrj uint_t *ccountp) 399912f080e7Smrj { 400012f080e7Smrj rootnex_window_t *window; 400112f080e7Smrj rootnex_trim_t *trim; 400212f080e7Smrj ddi_dma_impl_t *hp; 400312f080e7Smrj rootnex_dma_t *dma; 400412f080e7Smrj #if !defined(__amd64) 400512f080e7Smrj rootnex_sglinfo_t *sinfo; 400612f080e7Smrj rootnex_pgmap_t *pmap; 400712f080e7Smrj uint_t pidx; 400812f080e7Smrj uint_t pcnt; 400912f080e7Smrj off_t poff; 401012f080e7Smrj int i; 401112f080e7Smrj #endif 401212f080e7Smrj 401312f080e7Smrj 401412f080e7Smrj hp = (ddi_dma_impl_t *)handle; 401512f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 401612f080e7Smrj #if !defined(__amd64) 401712f080e7Smrj sinfo = &dma->dp_sglinfo; 401812f080e7Smrj #endif 401912f080e7Smrj 402012f080e7Smrj /* If we try and get a window which doesn't exist, return failure */ 402112f080e7Smrj if (win >= hp->dmai_nwin) { 402212f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_GETWIN_FAIL]); 402312f080e7Smrj return (DDI_FAILURE); 402412f080e7Smrj } 402512f080e7Smrj 402612f080e7Smrj /* 402712f080e7Smrj * if we don't have any windows, and they're asking for the first 402812f080e7Smrj * window, setup the cookie pointer to the first cookie in the bind. 402912f080e7Smrj * setup our return values, then increment the cookie since we return 403012f080e7Smrj * the first cookie on the stack. 403112f080e7Smrj */ 403212f080e7Smrj if (dma->dp_window == NULL) { 403312f080e7Smrj if (win != 0) { 403412f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_GETWIN_FAIL]); 403512f080e7Smrj return (DDI_FAILURE); 403612f080e7Smrj } 403712f080e7Smrj hp->dmai_cookie = dma->dp_cookies; 403812f080e7Smrj *offp = 0; 403912f080e7Smrj *lenp = dma->dp_dma.dmao_size; 404012f080e7Smrj *ccountp = dma->dp_sglinfo.si_sgl_size; 404112f080e7Smrj *cookiep = hp->dmai_cookie[0]; 404212f080e7Smrj hp->dmai_cookie++; 404312f080e7Smrj return (DDI_SUCCESS); 404412f080e7Smrj } 404512f080e7Smrj 404612f080e7Smrj /* sync the old window before moving on to the new one */ 404712f080e7Smrj window = &dma->dp_window[dma->dp_current_win]; 404812f080e7Smrj if ((window->wd_dosync) && (hp->dmai_rflags & DDI_DMA_READ)) { 404912f080e7Smrj (void) rootnex_dma_sync(dip, rdip, handle, 0, 0, 405012f080e7Smrj DDI_DMA_SYNC_FORCPU); 405112f080e7Smrj } 405212f080e7Smrj 405312f080e7Smrj #if !defined(__amd64) 405412f080e7Smrj /* 405512f080e7Smrj * before we move to the next window, if we need to re-map, unmap all 405612f080e7Smrj * the pages in this window. 405712f080e7Smrj */ 405812f080e7Smrj if (dma->dp_cb_remaping) { 405912f080e7Smrj /* 406012f080e7Smrj * If we switch to this window again, we'll need to map in 406112f080e7Smrj * on the fly next time. 406212f080e7Smrj */ 406312f080e7Smrj window->wd_remap_copybuf = B_TRUE; 406412f080e7Smrj 406512f080e7Smrj /* 406612f080e7Smrj * calculate the page index into the buffer where this window 406712f080e7Smrj * starts, and the number of pages this window takes up. 406812f080e7Smrj */ 406912f080e7Smrj pidx = (sinfo->si_buf_offset + window->wd_offset) >> 407012f080e7Smrj MMU_PAGESHIFT; 407112f080e7Smrj poff = (sinfo->si_buf_offset + window->wd_offset) & 407212f080e7Smrj MMU_PAGEOFFSET; 407312f080e7Smrj pcnt = mmu_btopr(window->wd_size + poff); 407412f080e7Smrj ASSERT((pidx + pcnt) <= sinfo->si_max_pages); 407512f080e7Smrj 407612f080e7Smrj /* unmap pages which are currently mapped in this window */ 407712f080e7Smrj for (i = 0; i < pcnt; i++) { 407812f080e7Smrj if (dma->dp_pgmap[pidx].pm_mapped) { 407912f080e7Smrj hat_unload(kas.a_hat, 408012f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr, MMU_PAGESIZE, 408112f080e7Smrj HAT_UNLOAD); 408212f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_FALSE; 408312f080e7Smrj } 408412f080e7Smrj pidx++; 408512f080e7Smrj } 408612f080e7Smrj } 408712f080e7Smrj #endif 408812f080e7Smrj 408912f080e7Smrj /* 409012f080e7Smrj * Move to the new window. 409112f080e7Smrj * NOTE: current_win must be set for sync to work right 409212f080e7Smrj */ 409312f080e7Smrj dma->dp_current_win = win; 409412f080e7Smrj window = &dma->dp_window[win]; 409512f080e7Smrj 409612f080e7Smrj /* if needed, adjust the first and/or last cookies for trim */ 409712f080e7Smrj trim = &window->wd_trim; 409812f080e7Smrj if (trim->tr_trim_first) { 4099843e1988Sjohnlev window->wd_first_cookie->dmac_laddress = trim->tr_first_paddr; 410012f080e7Smrj window->wd_first_cookie->dmac_size = trim->tr_first_size; 410112f080e7Smrj #if !defined(__amd64) 410212f080e7Smrj window->wd_first_cookie->dmac_type = 410312f080e7Smrj (window->wd_first_cookie->dmac_type & 410412f080e7Smrj ROOTNEX_USES_COPYBUF) + window->wd_offset; 410512f080e7Smrj #endif 410612f080e7Smrj if (trim->tr_first_copybuf_win) { 410712f080e7Smrj dma->dp_pgmap[trim->tr_first_pidx].pm_cbaddr = 410812f080e7Smrj trim->tr_first_cbaddr; 410912f080e7Smrj #if !defined(__amd64) 411012f080e7Smrj dma->dp_pgmap[trim->tr_first_pidx].pm_kaddr = 411112f080e7Smrj trim->tr_first_kaddr; 411212f080e7Smrj #endif 411312f080e7Smrj } 411412f080e7Smrj } 411512f080e7Smrj if (trim->tr_trim_last) { 4116843e1988Sjohnlev trim->tr_last_cookie->dmac_laddress = trim->tr_last_paddr; 411712f080e7Smrj trim->tr_last_cookie->dmac_size = trim->tr_last_size; 411812f080e7Smrj if (trim->tr_last_copybuf_win) { 411912f080e7Smrj dma->dp_pgmap[trim->tr_last_pidx].pm_cbaddr = 412012f080e7Smrj trim->tr_last_cbaddr; 412112f080e7Smrj #if !defined(__amd64) 412212f080e7Smrj dma->dp_pgmap[trim->tr_last_pidx].pm_kaddr = 412312f080e7Smrj trim->tr_last_kaddr; 412412f080e7Smrj #endif 412512f080e7Smrj } 412612f080e7Smrj } 412712f080e7Smrj 412812f080e7Smrj /* 412912f080e7Smrj * setup the cookie pointer to the first cookie in the window. setup 413012f080e7Smrj * our return values, then increment the cookie since we return the 413112f080e7Smrj * first cookie on the stack. 413212f080e7Smrj */ 413312f080e7Smrj hp->dmai_cookie = window->wd_first_cookie; 413412f080e7Smrj *offp = window->wd_offset; 413512f080e7Smrj *lenp = window->wd_size; 413612f080e7Smrj *ccountp = window->wd_cookie_cnt; 413712f080e7Smrj *cookiep = hp->dmai_cookie[0]; 413812f080e7Smrj hp->dmai_cookie++; 413912f080e7Smrj 414012f080e7Smrj #if !defined(__amd64) 414112f080e7Smrj /* re-map copybuf if required for this window */ 414212f080e7Smrj if (dma->dp_cb_remaping) { 414312f080e7Smrj /* 414412f080e7Smrj * calculate the page index into the buffer where this 414512f080e7Smrj * window starts. 414612f080e7Smrj */ 414712f080e7Smrj pidx = (sinfo->si_buf_offset + window->wd_offset) >> 414812f080e7Smrj MMU_PAGESHIFT; 414912f080e7Smrj ASSERT(pidx < sinfo->si_max_pages); 415012f080e7Smrj 415112f080e7Smrj /* 415212f080e7Smrj * the first page can get unmapped if it's shared with the 415312f080e7Smrj * previous window. Even if the rest of this window is already 415412f080e7Smrj * mapped in, we need to still check this one. 415512f080e7Smrj */ 415612f080e7Smrj pmap = &dma->dp_pgmap[pidx]; 415712f080e7Smrj if ((pmap->pm_uses_copybuf) && (pmap->pm_mapped == B_FALSE)) { 415812f080e7Smrj if (pmap->pm_pp != NULL) { 415912f080e7Smrj pmap->pm_mapped = B_TRUE; 416012f080e7Smrj i86_pp_map(pmap->pm_pp, pmap->pm_kaddr); 416112f080e7Smrj } else if (pmap->pm_vaddr != NULL) { 416212f080e7Smrj pmap->pm_mapped = B_TRUE; 416312f080e7Smrj i86_va_map(pmap->pm_vaddr, sinfo->si_asp, 416412f080e7Smrj pmap->pm_kaddr); 416512f080e7Smrj } 416612f080e7Smrj } 416712f080e7Smrj pidx++; 416812f080e7Smrj 416912f080e7Smrj /* map in the rest of the pages if required */ 417012f080e7Smrj if (window->wd_remap_copybuf) { 417112f080e7Smrj window->wd_remap_copybuf = B_FALSE; 417212f080e7Smrj 417312f080e7Smrj /* figure out many pages this window takes up */ 417412f080e7Smrj poff = (sinfo->si_buf_offset + window->wd_offset) & 417512f080e7Smrj MMU_PAGEOFFSET; 417612f080e7Smrj pcnt = mmu_btopr(window->wd_size + poff); 417712f080e7Smrj ASSERT(((pidx - 1) + pcnt) <= sinfo->si_max_pages); 417812f080e7Smrj 417912f080e7Smrj /* map pages which require it */ 418012f080e7Smrj for (i = 1; i < pcnt; i++) { 418112f080e7Smrj pmap = &dma->dp_pgmap[pidx]; 418212f080e7Smrj if (pmap->pm_uses_copybuf) { 418312f080e7Smrj ASSERT(pmap->pm_mapped == B_FALSE); 418412f080e7Smrj if (pmap->pm_pp != NULL) { 418512f080e7Smrj pmap->pm_mapped = B_TRUE; 418612f080e7Smrj i86_pp_map(pmap->pm_pp, 418712f080e7Smrj pmap->pm_kaddr); 418812f080e7Smrj } else if (pmap->pm_vaddr != NULL) { 418912f080e7Smrj pmap->pm_mapped = B_TRUE; 419012f080e7Smrj i86_va_map(pmap->pm_vaddr, 419112f080e7Smrj sinfo->si_asp, 419212f080e7Smrj pmap->pm_kaddr); 419312f080e7Smrj } 419412f080e7Smrj } 419512f080e7Smrj pidx++; 419612f080e7Smrj } 419712f080e7Smrj } 419812f080e7Smrj } 419912f080e7Smrj #endif 420012f080e7Smrj 420112f080e7Smrj /* if the new window uses the copy buffer, sync it for the device */ 420212f080e7Smrj if ((window->wd_dosync) && (hp->dmai_rflags & DDI_DMA_WRITE)) { 420312f080e7Smrj (void) rootnex_dma_sync(dip, rdip, handle, 0, 0, 420412f080e7Smrj DDI_DMA_SYNC_FORDEV); 420512f080e7Smrj } 420612f080e7Smrj 420712f080e7Smrj return (DDI_SUCCESS); 420812f080e7Smrj } 420912f080e7Smrj 421012f080e7Smrj 421112f080e7Smrj 421212f080e7Smrj /* 421312f080e7Smrj * ************************ 421412f080e7Smrj * obsoleted dma routines 421512f080e7Smrj * ************************ 421612f080e7Smrj */ 421712f080e7Smrj 421812f080e7Smrj /* 421912f080e7Smrj * rootnex_dma_map() 422012f080e7Smrj * called from ddi_dma_setup() 422112f080e7Smrj */ 422212f080e7Smrj /* ARGSUSED */ 422312f080e7Smrj static int 422412f080e7Smrj rootnex_dma_map(dev_info_t *dip, dev_info_t *rdip, struct ddi_dma_req *dmareq, 422512f080e7Smrj ddi_dma_handle_t *handlep) 422612f080e7Smrj { 422712f080e7Smrj #if defined(__amd64) 422812f080e7Smrj /* 422912f080e7Smrj * this interface is not supported in 64-bit x86 kernel. See comment in 423012f080e7Smrj * rootnex_dma_mctl() 423112f080e7Smrj */ 423212f080e7Smrj return (DDI_DMA_NORESOURCES); 423312f080e7Smrj 423412f080e7Smrj #else /* 32-bit x86 kernel */ 423512f080e7Smrj ddi_dma_handle_t *lhandlep; 423612f080e7Smrj ddi_dma_handle_t lhandle; 423712f080e7Smrj ddi_dma_cookie_t cookie; 423812f080e7Smrj ddi_dma_attr_t dma_attr; 423912f080e7Smrj ddi_dma_lim_t *dma_lim; 424012f080e7Smrj uint_t ccnt; 424112f080e7Smrj int e; 424212f080e7Smrj 424312f080e7Smrj 424412f080e7Smrj /* 424512f080e7Smrj * if the driver is just testing to see if it's possible to do the bind, 424612f080e7Smrj * we'll use local state. Otherwise, use the handle pointer passed in. 424712f080e7Smrj */ 424812f080e7Smrj if (handlep == NULL) { 424912f080e7Smrj lhandlep = &lhandle; 425012f080e7Smrj } else { 425112f080e7Smrj lhandlep = handlep; 425212f080e7Smrj } 425312f080e7Smrj 425412f080e7Smrj /* convert the limit structure to a dma_attr one */ 425512f080e7Smrj dma_lim = dmareq->dmar_limits; 425612f080e7Smrj dma_attr.dma_attr_version = DMA_ATTR_V0; 425712f080e7Smrj dma_attr.dma_attr_addr_lo = dma_lim->dlim_addr_lo; 425812f080e7Smrj dma_attr.dma_attr_addr_hi = dma_lim->dlim_addr_hi; 425912f080e7Smrj dma_attr.dma_attr_minxfer = dma_lim->dlim_minxfer; 426012f080e7Smrj dma_attr.dma_attr_seg = dma_lim->dlim_adreg_max; 426112f080e7Smrj dma_attr.dma_attr_count_max = dma_lim->dlim_ctreg_max; 426212f080e7Smrj dma_attr.dma_attr_granular = dma_lim->dlim_granular; 426312f080e7Smrj dma_attr.dma_attr_sgllen = dma_lim->dlim_sgllen; 426412f080e7Smrj dma_attr.dma_attr_maxxfer = dma_lim->dlim_reqsize; 426512f080e7Smrj dma_attr.dma_attr_burstsizes = dma_lim->dlim_burstsizes; 426612f080e7Smrj dma_attr.dma_attr_align = MMU_PAGESIZE; 426712f080e7Smrj dma_attr.dma_attr_flags = 0; 426812f080e7Smrj 426912f080e7Smrj e = rootnex_dma_allochdl(dip, rdip, &dma_attr, dmareq->dmar_fp, 427012f080e7Smrj dmareq->dmar_arg, lhandlep); 427112f080e7Smrj if (e != DDI_SUCCESS) { 427212f080e7Smrj return (e); 427312f080e7Smrj } 427412f080e7Smrj 427512f080e7Smrj e = rootnex_dma_bindhdl(dip, rdip, *lhandlep, dmareq, &cookie, &ccnt); 427612f080e7Smrj if ((e != DDI_DMA_MAPPED) && (e != DDI_DMA_PARTIAL_MAP)) { 427712f080e7Smrj (void) rootnex_dma_freehdl(dip, rdip, *lhandlep); 427812f080e7Smrj return (e); 427912f080e7Smrj } 428012f080e7Smrj 428112f080e7Smrj /* 428212f080e7Smrj * if the driver is just testing to see if it's possible to do the bind, 428312f080e7Smrj * free up the local state and return the result. 428412f080e7Smrj */ 428512f080e7Smrj if (handlep == NULL) { 428612f080e7Smrj (void) rootnex_dma_unbindhdl(dip, rdip, *lhandlep); 428712f080e7Smrj (void) rootnex_dma_freehdl(dip, rdip, *lhandlep); 428812f080e7Smrj if (e == DDI_DMA_MAPPED) { 428912f080e7Smrj return (DDI_DMA_MAPOK); 429012f080e7Smrj } else { 429112f080e7Smrj return (DDI_DMA_NOMAPPING); 429212f080e7Smrj } 429312f080e7Smrj } 429412f080e7Smrj 429512f080e7Smrj return (e); 429612f080e7Smrj #endif /* defined(__amd64) */ 429712f080e7Smrj } 429812f080e7Smrj 429912f080e7Smrj 430012f080e7Smrj /* 430112f080e7Smrj * rootnex_dma_mctl() 430212f080e7Smrj * 430312f080e7Smrj */ 430412f080e7Smrj /* ARGSUSED */ 430512f080e7Smrj static int 430612f080e7Smrj rootnex_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 430712f080e7Smrj enum ddi_dma_ctlops request, off_t *offp, size_t *lenp, caddr_t *objpp, 430812f080e7Smrj uint_t cache_flags) 430912f080e7Smrj { 431012f080e7Smrj #if defined(__amd64) 431112f080e7Smrj /* 431212f080e7Smrj * DDI_DMA_SMEM_ALLOC & DDI_DMA_IOPB_ALLOC we're changed to have a 431312f080e7Smrj * common implementation in genunix, so they no longer have x86 431412f080e7Smrj * specific functionality which called into dma_ctl. 431512f080e7Smrj * 431612f080e7Smrj * The rest of the obsoleted interfaces were never supported in the 431712f080e7Smrj * 64-bit x86 kernel. For s10, the obsoleted DDI_DMA_SEGTOC interface 431812f080e7Smrj * was not ported to the x86 64-bit kernel do to serious x86 rootnex 431912f080e7Smrj * implementation issues. 432012f080e7Smrj * 432112f080e7Smrj * If you can't use DDI_DMA_SEGTOC; DDI_DMA_NEXTSEG, DDI_DMA_FREE, and 432212f080e7Smrj * DDI_DMA_NEXTWIN are useless since you can get to the cookie, so we 432312f080e7Smrj * reflect that now too... 432412f080e7Smrj * 432512f080e7Smrj * Even though we fixed the pointer problem in DDI_DMA_SEGTOC, we are 432612f080e7Smrj * not going to put this functionality into the 64-bit x86 kernel now. 432712f080e7Smrj * It wasn't ported to the 64-bit kernel for s10, no reason to change 432812f080e7Smrj * that in a future release. 432912f080e7Smrj */ 433012f080e7Smrj return (DDI_FAILURE); 433112f080e7Smrj 433212f080e7Smrj #else /* 32-bit x86 kernel */ 433312f080e7Smrj ddi_dma_cookie_t lcookie; 433412f080e7Smrj ddi_dma_cookie_t *cookie; 433512f080e7Smrj rootnex_window_t *window; 433612f080e7Smrj ddi_dma_impl_t *hp; 433712f080e7Smrj rootnex_dma_t *dma; 433812f080e7Smrj uint_t nwin; 433912f080e7Smrj uint_t ccnt; 434012f080e7Smrj size_t len; 434112f080e7Smrj off_t off; 434212f080e7Smrj int e; 434312f080e7Smrj 434412f080e7Smrj 434512f080e7Smrj /* 434612f080e7Smrj * DDI_DMA_SEGTOC, DDI_DMA_NEXTSEG, and DDI_DMA_NEXTWIN are a little 434712f080e7Smrj * hacky since were optimizing for the current interfaces and so we can 434812f080e7Smrj * cleanup the mess in genunix. Hopefully we will remove the this 434912f080e7Smrj * obsoleted routines someday soon. 435012f080e7Smrj */ 435112f080e7Smrj 435212f080e7Smrj switch (request) { 435312f080e7Smrj 435412f080e7Smrj case DDI_DMA_SEGTOC: /* ddi_dma_segtocookie() */ 435512f080e7Smrj hp = (ddi_dma_impl_t *)handle; 435612f080e7Smrj cookie = (ddi_dma_cookie_t *)objpp; 435712f080e7Smrj 435812f080e7Smrj /* 435912f080e7Smrj * convert segment to cookie. We don't distinguish between the 436012f080e7Smrj * two :-) 436112f080e7Smrj */ 436212f080e7Smrj *cookie = *hp->dmai_cookie; 436312f080e7Smrj *lenp = cookie->dmac_size; 436412f080e7Smrj *offp = cookie->dmac_type & ~ROOTNEX_USES_COPYBUF; 436512f080e7Smrj return (DDI_SUCCESS); 436612f080e7Smrj 436712f080e7Smrj case DDI_DMA_NEXTSEG: /* ddi_dma_nextseg() */ 436812f080e7Smrj hp = (ddi_dma_impl_t *)handle; 436912f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 437012f080e7Smrj 437112f080e7Smrj if ((*lenp != NULL) && ((uintptr_t)*lenp != (uintptr_t)hp)) { 437212f080e7Smrj return (DDI_DMA_STALE); 437312f080e7Smrj } 437412f080e7Smrj 437512f080e7Smrj /* handle the case where we don't have any windows */ 437612f080e7Smrj if (dma->dp_window == NULL) { 437712f080e7Smrj /* 437812f080e7Smrj * if seg == NULL, and we don't have any windows, 437912f080e7Smrj * return the first cookie in the sgl. 438012f080e7Smrj */ 438112f080e7Smrj if (*lenp == NULL) { 438212f080e7Smrj dma->dp_current_cookie = 0; 438312f080e7Smrj hp->dmai_cookie = dma->dp_cookies; 438412f080e7Smrj *objpp = (caddr_t)handle; 438512f080e7Smrj return (DDI_SUCCESS); 438612f080e7Smrj 438712f080e7Smrj /* if we have more cookies, go to the next cookie */ 438812f080e7Smrj } else { 438912f080e7Smrj if ((dma->dp_current_cookie + 1) >= 439012f080e7Smrj dma->dp_sglinfo.si_sgl_size) { 439112f080e7Smrj return (DDI_DMA_DONE); 439212f080e7Smrj } 439312f080e7Smrj dma->dp_current_cookie++; 439412f080e7Smrj hp->dmai_cookie++; 439512f080e7Smrj return (DDI_SUCCESS); 439612f080e7Smrj } 439712f080e7Smrj } 439812f080e7Smrj 439912f080e7Smrj /* We have one or more windows */ 440012f080e7Smrj window = &dma->dp_window[dma->dp_current_win]; 440112f080e7Smrj 440212f080e7Smrj /* 440312f080e7Smrj * if seg == NULL, return the first cookie in the current 440412f080e7Smrj * window 440512f080e7Smrj */ 440612f080e7Smrj if (*lenp == NULL) { 440712f080e7Smrj dma->dp_current_cookie = 0; 4408cf4e9a1dSmrj hp->dmai_cookie = window->wd_first_cookie; 440912f080e7Smrj 441012f080e7Smrj /* 441112f080e7Smrj * go to the next cookie in the window then see if we done with 441212f080e7Smrj * this window. 441312f080e7Smrj */ 441412f080e7Smrj } else { 441512f080e7Smrj if ((dma->dp_current_cookie + 1) >= 441612f080e7Smrj window->wd_cookie_cnt) { 441712f080e7Smrj return (DDI_DMA_DONE); 441812f080e7Smrj } 441912f080e7Smrj dma->dp_current_cookie++; 442012f080e7Smrj hp->dmai_cookie++; 442112f080e7Smrj } 442212f080e7Smrj *objpp = (caddr_t)handle; 442312f080e7Smrj return (DDI_SUCCESS); 442412f080e7Smrj 442512f080e7Smrj case DDI_DMA_NEXTWIN: /* ddi_dma_nextwin() */ 442612f080e7Smrj hp = (ddi_dma_impl_t *)handle; 442712f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 442812f080e7Smrj 442912f080e7Smrj if ((*offp != NULL) && ((uintptr_t)*offp != (uintptr_t)hp)) { 443012f080e7Smrj return (DDI_DMA_STALE); 443112f080e7Smrj } 443212f080e7Smrj 443312f080e7Smrj /* if win == NULL, return the first window in the bind */ 443412f080e7Smrj if (*offp == NULL) { 443512f080e7Smrj nwin = 0; 443612f080e7Smrj 443712f080e7Smrj /* 443812f080e7Smrj * else, go to the next window then see if we're done with all 443912f080e7Smrj * the windows. 444012f080e7Smrj */ 444112f080e7Smrj } else { 444212f080e7Smrj nwin = dma->dp_current_win + 1; 444312f080e7Smrj if (nwin >= hp->dmai_nwin) { 444412f080e7Smrj return (DDI_DMA_DONE); 444512f080e7Smrj } 444612f080e7Smrj } 444712f080e7Smrj 444812f080e7Smrj /* switch to the next window */ 444912f080e7Smrj e = rootnex_dma_win(dip, rdip, handle, nwin, &off, &len, 445012f080e7Smrj &lcookie, &ccnt); 445112f080e7Smrj ASSERT(e == DDI_SUCCESS); 445212f080e7Smrj if (e != DDI_SUCCESS) { 445312f080e7Smrj return (DDI_DMA_STALE); 445412f080e7Smrj } 445512f080e7Smrj 445612f080e7Smrj /* reset the cookie back to the first cookie in the window */ 445712f080e7Smrj if (dma->dp_window != NULL) { 445812f080e7Smrj window = &dma->dp_window[dma->dp_current_win]; 445912f080e7Smrj hp->dmai_cookie = window->wd_first_cookie; 446012f080e7Smrj } else { 446112f080e7Smrj hp->dmai_cookie = dma->dp_cookies; 446212f080e7Smrj } 446312f080e7Smrj 446412f080e7Smrj *objpp = (caddr_t)handle; 446512f080e7Smrj return (DDI_SUCCESS); 446612f080e7Smrj 446712f080e7Smrj case DDI_DMA_FREE: /* ddi_dma_free() */ 446812f080e7Smrj (void) rootnex_dma_unbindhdl(dip, rdip, handle); 446912f080e7Smrj (void) rootnex_dma_freehdl(dip, rdip, handle); 447012f080e7Smrj if (rootnex_state->r_dvma_call_list_id) { 447112f080e7Smrj ddi_run_callback(&rootnex_state->r_dvma_call_list_id); 447212f080e7Smrj } 447312f080e7Smrj return (DDI_SUCCESS); 447412f080e7Smrj 447512f080e7Smrj case DDI_DMA_IOPB_ALLOC: /* get contiguous DMA-able memory */ 447612f080e7Smrj case DDI_DMA_SMEM_ALLOC: /* get contiguous DMA-able memory */ 447712f080e7Smrj /* should never get here, handled in genunix */ 447812f080e7Smrj ASSERT(0); 447912f080e7Smrj return (DDI_FAILURE); 448012f080e7Smrj 448112f080e7Smrj case DDI_DMA_KVADDR: 448212f080e7Smrj case DDI_DMA_GETERR: 448312f080e7Smrj case DDI_DMA_COFF: 448412f080e7Smrj return (DDI_FAILURE); 448512f080e7Smrj } 448612f080e7Smrj 448712f080e7Smrj return (DDI_FAILURE); 448812f080e7Smrj #endif /* defined(__amd64) */ 44897c478bd9Sstevel@tonic-gate } 44907aec1d6eScindi 449100d0963fSdilpreet 449200d0963fSdilpreet /* 449300d0963fSdilpreet * ********* 449400d0963fSdilpreet * FMA Code 449500d0963fSdilpreet * ********* 449600d0963fSdilpreet */ 449700d0963fSdilpreet 449800d0963fSdilpreet /* 449900d0963fSdilpreet * rootnex_fm_init() 450000d0963fSdilpreet * FMA init busop 450100d0963fSdilpreet */ 45027aec1d6eScindi /* ARGSUSED */ 45037aec1d6eScindi static int 450400d0963fSdilpreet rootnex_fm_init(dev_info_t *dip, dev_info_t *tdip, int tcap, 450500d0963fSdilpreet ddi_iblock_cookie_t *ibc) 45067aec1d6eScindi { 450700d0963fSdilpreet *ibc = rootnex_state->r_err_ibc; 450800d0963fSdilpreet 450900d0963fSdilpreet return (ddi_system_fmcap); 451000d0963fSdilpreet } 451100d0963fSdilpreet 451200d0963fSdilpreet /* 451300d0963fSdilpreet * rootnex_dma_check() 451400d0963fSdilpreet * Function called after a dma fault occurred to find out whether the 451500d0963fSdilpreet * fault address is associated with a driver that is able to handle faults 451600d0963fSdilpreet * and recover from faults. 451700d0963fSdilpreet */ 451800d0963fSdilpreet /* ARGSUSED */ 451900d0963fSdilpreet static int 452000d0963fSdilpreet rootnex_dma_check(dev_info_t *dip, const void *handle, const void *addr, 452100d0963fSdilpreet const void *not_used) 452200d0963fSdilpreet { 452300d0963fSdilpreet rootnex_window_t *window; 452400d0963fSdilpreet uint64_t start_addr; 452500d0963fSdilpreet uint64_t fault_addr; 452600d0963fSdilpreet ddi_dma_impl_t *hp; 452700d0963fSdilpreet rootnex_dma_t *dma; 452800d0963fSdilpreet uint64_t end_addr; 452900d0963fSdilpreet size_t csize; 453000d0963fSdilpreet int i; 453100d0963fSdilpreet int j; 453200d0963fSdilpreet 453300d0963fSdilpreet 453400d0963fSdilpreet /* The driver has to set DDI_DMA_FLAGERR to recover from dma faults */ 453500d0963fSdilpreet hp = (ddi_dma_impl_t *)handle; 453600d0963fSdilpreet ASSERT(hp); 453700d0963fSdilpreet 453800d0963fSdilpreet dma = (rootnex_dma_t *)hp->dmai_private; 453900d0963fSdilpreet 454000d0963fSdilpreet /* Get the address that we need to search for */ 454100d0963fSdilpreet fault_addr = *(uint64_t *)addr; 454200d0963fSdilpreet 454300d0963fSdilpreet /* 454400d0963fSdilpreet * if we don't have any windows, we can just walk through all the 454500d0963fSdilpreet * cookies. 454600d0963fSdilpreet */ 454700d0963fSdilpreet if (dma->dp_window == NULL) { 454800d0963fSdilpreet /* for each cookie */ 454900d0963fSdilpreet for (i = 0; i < dma->dp_sglinfo.si_sgl_size; i++) { 455000d0963fSdilpreet /* 455100d0963fSdilpreet * if the faulted address is within the physical address 455200d0963fSdilpreet * range of the cookie, return DDI_FM_NONFATAL. 455300d0963fSdilpreet */ 455400d0963fSdilpreet if ((fault_addr >= dma->dp_cookies[i].dmac_laddress) && 455500d0963fSdilpreet (fault_addr <= (dma->dp_cookies[i].dmac_laddress + 455600d0963fSdilpreet dma->dp_cookies[i].dmac_size))) { 455700d0963fSdilpreet return (DDI_FM_NONFATAL); 455800d0963fSdilpreet } 455900d0963fSdilpreet } 456000d0963fSdilpreet 456100d0963fSdilpreet /* fault_addr not within this DMA handle */ 456200d0963fSdilpreet return (DDI_FM_UNKNOWN); 456300d0963fSdilpreet } 456400d0963fSdilpreet 456500d0963fSdilpreet /* we have mutiple windows, walk through each window */ 456600d0963fSdilpreet for (i = 0; i < hp->dmai_nwin; i++) { 456700d0963fSdilpreet window = &dma->dp_window[i]; 456800d0963fSdilpreet 456900d0963fSdilpreet /* Go through all the cookies in the window */ 457000d0963fSdilpreet for (j = 0; j < window->wd_cookie_cnt; j++) { 457100d0963fSdilpreet 457200d0963fSdilpreet start_addr = window->wd_first_cookie[j].dmac_laddress; 457300d0963fSdilpreet csize = window->wd_first_cookie[j].dmac_size; 457400d0963fSdilpreet 457500d0963fSdilpreet /* 457600d0963fSdilpreet * if we are trimming the first cookie in the window, 457700d0963fSdilpreet * and this is the first cookie, adjust the start 457800d0963fSdilpreet * address and size of the cookie to account for the 457900d0963fSdilpreet * trim. 458000d0963fSdilpreet */ 458100d0963fSdilpreet if (window->wd_trim.tr_trim_first && (j == 0)) { 458200d0963fSdilpreet start_addr = window->wd_trim.tr_first_paddr; 458300d0963fSdilpreet csize = window->wd_trim.tr_first_size; 458400d0963fSdilpreet } 458500d0963fSdilpreet 458600d0963fSdilpreet /* 458700d0963fSdilpreet * if we are trimming the last cookie in the window, 458800d0963fSdilpreet * and this is the last cookie, adjust the start 458900d0963fSdilpreet * address and size of the cookie to account for the 459000d0963fSdilpreet * trim. 459100d0963fSdilpreet */ 459200d0963fSdilpreet if (window->wd_trim.tr_trim_last && 459300d0963fSdilpreet (j == (window->wd_cookie_cnt - 1))) { 459400d0963fSdilpreet start_addr = window->wd_trim.tr_last_paddr; 459500d0963fSdilpreet csize = window->wd_trim.tr_last_size; 459600d0963fSdilpreet } 459700d0963fSdilpreet 459800d0963fSdilpreet end_addr = start_addr + csize; 459900d0963fSdilpreet 460000d0963fSdilpreet /* 460100d0963fSdilpreet * if the faulted address is within the physical address 460200d0963fSdilpreet * range of the cookie, return DDI_FM_NONFATAL. 460300d0963fSdilpreet */ 460400d0963fSdilpreet if ((fault_addr >= start_addr) && 460500d0963fSdilpreet (fault_addr <= end_addr)) { 460600d0963fSdilpreet return (DDI_FM_NONFATAL); 460700d0963fSdilpreet } 460800d0963fSdilpreet } 460900d0963fSdilpreet } 461000d0963fSdilpreet 461100d0963fSdilpreet /* fault_addr not within this DMA handle */ 461200d0963fSdilpreet return (DDI_FM_UNKNOWN); 46137aec1d6eScindi } 4614