17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 57c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 67c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 77c478bd9Sstevel@tonic-gate * with the License. 87c478bd9Sstevel@tonic-gate * 97c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 107c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 117c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 127c478bd9Sstevel@tonic-gate * and limitations under the License. 137c478bd9Sstevel@tonic-gate * 147c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 157c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 167c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 177c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 187c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 197c478bd9Sstevel@tonic-gate * 207c478bd9Sstevel@tonic-gate * CDDL HEADER END 217c478bd9Sstevel@tonic-gate */ 227c478bd9Sstevel@tonic-gate /* 238a552b2dScth * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 247c478bd9Sstevel@tonic-gate * Use is subject to license terms. 257c478bd9Sstevel@tonic-gate */ 267c478bd9Sstevel@tonic-gate 277c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 287c478bd9Sstevel@tonic-gate 297c478bd9Sstevel@tonic-gate /* 3012f080e7Smrj * x86 root nexus driver 317c478bd9Sstevel@tonic-gate */ 327c478bd9Sstevel@tonic-gate 337c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h> 347c478bd9Sstevel@tonic-gate #include <sys/conf.h> 357c478bd9Sstevel@tonic-gate #include <sys/autoconf.h> 367c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h> 377c478bd9Sstevel@tonic-gate #include <sys/debug.h> 387c478bd9Sstevel@tonic-gate #include <sys/psw.h> 397c478bd9Sstevel@tonic-gate #include <sys/ddidmareq.h> 407c478bd9Sstevel@tonic-gate #include <sys/promif.h> 417c478bd9Sstevel@tonic-gate #include <sys/devops.h> 427c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 437c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 447c478bd9Sstevel@tonic-gate #include <vm/seg.h> 457c478bd9Sstevel@tonic-gate #include <vm/seg_kmem.h> 467c478bd9Sstevel@tonic-gate #include <vm/seg_dev.h> 477c478bd9Sstevel@tonic-gate #include <sys/vmem.h> 487c478bd9Sstevel@tonic-gate #include <sys/mman.h> 497c478bd9Sstevel@tonic-gate #include <vm/hat.h> 507c478bd9Sstevel@tonic-gate #include <vm/as.h> 517c478bd9Sstevel@tonic-gate #include <vm/page.h> 527c478bd9Sstevel@tonic-gate #include <sys/avintr.h> 537c478bd9Sstevel@tonic-gate #include <sys/errno.h> 547c478bd9Sstevel@tonic-gate #include <sys/modctl.h> 557c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 567c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 577c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 587a364d25Sschwartz #include <sys/mach_intr.h> 597c478bd9Sstevel@tonic-gate #include <sys/psm.h> 607c478bd9Sstevel@tonic-gate #include <sys/ontrap.h> 6112f080e7Smrj #include <sys/atomic.h> 6212f080e7Smrj #include <sys/sdt.h> 6312f080e7Smrj #include <sys/rootnex.h> 6412f080e7Smrj #include <vm/hat_i86.h> 657c478bd9Sstevel@tonic-gate 6612f080e7Smrj /* 6712f080e7Smrj * enable/disable extra checking of function parameters. Useful for debugging 6812f080e7Smrj * drivers. 6912f080e7Smrj */ 7012f080e7Smrj #ifdef DEBUG 7112f080e7Smrj int rootnex_alloc_check_parms = 1; 7212f080e7Smrj int rootnex_bind_check_parms = 1; 7312f080e7Smrj int rootnex_bind_check_inuse = 1; 7412f080e7Smrj int rootnex_unbind_verify_buffer = 0; 7512f080e7Smrj int rootnex_sync_check_parms = 1; 7612f080e7Smrj #else 7712f080e7Smrj int rootnex_alloc_check_parms = 0; 7812f080e7Smrj int rootnex_bind_check_parms = 0; 7912f080e7Smrj int rootnex_bind_check_inuse = 0; 8012f080e7Smrj int rootnex_unbind_verify_buffer = 0; 8112f080e7Smrj int rootnex_sync_check_parms = 0; 8212f080e7Smrj #endif 837c478bd9Sstevel@tonic-gate 84*7aec1d6eScindi /* Master Abort and Target Abort panic flag */ 85*7aec1d6eScindi int rootnex_fm_ma_ta_panic_flag = 0; 86*7aec1d6eScindi 8712f080e7Smrj /* Semi-temporary patchables to phase in bug fixes, test drivers, etc. */ 887c478bd9Sstevel@tonic-gate int rootnex_bind_fail = 1; 897c478bd9Sstevel@tonic-gate int rootnex_bind_warn = 1; 907c478bd9Sstevel@tonic-gate uint8_t *rootnex_warn_list; 917c478bd9Sstevel@tonic-gate /* bitmasks for rootnex_warn_list. Up to 8 different warnings with uint8_t */ 927c478bd9Sstevel@tonic-gate #define ROOTNEX_BIND_WARNING (0x1 << 0) 937c478bd9Sstevel@tonic-gate 947c478bd9Sstevel@tonic-gate /* 9512f080e7Smrj * revert back to old broken behavior of always sync'ing entire copy buffer. 9612f080e7Smrj * This is useful if be have a buggy driver which doesn't correctly pass in 9712f080e7Smrj * the offset and size into ddi_dma_sync(). 987c478bd9Sstevel@tonic-gate */ 9912f080e7Smrj int rootnex_sync_ignore_params = 0; 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate /* 10212f080e7Smrj * maximum size that we will allow for a copy buffer. Can be patched on the 10312f080e7Smrj * fly 1047c478bd9Sstevel@tonic-gate */ 10512f080e7Smrj size_t rootnex_max_copybuf_size = 0x100000; 1067c478bd9Sstevel@tonic-gate 1077c478bd9Sstevel@tonic-gate /* 10812f080e7Smrj * For the 64-bit kernel, pre-alloc enough cookies for a 256K buffer plus 1 10912f080e7Smrj * page for alignment. For the 32-bit kernel, pre-alloc enough cookies for a 11012f080e7Smrj * 64K buffer plus 1 page for alignment (we have less kernel space in a 32-bit 11112f080e7Smrj * kernel). Allocate enough windows to handle a 256K buffer w/ at least 65 11212f080e7Smrj * sgllen DMA engine, and enough copybuf buffer state pages to handle 2 pages 11312f080e7Smrj * (< 8K). We will still need to allocate the copy buffer during bind though 11412f080e7Smrj * (if we need one). These can only be modified in /etc/system before rootnex 11512f080e7Smrj * attach. 1167c478bd9Sstevel@tonic-gate */ 11712f080e7Smrj #if defined(__amd64) 11812f080e7Smrj int rootnex_prealloc_cookies = 65; 11912f080e7Smrj int rootnex_prealloc_windows = 4; 12012f080e7Smrj int rootnex_prealloc_copybuf = 2; 12112f080e7Smrj #else 12212f080e7Smrj int rootnex_prealloc_cookies = 33; 12312f080e7Smrj int rootnex_prealloc_windows = 4; 12412f080e7Smrj int rootnex_prealloc_copybuf = 2; 12512f080e7Smrj #endif 1267c478bd9Sstevel@tonic-gate 12712f080e7Smrj /* driver global state */ 12812f080e7Smrj static rootnex_state_t *rootnex_state; 12912f080e7Smrj 13012f080e7Smrj /* shortcut to rootnex counters */ 13112f080e7Smrj static uint64_t *rootnex_cnt; 1327c478bd9Sstevel@tonic-gate 1337c478bd9Sstevel@tonic-gate /* 13412f080e7Smrj * XXX - does x86 even need these or are they left over from the SPARC days? 1357c478bd9Sstevel@tonic-gate */ 13612f080e7Smrj /* statically defined integer/boolean properties for the root node */ 13712f080e7Smrj static rootnex_intprop_t rootnex_intprp[] = { 13812f080e7Smrj { "PAGESIZE", PAGESIZE }, 13912f080e7Smrj { "MMU_PAGESIZE", MMU_PAGESIZE }, 14012f080e7Smrj { "MMU_PAGEOFFSET", MMU_PAGEOFFSET }, 14112f080e7Smrj { DDI_RELATIVE_ADDRESSING, 1 }, 14212f080e7Smrj }; 14312f080e7Smrj #define NROOT_INTPROPS (sizeof (rootnex_intprp) / sizeof (rootnex_intprop_t)) 1447c478bd9Sstevel@tonic-gate 1457c478bd9Sstevel@tonic-gate 14612f080e7Smrj static struct cb_ops rootnex_cb_ops = { 14712f080e7Smrj nodev, /* open */ 14812f080e7Smrj nodev, /* close */ 14912f080e7Smrj nodev, /* strategy */ 15012f080e7Smrj nodev, /* print */ 15112f080e7Smrj nodev, /* dump */ 15212f080e7Smrj nodev, /* read */ 15312f080e7Smrj nodev, /* write */ 15412f080e7Smrj nodev, /* ioctl */ 15512f080e7Smrj nodev, /* devmap */ 15612f080e7Smrj nodev, /* mmap */ 15712f080e7Smrj nodev, /* segmap */ 15812f080e7Smrj nochpoll, /* chpoll */ 15912f080e7Smrj ddi_prop_op, /* cb_prop_op */ 16012f080e7Smrj NULL, /* struct streamtab */ 16112f080e7Smrj D_NEW | D_MP | D_HOTPLUG, /* compatibility flags */ 16212f080e7Smrj CB_REV, /* Rev */ 16312f080e7Smrj nodev, /* cb_aread */ 16412f080e7Smrj nodev /* cb_awrite */ 16512f080e7Smrj }; 1667c478bd9Sstevel@tonic-gate 16712f080e7Smrj static int rootnex_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 1687c478bd9Sstevel@tonic-gate off_t offset, off_t len, caddr_t *vaddrp); 16912f080e7Smrj static int rootnex_map_fault(dev_info_t *dip, dev_info_t *rdip, 1707c478bd9Sstevel@tonic-gate struct hat *hat, struct seg *seg, caddr_t addr, 1717c478bd9Sstevel@tonic-gate struct devpage *dp, pfn_t pfn, uint_t prot, uint_t lock); 17212f080e7Smrj static int rootnex_dma_map(dev_info_t *dip, dev_info_t *rdip, 1737c478bd9Sstevel@tonic-gate struct ddi_dma_req *dmareq, ddi_dma_handle_t *handlep); 17412f080e7Smrj static int rootnex_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 17512f080e7Smrj ddi_dma_attr_t *attr, int (*waitfp)(caddr_t), caddr_t arg, 17612f080e7Smrj ddi_dma_handle_t *handlep); 17712f080e7Smrj static int rootnex_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, 17812f080e7Smrj ddi_dma_handle_t handle); 17912f080e7Smrj static int rootnex_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 18012f080e7Smrj ddi_dma_handle_t handle, struct ddi_dma_req *dmareq, 18112f080e7Smrj ddi_dma_cookie_t *cookiep, uint_t *ccountp); 18212f080e7Smrj static int rootnex_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 18312f080e7Smrj ddi_dma_handle_t handle); 18412f080e7Smrj static int rootnex_dma_sync(dev_info_t *dip, dev_info_t *rdip, 18512f080e7Smrj ddi_dma_handle_t handle, off_t off, size_t len, uint_t cache_flags); 18612f080e7Smrj static int rootnex_dma_win(dev_info_t *dip, dev_info_t *rdip, 18712f080e7Smrj ddi_dma_handle_t handle, uint_t win, off_t *offp, size_t *lenp, 18812f080e7Smrj ddi_dma_cookie_t *cookiep, uint_t *ccountp); 18912f080e7Smrj static int rootnex_dma_mctl(dev_info_t *dip, dev_info_t *rdip, 1907c478bd9Sstevel@tonic-gate ddi_dma_handle_t handle, enum ddi_dma_ctlops request, 1917c478bd9Sstevel@tonic-gate off_t *offp, size_t *lenp, caddr_t *objp, uint_t cache_flags); 19212f080e7Smrj static int rootnex_ctlops(dev_info_t *dip, dev_info_t *rdip, 19312f080e7Smrj ddi_ctl_enum_t ctlop, void *arg, void *result); 19412f080e7Smrj static int rootnex_intr_ops(dev_info_t *pdip, dev_info_t *rdip, 19512f080e7Smrj ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 1967c478bd9Sstevel@tonic-gate 1977c478bd9Sstevel@tonic-gate 1987c478bd9Sstevel@tonic-gate static struct bus_ops rootnex_bus_ops = { 1997c478bd9Sstevel@tonic-gate BUSO_REV, 2007c478bd9Sstevel@tonic-gate rootnex_map, 2017c478bd9Sstevel@tonic-gate NULL, 2027c478bd9Sstevel@tonic-gate NULL, 2037c478bd9Sstevel@tonic-gate NULL, 2047c478bd9Sstevel@tonic-gate rootnex_map_fault, 2057c478bd9Sstevel@tonic-gate rootnex_dma_map, 2067c478bd9Sstevel@tonic-gate rootnex_dma_allochdl, 2077c478bd9Sstevel@tonic-gate rootnex_dma_freehdl, 2087c478bd9Sstevel@tonic-gate rootnex_dma_bindhdl, 2097c478bd9Sstevel@tonic-gate rootnex_dma_unbindhdl, 21012f080e7Smrj rootnex_dma_sync, 2117c478bd9Sstevel@tonic-gate rootnex_dma_win, 2127c478bd9Sstevel@tonic-gate rootnex_dma_mctl, 2137c478bd9Sstevel@tonic-gate rootnex_ctlops, 2147c478bd9Sstevel@tonic-gate ddi_bus_prop_op, 2157c478bd9Sstevel@tonic-gate i_ddi_rootnex_get_eventcookie, 2167c478bd9Sstevel@tonic-gate i_ddi_rootnex_add_eventcall, 2177c478bd9Sstevel@tonic-gate i_ddi_rootnex_remove_eventcall, 2187c478bd9Sstevel@tonic-gate i_ddi_rootnex_post_event, 2197c478bd9Sstevel@tonic-gate 0, /* bus_intr_ctl */ 2207c478bd9Sstevel@tonic-gate 0, /* bus_config */ 2217c478bd9Sstevel@tonic-gate 0, /* bus_unconfig */ 2227c478bd9Sstevel@tonic-gate NULL, /* bus_fm_init */ 2237c478bd9Sstevel@tonic-gate NULL, /* bus_fm_fini */ 2247c478bd9Sstevel@tonic-gate NULL, /* bus_fm_access_enter */ 2257c478bd9Sstevel@tonic-gate NULL, /* bus_fm_access_exit */ 2267c478bd9Sstevel@tonic-gate NULL, /* bus_powr */ 2277c478bd9Sstevel@tonic-gate rootnex_intr_ops /* bus_intr_op */ 2287c478bd9Sstevel@tonic-gate }; 2297c478bd9Sstevel@tonic-gate 23012f080e7Smrj static int rootnex_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 23112f080e7Smrj static int rootnex_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 2327c478bd9Sstevel@tonic-gate 2337c478bd9Sstevel@tonic-gate static struct dev_ops rootnex_ops = { 2347c478bd9Sstevel@tonic-gate DEVO_REV, 23512f080e7Smrj 0, 23612f080e7Smrj ddi_no_info, 2377c478bd9Sstevel@tonic-gate nulldev, 23812f080e7Smrj nulldev, 2397c478bd9Sstevel@tonic-gate rootnex_attach, 24012f080e7Smrj rootnex_detach, 24112f080e7Smrj nulldev, 24212f080e7Smrj &rootnex_cb_ops, 2437c478bd9Sstevel@tonic-gate &rootnex_bus_ops 2447c478bd9Sstevel@tonic-gate }; 2457c478bd9Sstevel@tonic-gate 24612f080e7Smrj static struct modldrv rootnex_modldrv = { 24712f080e7Smrj &mod_driverops, 2487c478bd9Sstevel@tonic-gate "i86pc root nexus %I%", 24912f080e7Smrj &rootnex_ops 2507c478bd9Sstevel@tonic-gate }; 2517c478bd9Sstevel@tonic-gate 25212f080e7Smrj static struct modlinkage rootnex_modlinkage = { 25312f080e7Smrj MODREV_1, 25412f080e7Smrj (void *)&rootnex_modldrv, 25512f080e7Smrj NULL 2567c478bd9Sstevel@tonic-gate }; 2577c478bd9Sstevel@tonic-gate 2587c478bd9Sstevel@tonic-gate 25912f080e7Smrj /* 26012f080e7Smrj * extern hacks 26112f080e7Smrj */ 26212f080e7Smrj extern struct seg_ops segdev_ops; 26312f080e7Smrj extern int ignore_hardware_nodes; /* force flag from ddi_impl.c */ 26412f080e7Smrj #ifdef DDI_MAP_DEBUG 26512f080e7Smrj extern int ddi_map_debug_flag; 26612f080e7Smrj #define ddi_map_debug if (ddi_map_debug_flag) prom_printf 26712f080e7Smrj #endif 26812f080e7Smrj #define ptob64(x) (((uint64_t)(x)) << MMU_PAGESHIFT) 26912f080e7Smrj extern void i86_pp_map(page_t *pp, caddr_t kaddr); 27012f080e7Smrj extern void i86_va_map(caddr_t vaddr, struct as *asp, caddr_t kaddr); 27112f080e7Smrj extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, 27212f080e7Smrj psm_intr_op_t, int *); 27312f080e7Smrj extern int impl_ddi_sunbus_initchild(dev_info_t *dip); 27412f080e7Smrj extern void impl_ddi_sunbus_removechild(dev_info_t *dip); 27512f080e7Smrj /* 27612f080e7Smrj * Use device arena to use for device control register mappings. 27712f080e7Smrj * Various kernel memory walkers (debugger, dtrace) need to know 27812f080e7Smrj * to avoid this address range to prevent undesired device activity. 27912f080e7Smrj */ 28012f080e7Smrj extern void *device_arena_alloc(size_t size, int vm_flag); 28112f080e7Smrj extern void device_arena_free(void * vaddr, size_t size); 28212f080e7Smrj 28312f080e7Smrj 28412f080e7Smrj /* 28512f080e7Smrj * Internal functions 28612f080e7Smrj */ 28712f080e7Smrj static int rootnex_dma_init(); 28812f080e7Smrj static void rootnex_add_props(dev_info_t *); 28912f080e7Smrj static int rootnex_ctl_reportdev(dev_info_t *dip); 29012f080e7Smrj static struct intrspec *rootnex_get_ispec(dev_info_t *rdip, int inum); 29112f080e7Smrj static int rootnex_ctlops_poke(peekpoke_ctlops_t *in_args); 29212f080e7Smrj static int rootnex_ctlops_peek(peekpoke_ctlops_t *in_args, void *result); 29312f080e7Smrj static int rootnex_map_regspec(ddi_map_req_t *mp, caddr_t *vaddrp); 29412f080e7Smrj static int rootnex_unmap_regspec(ddi_map_req_t *mp, caddr_t *vaddrp); 29512f080e7Smrj static int rootnex_map_handle(ddi_map_req_t *mp); 29612f080e7Smrj static void rootnex_clean_dmahdl(ddi_dma_impl_t *hp); 29712f080e7Smrj static int rootnex_valid_alloc_parms(ddi_dma_attr_t *attr, uint_t maxsegsize); 29812f080e7Smrj static int rootnex_valid_bind_parms(ddi_dma_req_t *dmareq, 29912f080e7Smrj ddi_dma_attr_t *attr); 30012f080e7Smrj static void rootnex_get_sgl(ddi_dma_obj_t *dmar_object, ddi_dma_cookie_t *sgl, 30112f080e7Smrj rootnex_sglinfo_t *sglinfo); 30212f080e7Smrj static int rootnex_bind_slowpath(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq, 30312f080e7Smrj rootnex_dma_t *dma, ddi_dma_attr_t *attr, int kmflag); 30412f080e7Smrj static int rootnex_setup_copybuf(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq, 30512f080e7Smrj rootnex_dma_t *dma, ddi_dma_attr_t *attr); 30612f080e7Smrj static void rootnex_teardown_copybuf(rootnex_dma_t *dma); 30712f080e7Smrj static int rootnex_setup_windows(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 30812f080e7Smrj ddi_dma_attr_t *attr, int kmflag); 30912f080e7Smrj static void rootnex_teardown_windows(rootnex_dma_t *dma); 31012f080e7Smrj static void rootnex_init_win(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 31112f080e7Smrj rootnex_window_t *window, ddi_dma_cookie_t *cookie, off_t cur_offset); 31212f080e7Smrj static void rootnex_setup_cookie(ddi_dma_obj_t *dmar_object, 31312f080e7Smrj rootnex_dma_t *dma, ddi_dma_cookie_t *cookie, off_t cur_offset, 31412f080e7Smrj size_t *copybuf_used, page_t **cur_pp); 31512f080e7Smrj static int rootnex_sgllen_window_boundary(ddi_dma_impl_t *hp, 31612f080e7Smrj rootnex_dma_t *dma, rootnex_window_t **windowp, ddi_dma_cookie_t *cookie, 31712f080e7Smrj ddi_dma_attr_t *attr, off_t cur_offset); 31812f080e7Smrj static int rootnex_copybuf_window_boundary(ddi_dma_impl_t *hp, 31912f080e7Smrj rootnex_dma_t *dma, rootnex_window_t **windowp, 32012f080e7Smrj ddi_dma_cookie_t *cookie, off_t cur_offset, size_t *copybuf_used); 32112f080e7Smrj static int rootnex_maxxfer_window_boundary(ddi_dma_impl_t *hp, 32212f080e7Smrj rootnex_dma_t *dma, rootnex_window_t **windowp, ddi_dma_cookie_t *cookie); 32312f080e7Smrj static int rootnex_valid_sync_parms(ddi_dma_impl_t *hp, rootnex_window_t *win, 32412f080e7Smrj off_t offset, size_t size, uint_t cache_flags); 32512f080e7Smrj static int rootnex_verify_buffer(rootnex_dma_t *dma); 326*7aec1d6eScindi static int rootnex_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, 327*7aec1d6eScindi const void *no_used); 32812f080e7Smrj 32912f080e7Smrj 33012f080e7Smrj /* 33112f080e7Smrj * _init() 33212f080e7Smrj * 33312f080e7Smrj */ 3347c478bd9Sstevel@tonic-gate int 3357c478bd9Sstevel@tonic-gate _init(void) 3367c478bd9Sstevel@tonic-gate { 33712f080e7Smrj 33812f080e7Smrj rootnex_state = NULL; 33912f080e7Smrj return (mod_install(&rootnex_modlinkage)); 3407c478bd9Sstevel@tonic-gate } 3417c478bd9Sstevel@tonic-gate 34212f080e7Smrj 34312f080e7Smrj /* 34412f080e7Smrj * _info() 34512f080e7Smrj * 34612f080e7Smrj */ 34712f080e7Smrj int 34812f080e7Smrj _info(struct modinfo *modinfop) 34912f080e7Smrj { 35012f080e7Smrj return (mod_info(&rootnex_modlinkage, modinfop)); 35112f080e7Smrj } 35212f080e7Smrj 35312f080e7Smrj 35412f080e7Smrj /* 35512f080e7Smrj * _fini() 35612f080e7Smrj * 35712f080e7Smrj */ 3587c478bd9Sstevel@tonic-gate int 3597c478bd9Sstevel@tonic-gate _fini(void) 3607c478bd9Sstevel@tonic-gate { 3617c478bd9Sstevel@tonic-gate return (EBUSY); 3627c478bd9Sstevel@tonic-gate } 3637c478bd9Sstevel@tonic-gate 36412f080e7Smrj 36512f080e7Smrj /* 36612f080e7Smrj * rootnex_attach() 36712f080e7Smrj * 36812f080e7Smrj */ 36912f080e7Smrj static int 37012f080e7Smrj rootnex_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 3717c478bd9Sstevel@tonic-gate { 372*7aec1d6eScindi int fmcap; 37312f080e7Smrj int e; 37412f080e7Smrj 37512f080e7Smrj 37612f080e7Smrj switch (cmd) { 37712f080e7Smrj case DDI_ATTACH: 37812f080e7Smrj break; 37912f080e7Smrj case DDI_RESUME: 38012f080e7Smrj return (DDI_SUCCESS); 38112f080e7Smrj default: 38212f080e7Smrj return (DDI_FAILURE); 3837c478bd9Sstevel@tonic-gate } 3847c478bd9Sstevel@tonic-gate 3857c478bd9Sstevel@tonic-gate /* 38612f080e7Smrj * We should only have one instance of rootnex. Save it away since we 38712f080e7Smrj * don't have an easy way to get it back later. 3887c478bd9Sstevel@tonic-gate */ 38912f080e7Smrj ASSERT(rootnex_state == NULL); 39012f080e7Smrj rootnex_state = kmem_zalloc(sizeof (rootnex_state_t), KM_SLEEP); 3917c478bd9Sstevel@tonic-gate 39212f080e7Smrj rootnex_state->r_dip = dip; 393*7aec1d6eScindi rootnex_state->r_err_ibc = (ddi_iblock_cookie_t)ipltospl(15); 39412f080e7Smrj rootnex_state->r_reserved_msg_printed = B_FALSE; 39512f080e7Smrj rootnex_cnt = &rootnex_state->r_counters[0]; 3967c478bd9Sstevel@tonic-gate 39712f080e7Smrj mutex_init(&rootnex_state->r_peekpoke_mutex, NULL, MUTEX_SPIN, 39812f080e7Smrj (void *)ipltospl(15)); 39912f080e7Smrj 400*7aec1d6eScindi /* 401*7aec1d6eScindi * Set minimum fm capability level for i86pc platforms and then 402*7aec1d6eScindi * initialize error handling. Since we're the rootnex, we don't 403*7aec1d6eScindi * care what's returned in the fmcap field. 404*7aec1d6eScindi */ 405*7aec1d6eScindi ddi_system_fmcap = DDI_FM_ERRCB_CAPABLE; 406*7aec1d6eScindi fmcap = ddi_system_fmcap; 407*7aec1d6eScindi ddi_fm_init(dip, &fmcap, &rootnex_state->r_err_ibc); 408*7aec1d6eScindi if (fmcap & DDI_FM_ERRCB_CAPABLE) 409*7aec1d6eScindi ddi_fm_handler_register(dip, rootnex_fm_callback, NULL); 410*7aec1d6eScindi 41112f080e7Smrj /* initialize DMA related state */ 41212f080e7Smrj e = rootnex_dma_init(); 41312f080e7Smrj if (e != DDI_SUCCESS) { 41412f080e7Smrj mutex_destroy(&rootnex_state->r_peekpoke_mutex); 41512f080e7Smrj kmem_free(rootnex_state, sizeof (rootnex_state_t)); 41612f080e7Smrj return (DDI_FAILURE); 41712f080e7Smrj } 41812f080e7Smrj 41912f080e7Smrj /* Add static root node properties */ 42012f080e7Smrj rootnex_add_props(dip); 42112f080e7Smrj 42212f080e7Smrj /* since we can't call ddi_report_dev() */ 42312f080e7Smrj cmn_err(CE_CONT, "?root nexus = %s\n", ddi_get_name(dip)); 42412f080e7Smrj 42512f080e7Smrj /* Initialize rootnex event handle */ 42612f080e7Smrj i_ddi_rootnex_init_events(dip); 42712f080e7Smrj 42812f080e7Smrj return (DDI_SUCCESS); 42912f080e7Smrj } 43012f080e7Smrj 43112f080e7Smrj 43212f080e7Smrj /* 43312f080e7Smrj * rootnex_detach() 43412f080e7Smrj * 43512f080e7Smrj */ 4367c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 4377c478bd9Sstevel@tonic-gate static int 43812f080e7Smrj rootnex_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 4397c478bd9Sstevel@tonic-gate { 44012f080e7Smrj switch (cmd) { 44112f080e7Smrj case DDI_SUSPEND: 44212f080e7Smrj break; 44312f080e7Smrj default: 44412f080e7Smrj return (DDI_FAILURE); 44512f080e7Smrj } 4467c478bd9Sstevel@tonic-gate 44712f080e7Smrj return (DDI_SUCCESS); 44812f080e7Smrj } 4497c478bd9Sstevel@tonic-gate 4507c478bd9Sstevel@tonic-gate 45112f080e7Smrj /* 45212f080e7Smrj * rootnex_dma_init() 45312f080e7Smrj * 45412f080e7Smrj */ 45512f080e7Smrj /*ARGSUSED*/ 45612f080e7Smrj static int 45712f080e7Smrj rootnex_dma_init() 45812f080e7Smrj { 45912f080e7Smrj size_t bufsize; 46012f080e7Smrj 46112f080e7Smrj 46212f080e7Smrj /* 46312f080e7Smrj * size of our cookie/window/copybuf state needed in dma bind that we 46412f080e7Smrj * pre-alloc in dma_alloc_handle 46512f080e7Smrj */ 46612f080e7Smrj rootnex_state->r_prealloc_cookies = rootnex_prealloc_cookies; 46712f080e7Smrj rootnex_state->r_prealloc_size = 46812f080e7Smrj (rootnex_state->r_prealloc_cookies * sizeof (ddi_dma_cookie_t)) + 46912f080e7Smrj (rootnex_prealloc_windows * sizeof (rootnex_window_t)) + 47012f080e7Smrj (rootnex_prealloc_copybuf * sizeof (rootnex_pgmap_t)); 47112f080e7Smrj 47212f080e7Smrj /* 47312f080e7Smrj * setup DDI DMA handle kmem cache, align each handle on 64 bytes, 47412f080e7Smrj * allocate 16 extra bytes for struct pointer alignment 47512f080e7Smrj * (p->dmai_private & dma->dp_prealloc_buffer) 47612f080e7Smrj */ 47712f080e7Smrj bufsize = sizeof (ddi_dma_impl_t) + sizeof (rootnex_dma_t) + 47812f080e7Smrj rootnex_state->r_prealloc_size + 0x10; 47912f080e7Smrj rootnex_state->r_dmahdl_cache = kmem_cache_create("rootnex_dmahdl", 48012f080e7Smrj bufsize, 64, NULL, NULL, NULL, NULL, NULL, 0); 48112f080e7Smrj if (rootnex_state->r_dmahdl_cache == NULL) { 48212f080e7Smrj return (DDI_FAILURE); 48312f080e7Smrj } 4847c478bd9Sstevel@tonic-gate 4857c478bd9Sstevel@tonic-gate /* 4867c478bd9Sstevel@tonic-gate * allocate array to track which major numbers we have printed warnings 4877c478bd9Sstevel@tonic-gate * for. 4887c478bd9Sstevel@tonic-gate */ 4897c478bd9Sstevel@tonic-gate rootnex_warn_list = kmem_zalloc(devcnt * sizeof (*rootnex_warn_list), 4907c478bd9Sstevel@tonic-gate KM_SLEEP); 4917c478bd9Sstevel@tonic-gate 4927c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 4937c478bd9Sstevel@tonic-gate } 4947c478bd9Sstevel@tonic-gate 4957c478bd9Sstevel@tonic-gate 4967c478bd9Sstevel@tonic-gate /* 49712f080e7Smrj * rootnex_add_props() 49812f080e7Smrj * 4997c478bd9Sstevel@tonic-gate */ 5007c478bd9Sstevel@tonic-gate static void 50112f080e7Smrj rootnex_add_props(dev_info_t *dip) 5027c478bd9Sstevel@tonic-gate { 50312f080e7Smrj rootnex_intprop_t *rpp; 5047c478bd9Sstevel@tonic-gate int i; 5057c478bd9Sstevel@tonic-gate 50612f080e7Smrj /* Add static integer/boolean properties to the root node */ 50712f080e7Smrj rpp = rootnex_intprp; 50812f080e7Smrj for (i = 0; i < NROOT_INTPROPS; i++) { 50912f080e7Smrj (void) e_ddi_prop_update_int(DDI_DEV_T_NONE, dip, 51012f080e7Smrj rpp[i].prop_name, rpp[i].prop_value); 51112f080e7Smrj } 5127c478bd9Sstevel@tonic-gate } 5137c478bd9Sstevel@tonic-gate 51412f080e7Smrj 51512f080e7Smrj 5167c478bd9Sstevel@tonic-gate /* 51712f080e7Smrj * ************************* 51812f080e7Smrj * ctlops related routines 51912f080e7Smrj * ************************* 52012f080e7Smrj */ 52112f080e7Smrj 52212f080e7Smrj /* 52312f080e7Smrj * rootnex_ctlops() 5247c478bd9Sstevel@tonic-gate * 5257c478bd9Sstevel@tonic-gate */ 526a195726fSgovinda /*ARGSUSED*/ 5277c478bd9Sstevel@tonic-gate static int 52812f080e7Smrj rootnex_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop, 52912f080e7Smrj void *arg, void *result) 5307c478bd9Sstevel@tonic-gate { 53112f080e7Smrj int n, *ptr; 53212f080e7Smrj struct ddi_parent_private_data *pdp; 5337c478bd9Sstevel@tonic-gate 53412f080e7Smrj switch (ctlop) { 53512f080e7Smrj case DDI_CTLOPS_DMAPMAPC: 5367c478bd9Sstevel@tonic-gate /* 53712f080e7Smrj * Return 'partial' to indicate that dma mapping 53812f080e7Smrj * has to be done in the main MMU. 5397c478bd9Sstevel@tonic-gate */ 54012f080e7Smrj return (DDI_DMA_PARTIAL); 5417c478bd9Sstevel@tonic-gate 54212f080e7Smrj case DDI_CTLOPS_BTOP: 5437c478bd9Sstevel@tonic-gate /* 54412f080e7Smrj * Convert byte count input to physical page units. 54512f080e7Smrj * (byte counts that are not a page-size multiple 54612f080e7Smrj * are rounded down) 5477c478bd9Sstevel@tonic-gate */ 54812f080e7Smrj *(ulong_t *)result = btop(*(ulong_t *)arg); 5497c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5507c478bd9Sstevel@tonic-gate 55112f080e7Smrj case DDI_CTLOPS_PTOB: 5527c478bd9Sstevel@tonic-gate /* 55312f080e7Smrj * Convert size in physical pages to bytes 5547c478bd9Sstevel@tonic-gate */ 55512f080e7Smrj *(ulong_t *)result = ptob(*(ulong_t *)arg); 5567c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5577c478bd9Sstevel@tonic-gate 55812f080e7Smrj case DDI_CTLOPS_BTOPR: 5597c478bd9Sstevel@tonic-gate /* 56012f080e7Smrj * Convert byte count input to physical page units 56112f080e7Smrj * (byte counts that are not a page-size multiple 56212f080e7Smrj * are rounded up) 5637c478bd9Sstevel@tonic-gate */ 56412f080e7Smrj *(ulong_t *)result = btopr(*(ulong_t *)arg); 56512f080e7Smrj return (DDI_SUCCESS); 56612f080e7Smrj 56712f080e7Smrj case DDI_CTLOPS_POKE: 56812f080e7Smrj return (rootnex_ctlops_poke((peekpoke_ctlops_t *)arg)); 56912f080e7Smrj 57012f080e7Smrj case DDI_CTLOPS_PEEK: 57112f080e7Smrj return (rootnex_ctlops_peek((peekpoke_ctlops_t *)arg, result)); 57212f080e7Smrj 57312f080e7Smrj case DDI_CTLOPS_INITCHILD: 57412f080e7Smrj return (impl_ddi_sunbus_initchild(arg)); 57512f080e7Smrj 57612f080e7Smrj case DDI_CTLOPS_UNINITCHILD: 57712f080e7Smrj impl_ddi_sunbus_removechild(arg); 57812f080e7Smrj return (DDI_SUCCESS); 57912f080e7Smrj 58012f080e7Smrj case DDI_CTLOPS_REPORTDEV: 58112f080e7Smrj return (rootnex_ctl_reportdev(rdip)); 58212f080e7Smrj 58312f080e7Smrj case DDI_CTLOPS_IOMIN: 5847c478bd9Sstevel@tonic-gate /* 58512f080e7Smrj * Nothing to do here but reflect back.. 5867c478bd9Sstevel@tonic-gate */ 5877c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5887c478bd9Sstevel@tonic-gate 58912f080e7Smrj case DDI_CTLOPS_REGSIZE: 59012f080e7Smrj case DDI_CTLOPS_NREGS: 59112f080e7Smrj break; 5927c478bd9Sstevel@tonic-gate 59312f080e7Smrj case DDI_CTLOPS_SIDDEV: 59412f080e7Smrj if (ndi_dev_is_prom_node(rdip)) 5957c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 59612f080e7Smrj if (ndi_dev_is_persistent_node(rdip)) 59712f080e7Smrj return (DDI_SUCCESS); 5987c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 5997c478bd9Sstevel@tonic-gate 60012f080e7Smrj case DDI_CTLOPS_POWER: 60112f080e7Smrj return ((*pm_platform_power)((power_req_t *)arg)); 60212f080e7Smrj 603a195726fSgovinda case DDI_CTLOPS_RESERVED0: /* Was DDI_CTLOPS_NINTRS, obsolete */ 60412f080e7Smrj case DDI_CTLOPS_RESERVED1: /* Was DDI_CTLOPS_POKE_INIT, obsolete */ 60512f080e7Smrj case DDI_CTLOPS_RESERVED2: /* Was DDI_CTLOPS_POKE_FLUSH, obsolete */ 60612f080e7Smrj case DDI_CTLOPS_RESERVED3: /* Was DDI_CTLOPS_POKE_FINI, obsolete */ 607a195726fSgovinda case DDI_CTLOPS_RESERVED4: /* Was DDI_CTLOPS_INTR_HILEVEL, obsolete */ 608a195726fSgovinda case DDI_CTLOPS_RESERVED5: /* Was DDI_CTLOPS_XLATE_INTRS, obsolete */ 60912f080e7Smrj if (!rootnex_state->r_reserved_msg_printed) { 61012f080e7Smrj rootnex_state->r_reserved_msg_printed = B_TRUE; 61112f080e7Smrj cmn_err(CE_WARN, "Failing ddi_ctlops call(s) for " 61212f080e7Smrj "1 or more reserved/obsolete operations."); 6137c478bd9Sstevel@tonic-gate } 61412f080e7Smrj return (DDI_FAILURE); 6157c478bd9Sstevel@tonic-gate 6167c478bd9Sstevel@tonic-gate default: 6177c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 6187c478bd9Sstevel@tonic-gate } 61912f080e7Smrj /* 62012f080e7Smrj * The rest are for "hardware" properties 62112f080e7Smrj */ 62212f080e7Smrj if ((pdp = ddi_get_parent_data(rdip)) == NULL) 62312f080e7Smrj return (DDI_FAILURE); 6247c478bd9Sstevel@tonic-gate 62512f080e7Smrj if (ctlop == DDI_CTLOPS_NREGS) { 62612f080e7Smrj ptr = (int *)result; 62712f080e7Smrj *ptr = pdp->par_nreg; 62812f080e7Smrj } else { 62912f080e7Smrj off_t *size = (off_t *)result; 6307c478bd9Sstevel@tonic-gate 63112f080e7Smrj ptr = (int *)arg; 63212f080e7Smrj n = *ptr; 63312f080e7Smrj if (n >= pdp->par_nreg) { 63412f080e7Smrj return (DDI_FAILURE); 63512f080e7Smrj } 63612f080e7Smrj *size = (off_t)pdp->par_reg[n].regspec_size; 63712f080e7Smrj } 6387c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 6397c478bd9Sstevel@tonic-gate } 6407c478bd9Sstevel@tonic-gate 64112f080e7Smrj 64212f080e7Smrj /* 64312f080e7Smrj * rootnex_ctl_reportdev() 64412f080e7Smrj * 64512f080e7Smrj */ 6467c478bd9Sstevel@tonic-gate static int 64712f080e7Smrj rootnex_ctl_reportdev(dev_info_t *dev) 64812f080e7Smrj { 64912f080e7Smrj int i, n, len, f_len = 0; 65012f080e7Smrj char *buf; 65112f080e7Smrj 65212f080e7Smrj buf = kmem_alloc(REPORTDEV_BUFSIZE, KM_SLEEP); 65312f080e7Smrj f_len += snprintf(buf, REPORTDEV_BUFSIZE, 65412f080e7Smrj "%s%d at root", ddi_driver_name(dev), ddi_get_instance(dev)); 65512f080e7Smrj len = strlen(buf); 65612f080e7Smrj 65712f080e7Smrj for (i = 0; i < sparc_pd_getnreg(dev); i++) { 65812f080e7Smrj 65912f080e7Smrj struct regspec *rp = sparc_pd_getreg(dev, i); 66012f080e7Smrj 66112f080e7Smrj if (i == 0) 66212f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 66312f080e7Smrj ": "); 66412f080e7Smrj else 66512f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 66612f080e7Smrj " and "); 66712f080e7Smrj len = strlen(buf); 66812f080e7Smrj 66912f080e7Smrj switch (rp->regspec_bustype) { 67012f080e7Smrj 67112f080e7Smrj case BTEISA: 67212f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 67312f080e7Smrj "%s 0x%x", DEVI_EISA_NEXNAME, rp->regspec_addr); 67412f080e7Smrj break; 67512f080e7Smrj 67612f080e7Smrj case BTISA: 67712f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 67812f080e7Smrj "%s 0x%x", DEVI_ISA_NEXNAME, rp->regspec_addr); 67912f080e7Smrj break; 68012f080e7Smrj 68112f080e7Smrj default: 68212f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 68312f080e7Smrj "space %x offset %x", 68412f080e7Smrj rp->regspec_bustype, rp->regspec_addr); 68512f080e7Smrj break; 68612f080e7Smrj } 68712f080e7Smrj len = strlen(buf); 68812f080e7Smrj } 68912f080e7Smrj for (i = 0, n = sparc_pd_getnintr(dev); i < n; i++) { 69012f080e7Smrj int pri; 69112f080e7Smrj 69212f080e7Smrj if (i != 0) { 69312f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 69412f080e7Smrj ","); 69512f080e7Smrj len = strlen(buf); 69612f080e7Smrj } 69712f080e7Smrj pri = INT_IPL(sparc_pd_getintr(dev, i)->intrspec_pri); 69812f080e7Smrj f_len += snprintf(buf + len, REPORTDEV_BUFSIZE - len, 69912f080e7Smrj " sparc ipl %d", pri); 70012f080e7Smrj len = strlen(buf); 70112f080e7Smrj } 70212f080e7Smrj #ifdef DEBUG 70312f080e7Smrj if (f_len + 1 >= REPORTDEV_BUFSIZE) { 70412f080e7Smrj cmn_err(CE_NOTE, "next message is truncated: " 70512f080e7Smrj "printed length 1024, real length %d", f_len); 70612f080e7Smrj } 70712f080e7Smrj #endif /* DEBUG */ 70812f080e7Smrj cmn_err(CE_CONT, "?%s\n", buf); 70912f080e7Smrj kmem_free(buf, REPORTDEV_BUFSIZE); 71012f080e7Smrj return (DDI_SUCCESS); 71112f080e7Smrj } 71212f080e7Smrj 71312f080e7Smrj 71412f080e7Smrj /* 71512f080e7Smrj * rootnex_ctlops_poke() 71612f080e7Smrj * 71712f080e7Smrj */ 71812f080e7Smrj static int 71912f080e7Smrj rootnex_ctlops_poke(peekpoke_ctlops_t *in_args) 72012f080e7Smrj { 72112f080e7Smrj int err = DDI_SUCCESS; 72212f080e7Smrj on_trap_data_t otd; 72312f080e7Smrj 72412f080e7Smrj /* Cautious access not supported. */ 72512f080e7Smrj if (in_args->handle != NULL) 72612f080e7Smrj return (DDI_FAILURE); 72712f080e7Smrj 72812f080e7Smrj mutex_enter(&rootnex_state->r_peekpoke_mutex); 72912f080e7Smrj 73012f080e7Smrj /* Set up protected environment. */ 73112f080e7Smrj if (!on_trap(&otd, OT_DATA_ACCESS)) { 73212f080e7Smrj switch (in_args->size) { 73312f080e7Smrj case sizeof (uint8_t): 73412f080e7Smrj *(uint8_t *)in_args->dev_addr = *(uint8_t *) 73512f080e7Smrj in_args->host_addr; 73612f080e7Smrj break; 73712f080e7Smrj 73812f080e7Smrj case sizeof (uint16_t): 73912f080e7Smrj *(uint16_t *)in_args->dev_addr = 74012f080e7Smrj *(uint16_t *)in_args->host_addr; 74112f080e7Smrj break; 74212f080e7Smrj 74312f080e7Smrj case sizeof (uint32_t): 74412f080e7Smrj *(uint32_t *)in_args->dev_addr = 74512f080e7Smrj *(uint32_t *)in_args->host_addr; 74612f080e7Smrj break; 74712f080e7Smrj 74812f080e7Smrj case sizeof (uint64_t): 74912f080e7Smrj *(uint64_t *)in_args->dev_addr = 75012f080e7Smrj *(uint64_t *)in_args->host_addr; 75112f080e7Smrj break; 75212f080e7Smrj 75312f080e7Smrj default: 75412f080e7Smrj err = DDI_FAILURE; 75512f080e7Smrj break; 75612f080e7Smrj } 75712f080e7Smrj } else 75812f080e7Smrj err = DDI_FAILURE; 75912f080e7Smrj 76012f080e7Smrj /* Take down protected environment. */ 76112f080e7Smrj no_trap(); 76212f080e7Smrj mutex_exit(&rootnex_state->r_peekpoke_mutex); 76312f080e7Smrj 76412f080e7Smrj return (err); 76512f080e7Smrj } 76612f080e7Smrj 76712f080e7Smrj 76812f080e7Smrj /* 76912f080e7Smrj * rootnex_ctlops_peek() 77012f080e7Smrj * 77112f080e7Smrj */ 77212f080e7Smrj static int 77312f080e7Smrj rootnex_ctlops_peek(peekpoke_ctlops_t *in_args, void *result) 77412f080e7Smrj { 77512f080e7Smrj int err = DDI_SUCCESS; 77612f080e7Smrj on_trap_data_t otd; 77712f080e7Smrj 77812f080e7Smrj /* Cautious access not supported. */ 77912f080e7Smrj if (in_args->handle != NULL) 78012f080e7Smrj return (DDI_FAILURE); 78112f080e7Smrj 78212f080e7Smrj mutex_enter(&rootnex_state->r_peekpoke_mutex); 78312f080e7Smrj 78412f080e7Smrj if (!on_trap(&otd, OT_DATA_ACCESS)) { 78512f080e7Smrj switch (in_args->size) { 78612f080e7Smrj case sizeof (uint8_t): 78712f080e7Smrj *(uint8_t *)in_args->host_addr = 78812f080e7Smrj *(uint8_t *)in_args->dev_addr; 78912f080e7Smrj break; 79012f080e7Smrj 79112f080e7Smrj case sizeof (uint16_t): 79212f080e7Smrj *(uint16_t *)in_args->host_addr = 79312f080e7Smrj *(uint16_t *)in_args->dev_addr; 79412f080e7Smrj break; 79512f080e7Smrj 79612f080e7Smrj case sizeof (uint32_t): 79712f080e7Smrj *(uint32_t *)in_args->host_addr = 79812f080e7Smrj *(uint32_t *)in_args->dev_addr; 79912f080e7Smrj break; 80012f080e7Smrj 80112f080e7Smrj case sizeof (uint64_t): 80212f080e7Smrj *(uint64_t *)in_args->host_addr = 80312f080e7Smrj *(uint64_t *)in_args->dev_addr; 80412f080e7Smrj break; 80512f080e7Smrj 80612f080e7Smrj default: 80712f080e7Smrj err = DDI_FAILURE; 80812f080e7Smrj break; 80912f080e7Smrj } 81012f080e7Smrj result = (void *)in_args->host_addr; 81112f080e7Smrj } else 81212f080e7Smrj err = DDI_FAILURE; 81312f080e7Smrj 81412f080e7Smrj no_trap(); 81512f080e7Smrj mutex_exit(&rootnex_state->r_peekpoke_mutex); 81612f080e7Smrj 81712f080e7Smrj return (err); 81812f080e7Smrj } 81912f080e7Smrj 82012f080e7Smrj 82112f080e7Smrj 82212f080e7Smrj /* 82312f080e7Smrj * ****************** 82412f080e7Smrj * map related code 82512f080e7Smrj * ****************** 82612f080e7Smrj */ 82712f080e7Smrj 82812f080e7Smrj /* 82912f080e7Smrj * rootnex_map() 83012f080e7Smrj * 83112f080e7Smrj */ 83212f080e7Smrj static int 83312f080e7Smrj rootnex_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, off_t offset, 83412f080e7Smrj off_t len, caddr_t *vaddrp) 8357c478bd9Sstevel@tonic-gate { 8367c478bd9Sstevel@tonic-gate struct regspec *rp, tmp_reg; 8377c478bd9Sstevel@tonic-gate ddi_map_req_t mr = *mp; /* Get private copy of request */ 8387c478bd9Sstevel@tonic-gate int error; 8397c478bd9Sstevel@tonic-gate 8407c478bd9Sstevel@tonic-gate mp = &mr; 8417c478bd9Sstevel@tonic-gate 8427c478bd9Sstevel@tonic-gate switch (mp->map_op) { 8437c478bd9Sstevel@tonic-gate case DDI_MO_MAP_LOCKED: 8447c478bd9Sstevel@tonic-gate case DDI_MO_UNMAP: 8457c478bd9Sstevel@tonic-gate case DDI_MO_MAP_HANDLE: 8467c478bd9Sstevel@tonic-gate break; 8477c478bd9Sstevel@tonic-gate default: 8487c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 8497c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "rootnex_map: unimplemented map op %d.", 8507c478bd9Sstevel@tonic-gate mp->map_op); 8517c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 8527c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED); 8537c478bd9Sstevel@tonic-gate } 8547c478bd9Sstevel@tonic-gate 8557c478bd9Sstevel@tonic-gate if (mp->map_flags & DDI_MF_USER_MAPPING) { 8567c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 8577c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "rootnex_map: unimplemented map type: user."); 8587c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 8597c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED); 8607c478bd9Sstevel@tonic-gate } 8617c478bd9Sstevel@tonic-gate 8627c478bd9Sstevel@tonic-gate /* 8637c478bd9Sstevel@tonic-gate * First, if given an rnumber, convert it to a regspec... 8647c478bd9Sstevel@tonic-gate * (Presumably, this is on behalf of a child of the root node?) 8657c478bd9Sstevel@tonic-gate */ 8667c478bd9Sstevel@tonic-gate 8677c478bd9Sstevel@tonic-gate if (mp->map_type == DDI_MT_RNUMBER) { 8687c478bd9Sstevel@tonic-gate 8697c478bd9Sstevel@tonic-gate int rnumber = mp->map_obj.rnumber; 8707c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 8717c478bd9Sstevel@tonic-gate static char *out_of_range = 8727c478bd9Sstevel@tonic-gate "rootnex_map: Out of range rnumber <%d>, device <%s>"; 8737c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 8747c478bd9Sstevel@tonic-gate 8757c478bd9Sstevel@tonic-gate rp = i_ddi_rnumber_to_regspec(rdip, rnumber); 8767c478bd9Sstevel@tonic-gate if (rp == NULL) { 8777c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 8787c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, out_of_range, rnumber, 8797c478bd9Sstevel@tonic-gate ddi_get_name(rdip)); 8807c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 8817c478bd9Sstevel@tonic-gate return (DDI_ME_RNUMBER_RANGE); 8827c478bd9Sstevel@tonic-gate } 8837c478bd9Sstevel@tonic-gate 8847c478bd9Sstevel@tonic-gate /* 8857c478bd9Sstevel@tonic-gate * Convert the given ddi_map_req_t from rnumber to regspec... 8867c478bd9Sstevel@tonic-gate */ 8877c478bd9Sstevel@tonic-gate 8887c478bd9Sstevel@tonic-gate mp->map_type = DDI_MT_REGSPEC; 8897c478bd9Sstevel@tonic-gate mp->map_obj.rp = rp; 8907c478bd9Sstevel@tonic-gate } 8917c478bd9Sstevel@tonic-gate 8927c478bd9Sstevel@tonic-gate /* 8937c478bd9Sstevel@tonic-gate * Adjust offset and length correspnding to called values... 8947c478bd9Sstevel@tonic-gate * XXX: A non-zero length means override the one in the regspec 8957c478bd9Sstevel@tonic-gate * XXX: (regardless of what's in the parent's range?) 8967c478bd9Sstevel@tonic-gate */ 8977c478bd9Sstevel@tonic-gate 8987c478bd9Sstevel@tonic-gate tmp_reg = *(mp->map_obj.rp); /* Preserve underlying data */ 8997c478bd9Sstevel@tonic-gate rp = mp->map_obj.rp = &tmp_reg; /* Use tmp_reg in request */ 9007c478bd9Sstevel@tonic-gate 9017c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 9027c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, 9037c478bd9Sstevel@tonic-gate "rootnex: <%s,%s> <0x%x, 0x%x, 0x%d>" 9047c478bd9Sstevel@tonic-gate " offset %d len %d handle 0x%x\n", 9057c478bd9Sstevel@tonic-gate ddi_get_name(dip), ddi_get_name(rdip), 9067c478bd9Sstevel@tonic-gate rp->regspec_bustype, rp->regspec_addr, rp->regspec_size, 9077c478bd9Sstevel@tonic-gate offset, len, mp->map_handlep); 9087c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 9097c478bd9Sstevel@tonic-gate 9107c478bd9Sstevel@tonic-gate /* 9117c478bd9Sstevel@tonic-gate * I/O or memory mapping: 9127c478bd9Sstevel@tonic-gate * 9137c478bd9Sstevel@tonic-gate * <bustype=0, addr=x, len=x>: memory 9147c478bd9Sstevel@tonic-gate * <bustype=1, addr=x, len=x>: i/o 9157c478bd9Sstevel@tonic-gate * <bustype>1, addr=0, len=x>: x86-compatibility i/o 9167c478bd9Sstevel@tonic-gate */ 9177c478bd9Sstevel@tonic-gate 9187c478bd9Sstevel@tonic-gate if (rp->regspec_bustype > 1 && rp->regspec_addr != 0) { 9197c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "<%s,%s> invalid register spec" 9207c478bd9Sstevel@tonic-gate " <0x%x, 0x%x, 0x%x>", ddi_get_name(dip), 9217c478bd9Sstevel@tonic-gate ddi_get_name(rdip), rp->regspec_bustype, 9227c478bd9Sstevel@tonic-gate rp->regspec_addr, rp->regspec_size); 9237c478bd9Sstevel@tonic-gate return (DDI_ME_INVAL); 9247c478bd9Sstevel@tonic-gate } 9257c478bd9Sstevel@tonic-gate 9267c478bd9Sstevel@tonic-gate if (rp->regspec_bustype > 1 && rp->regspec_addr == 0) { 9277c478bd9Sstevel@tonic-gate /* 9287c478bd9Sstevel@tonic-gate * compatibility i/o mapping 9297c478bd9Sstevel@tonic-gate */ 9307c478bd9Sstevel@tonic-gate rp->regspec_bustype += (uint_t)offset; 9317c478bd9Sstevel@tonic-gate } else { 9327c478bd9Sstevel@tonic-gate /* 9337c478bd9Sstevel@tonic-gate * Normal memory or i/o mapping 9347c478bd9Sstevel@tonic-gate */ 9357c478bd9Sstevel@tonic-gate rp->regspec_addr += (uint_t)offset; 9367c478bd9Sstevel@tonic-gate } 9377c478bd9Sstevel@tonic-gate 9387c478bd9Sstevel@tonic-gate if (len != 0) 9397c478bd9Sstevel@tonic-gate rp->regspec_size = (uint_t)len; 9407c478bd9Sstevel@tonic-gate 9417c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 9427c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, 9437c478bd9Sstevel@tonic-gate " <%s,%s> <0x%x, 0x%x, 0x%d>" 9447c478bd9Sstevel@tonic-gate " offset %d len %d handle 0x%x\n", 9457c478bd9Sstevel@tonic-gate ddi_get_name(dip), ddi_get_name(rdip), 9467c478bd9Sstevel@tonic-gate rp->regspec_bustype, rp->regspec_addr, rp->regspec_size, 9477c478bd9Sstevel@tonic-gate offset, len, mp->map_handlep); 9487c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 9497c478bd9Sstevel@tonic-gate 9507c478bd9Sstevel@tonic-gate /* 9517c478bd9Sstevel@tonic-gate * Apply any parent ranges at this level, if applicable. 9527c478bd9Sstevel@tonic-gate * (This is where nexus specific regspec translation takes place. 9537c478bd9Sstevel@tonic-gate * Use of this function is implicit agreement that translation is 9547c478bd9Sstevel@tonic-gate * provided via ddi_apply_range.) 9557c478bd9Sstevel@tonic-gate */ 9567c478bd9Sstevel@tonic-gate 9577c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 9587c478bd9Sstevel@tonic-gate ddi_map_debug("applying range of parent <%s> to child <%s>...\n", 9597c478bd9Sstevel@tonic-gate ddi_get_name(dip), ddi_get_name(rdip)); 9607c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 9617c478bd9Sstevel@tonic-gate 9627c478bd9Sstevel@tonic-gate if ((error = i_ddi_apply_range(dip, rdip, mp->map_obj.rp)) != 0) 9637c478bd9Sstevel@tonic-gate return (error); 9647c478bd9Sstevel@tonic-gate 9657c478bd9Sstevel@tonic-gate switch (mp->map_op) { 9667c478bd9Sstevel@tonic-gate case DDI_MO_MAP_LOCKED: 9677c478bd9Sstevel@tonic-gate 9687c478bd9Sstevel@tonic-gate /* 9697c478bd9Sstevel@tonic-gate * Set up the locked down kernel mapping to the regspec... 9707c478bd9Sstevel@tonic-gate */ 9717c478bd9Sstevel@tonic-gate 9727c478bd9Sstevel@tonic-gate return (rootnex_map_regspec(mp, vaddrp)); 9737c478bd9Sstevel@tonic-gate 9747c478bd9Sstevel@tonic-gate case DDI_MO_UNMAP: 9757c478bd9Sstevel@tonic-gate 9767c478bd9Sstevel@tonic-gate /* 9777c478bd9Sstevel@tonic-gate * Release mapping... 9787c478bd9Sstevel@tonic-gate */ 9797c478bd9Sstevel@tonic-gate 9807c478bd9Sstevel@tonic-gate return (rootnex_unmap_regspec(mp, vaddrp)); 9817c478bd9Sstevel@tonic-gate 9827c478bd9Sstevel@tonic-gate case DDI_MO_MAP_HANDLE: 9837c478bd9Sstevel@tonic-gate 9847c478bd9Sstevel@tonic-gate return (rootnex_map_handle(mp)); 9857c478bd9Sstevel@tonic-gate 9867c478bd9Sstevel@tonic-gate default: 9877c478bd9Sstevel@tonic-gate return (DDI_ME_UNIMPLEMENTED); 9887c478bd9Sstevel@tonic-gate } 9897c478bd9Sstevel@tonic-gate } 9907c478bd9Sstevel@tonic-gate 9917c478bd9Sstevel@tonic-gate 9927c478bd9Sstevel@tonic-gate /* 99312f080e7Smrj * rootnex_map_fault() 9947c478bd9Sstevel@tonic-gate * 9957c478bd9Sstevel@tonic-gate * fault in mappings for requestors 9967c478bd9Sstevel@tonic-gate */ 9977c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 9987c478bd9Sstevel@tonic-gate static int 99912f080e7Smrj rootnex_map_fault(dev_info_t *dip, dev_info_t *rdip, struct hat *hat, 100012f080e7Smrj struct seg *seg, caddr_t addr, struct devpage *dp, pfn_t pfn, uint_t prot, 100112f080e7Smrj uint_t lock) 10027c478bd9Sstevel@tonic-gate { 10037c478bd9Sstevel@tonic-gate 10047c478bd9Sstevel@tonic-gate #ifdef DDI_MAP_DEBUG 10057c478bd9Sstevel@tonic-gate ddi_map_debug("rootnex_map_fault: address <%x> pfn <%x>", addr, pfn); 10067c478bd9Sstevel@tonic-gate ddi_map_debug(" Seg <%s>\n", 10077c478bd9Sstevel@tonic-gate seg->s_ops == &segdev_ops ? "segdev" : 10087c478bd9Sstevel@tonic-gate seg == &kvseg ? "segkmem" : "NONE!"); 10097c478bd9Sstevel@tonic-gate #endif /* DDI_MAP_DEBUG */ 10107c478bd9Sstevel@tonic-gate 10117c478bd9Sstevel@tonic-gate /* 10127c478bd9Sstevel@tonic-gate * This is all terribly broken, but it is a start 10137c478bd9Sstevel@tonic-gate * 10147c478bd9Sstevel@tonic-gate * XXX Note that this test means that segdev_ops 10157c478bd9Sstevel@tonic-gate * must be exported from seg_dev.c. 10167c478bd9Sstevel@tonic-gate * XXX What about devices with their own segment drivers? 10177c478bd9Sstevel@tonic-gate */ 10187c478bd9Sstevel@tonic-gate if (seg->s_ops == &segdev_ops) { 10197c478bd9Sstevel@tonic-gate struct segdev_data *sdp = 10207c478bd9Sstevel@tonic-gate (struct segdev_data *)seg->s_data; 10217c478bd9Sstevel@tonic-gate 10227c478bd9Sstevel@tonic-gate if (hat == NULL) { 10237c478bd9Sstevel@tonic-gate /* 10247c478bd9Sstevel@tonic-gate * This is one plausible interpretation of 10257c478bd9Sstevel@tonic-gate * a null hat i.e. use the first hat on the 10267c478bd9Sstevel@tonic-gate * address space hat list which by convention is 10277c478bd9Sstevel@tonic-gate * the hat of the system MMU. At alternative 10287c478bd9Sstevel@tonic-gate * would be to panic .. this might well be better .. 10297c478bd9Sstevel@tonic-gate */ 10307c478bd9Sstevel@tonic-gate ASSERT(AS_READ_HELD(seg->s_as, &seg->s_as->a_lock)); 10317c478bd9Sstevel@tonic-gate hat = seg->s_as->a_hat; 10327c478bd9Sstevel@tonic-gate cmn_err(CE_NOTE, "rootnex_map_fault: nil hat"); 10337c478bd9Sstevel@tonic-gate } 10347c478bd9Sstevel@tonic-gate hat_devload(hat, addr, MMU_PAGESIZE, pfn, prot | sdp->hat_attr, 10357c478bd9Sstevel@tonic-gate (lock ? HAT_LOAD_LOCK : HAT_LOAD)); 10367c478bd9Sstevel@tonic-gate } else if (seg == &kvseg && dp == NULL) { 10377c478bd9Sstevel@tonic-gate hat_devload(kas.a_hat, addr, MMU_PAGESIZE, pfn, prot, 10387c478bd9Sstevel@tonic-gate HAT_LOAD_LOCK); 10397c478bd9Sstevel@tonic-gate } else 10407c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 10417c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 10427c478bd9Sstevel@tonic-gate } 10437c478bd9Sstevel@tonic-gate 10447c478bd9Sstevel@tonic-gate 10457c478bd9Sstevel@tonic-gate /* 104612f080e7Smrj * rootnex_map_regspec() 104712f080e7Smrj * we don't support mapping of I/O cards above 4Gb 10487c478bd9Sstevel@tonic-gate */ 10497c478bd9Sstevel@tonic-gate static int 105012f080e7Smrj rootnex_map_regspec(ddi_map_req_t *mp, caddr_t *vaddrp) 10517c478bd9Sstevel@tonic-gate { 105212f080e7Smrj ulong_t base; 105312f080e7Smrj void *cvaddr; 105412f080e7Smrj uint_t npages, pgoffset; 105512f080e7Smrj struct regspec *rp; 105612f080e7Smrj ddi_acc_hdl_t *hp; 105712f080e7Smrj ddi_acc_impl_t *ap; 105812f080e7Smrj uint_t hat_acc_flags; 10597c478bd9Sstevel@tonic-gate 106012f080e7Smrj rp = mp->map_obj.rp; 106112f080e7Smrj hp = mp->map_handlep; 106212f080e7Smrj 106312f080e7Smrj #ifdef DDI_MAP_DEBUG 106412f080e7Smrj ddi_map_debug( 106512f080e7Smrj "rootnex_map_regspec: <0x%x 0x%x 0x%x> handle 0x%x\n", 106612f080e7Smrj rp->regspec_bustype, rp->regspec_addr, 106712f080e7Smrj rp->regspec_size, mp->map_handlep); 106812f080e7Smrj #endif /* DDI_MAP_DEBUG */ 10697c478bd9Sstevel@tonic-gate 10707c478bd9Sstevel@tonic-gate /* 107112f080e7Smrj * I/O or memory mapping 107212f080e7Smrj * 107312f080e7Smrj * <bustype=0, addr=x, len=x>: memory 107412f080e7Smrj * <bustype=1, addr=x, len=x>: i/o 107512f080e7Smrj * <bustype>1, addr=0, len=x>: x86-compatibility i/o 10767c478bd9Sstevel@tonic-gate */ 107712f080e7Smrj 107812f080e7Smrj if (rp->regspec_bustype > 1 && rp->regspec_addr != 0) { 107912f080e7Smrj cmn_err(CE_WARN, "rootnex: invalid register spec" 108012f080e7Smrj " <0x%x, 0x%x, 0x%x>", rp->regspec_bustype, 108112f080e7Smrj rp->regspec_addr, rp->regspec_size); 108212f080e7Smrj return (DDI_FAILURE); 10837c478bd9Sstevel@tonic-gate } 108412f080e7Smrj 108512f080e7Smrj if (rp->regspec_bustype != 0) { 10867c478bd9Sstevel@tonic-gate /* 108712f080e7Smrj * I/O space - needs a handle. 10887c478bd9Sstevel@tonic-gate */ 10897c478bd9Sstevel@tonic-gate if (hp == NULL) { 109012f080e7Smrj return (DDI_FAILURE); 10917c478bd9Sstevel@tonic-gate } 109212f080e7Smrj ap = (ddi_acc_impl_t *)hp->ah_platform_private; 109312f080e7Smrj ap->ahi_acc_attr |= DDI_ACCATTR_IO_SPACE; 109412f080e7Smrj impl_acc_hdl_init(hp); 10957c478bd9Sstevel@tonic-gate 109612f080e7Smrj if (mp->map_flags & DDI_MF_DEVICE_MAPPING) { 109712f080e7Smrj #ifdef DDI_MAP_DEBUG 109812f080e7Smrj ddi_map_debug("rootnex_map_regspec: mmap() \ 109912f080e7Smrj to I/O space is not supported.\n"); 110012f080e7Smrj #endif /* DDI_MAP_DEBUG */ 110112f080e7Smrj return (DDI_ME_INVAL); 11027c478bd9Sstevel@tonic-gate } else { 11037c478bd9Sstevel@tonic-gate /* 110412f080e7Smrj * 1275-compliant vs. compatibility i/o mapping 11057c478bd9Sstevel@tonic-gate */ 110612f080e7Smrj *vaddrp = 110712f080e7Smrj (rp->regspec_bustype > 1 && rp->regspec_addr == 0) ? 110812f080e7Smrj ((caddr_t)(uintptr_t)rp->regspec_bustype) : 110912f080e7Smrj ((caddr_t)(uintptr_t)rp->regspec_addr); 11107c478bd9Sstevel@tonic-gate } 11117c478bd9Sstevel@tonic-gate 111212f080e7Smrj #ifdef DDI_MAP_DEBUG 111312f080e7Smrj ddi_map_debug( 111412f080e7Smrj "rootnex_map_regspec: \"Mapping\" %d bytes I/O space at 0x%x\n", 111512f080e7Smrj rp->regspec_size, *vaddrp); 111612f080e7Smrj #endif /* DDI_MAP_DEBUG */ 111712f080e7Smrj return (DDI_SUCCESS); 11187c478bd9Sstevel@tonic-gate } 11197c478bd9Sstevel@tonic-gate 11207c478bd9Sstevel@tonic-gate /* 112112f080e7Smrj * Memory space 112212f080e7Smrj */ 112312f080e7Smrj 112412f080e7Smrj if (hp != NULL) { 112512f080e7Smrj /* 112612f080e7Smrj * hat layer ignores 112712f080e7Smrj * hp->ah_acc.devacc_attr_endian_flags. 112812f080e7Smrj */ 112912f080e7Smrj switch (hp->ah_acc.devacc_attr_dataorder) { 113012f080e7Smrj case DDI_STRICTORDER_ACC: 113112f080e7Smrj hat_acc_flags = HAT_STRICTORDER; 113212f080e7Smrj break; 113312f080e7Smrj case DDI_UNORDERED_OK_ACC: 113412f080e7Smrj hat_acc_flags = HAT_UNORDERED_OK; 113512f080e7Smrj break; 113612f080e7Smrj case DDI_MERGING_OK_ACC: 113712f080e7Smrj hat_acc_flags = HAT_MERGING_OK; 113812f080e7Smrj break; 113912f080e7Smrj case DDI_LOADCACHING_OK_ACC: 114012f080e7Smrj hat_acc_flags = HAT_LOADCACHING_OK; 114112f080e7Smrj break; 114212f080e7Smrj case DDI_STORECACHING_OK_ACC: 114312f080e7Smrj hat_acc_flags = HAT_STORECACHING_OK; 114412f080e7Smrj break; 114512f080e7Smrj } 114612f080e7Smrj ap = (ddi_acc_impl_t *)hp->ah_platform_private; 114712f080e7Smrj ap->ahi_acc_attr |= DDI_ACCATTR_CPU_VADDR; 114812f080e7Smrj impl_acc_hdl_init(hp); 114912f080e7Smrj hp->ah_hat_flags = hat_acc_flags; 115012f080e7Smrj } else { 115112f080e7Smrj hat_acc_flags = HAT_STRICTORDER; 115212f080e7Smrj } 115312f080e7Smrj 115412f080e7Smrj base = (ulong_t)rp->regspec_addr & (~MMU_PAGEOFFSET); /* base addr */ 115512f080e7Smrj pgoffset = (ulong_t)rp->regspec_addr & MMU_PAGEOFFSET; /* offset */ 115612f080e7Smrj 115712f080e7Smrj if (rp->regspec_size == 0) { 115812f080e7Smrj #ifdef DDI_MAP_DEBUG 115912f080e7Smrj ddi_map_debug("rootnex_map_regspec: zero regspec_size\n"); 116012f080e7Smrj #endif /* DDI_MAP_DEBUG */ 116112f080e7Smrj return (DDI_ME_INVAL); 116212f080e7Smrj } 116312f080e7Smrj 116412f080e7Smrj if (mp->map_flags & DDI_MF_DEVICE_MAPPING) { 116512f080e7Smrj *vaddrp = (caddr_t)mmu_btop(base); 116612f080e7Smrj } else { 116712f080e7Smrj npages = mmu_btopr(rp->regspec_size + pgoffset); 116812f080e7Smrj 116912f080e7Smrj #ifdef DDI_MAP_DEBUG 117012f080e7Smrj ddi_map_debug("rootnex_map_regspec: Mapping %d pages \ 117112f080e7Smrj physical %x ", 117212f080e7Smrj npages, base); 117312f080e7Smrj #endif /* DDI_MAP_DEBUG */ 117412f080e7Smrj 117512f080e7Smrj cvaddr = device_arena_alloc(ptob(npages), VM_NOSLEEP); 117612f080e7Smrj if (cvaddr == NULL) 117712f080e7Smrj return (DDI_ME_NORESOURCES); 117812f080e7Smrj 117912f080e7Smrj /* 118012f080e7Smrj * Now map in the pages we've allocated... 118112f080e7Smrj */ 118212f080e7Smrj hat_devload(kas.a_hat, cvaddr, mmu_ptob(npages), mmu_btop(base), 118312f080e7Smrj mp->map_prot | hat_acc_flags, HAT_LOAD_LOCK); 118412f080e7Smrj *vaddrp = (caddr_t)cvaddr + pgoffset; 118512f080e7Smrj } 118612f080e7Smrj 118712f080e7Smrj #ifdef DDI_MAP_DEBUG 118812f080e7Smrj ddi_map_debug("at virtual 0x%x\n", *vaddrp); 118912f080e7Smrj #endif /* DDI_MAP_DEBUG */ 119012f080e7Smrj return (DDI_SUCCESS); 119112f080e7Smrj } 119212f080e7Smrj 119312f080e7Smrj 119412f080e7Smrj /* 119512f080e7Smrj * rootnex_unmap_regspec() 11967c478bd9Sstevel@tonic-gate * 11977c478bd9Sstevel@tonic-gate */ 11987c478bd9Sstevel@tonic-gate static int 119912f080e7Smrj rootnex_unmap_regspec(ddi_map_req_t *mp, caddr_t *vaddrp) 12007c478bd9Sstevel@tonic-gate { 120112f080e7Smrj caddr_t addr = (caddr_t)*vaddrp; 120212f080e7Smrj uint_t npages, pgoffset; 120312f080e7Smrj struct regspec *rp; 12047c478bd9Sstevel@tonic-gate 120512f080e7Smrj if (mp->map_flags & DDI_MF_DEVICE_MAPPING) 120612f080e7Smrj return (0); 12077c478bd9Sstevel@tonic-gate 120812f080e7Smrj rp = mp->map_obj.rp; 12097c478bd9Sstevel@tonic-gate 121012f080e7Smrj if (rp->regspec_size == 0) { 121112f080e7Smrj #ifdef DDI_MAP_DEBUG 121212f080e7Smrj ddi_map_debug("rootnex_unmap_regspec: zero regspec_size\n"); 121312f080e7Smrj #endif /* DDI_MAP_DEBUG */ 121412f080e7Smrj return (DDI_ME_INVAL); 12157c478bd9Sstevel@tonic-gate } 12167c478bd9Sstevel@tonic-gate 12177c478bd9Sstevel@tonic-gate /* 121812f080e7Smrj * I/O or memory mapping: 12197c478bd9Sstevel@tonic-gate * 122012f080e7Smrj * <bustype=0, addr=x, len=x>: memory 122112f080e7Smrj * <bustype=1, addr=x, len=x>: i/o 122212f080e7Smrj * <bustype>1, addr=0, len=x>: x86-compatibility i/o 12237c478bd9Sstevel@tonic-gate */ 122412f080e7Smrj if (rp->regspec_bustype != 0) { 12257c478bd9Sstevel@tonic-gate /* 122612f080e7Smrj * This is I/O space, which requires no particular 122712f080e7Smrj * processing on unmap since it isn't mapped in the 122812f080e7Smrj * first place. 12297c478bd9Sstevel@tonic-gate */ 12307c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12317c478bd9Sstevel@tonic-gate } 12327c478bd9Sstevel@tonic-gate 12337c478bd9Sstevel@tonic-gate /* 123412f080e7Smrj * Memory space 12357c478bd9Sstevel@tonic-gate */ 123612f080e7Smrj pgoffset = (uintptr_t)addr & MMU_PAGEOFFSET; 123712f080e7Smrj npages = mmu_btopr(rp->regspec_size + pgoffset); 123812f080e7Smrj hat_unload(kas.a_hat, addr - pgoffset, ptob(npages), HAT_UNLOAD_UNLOCK); 123912f080e7Smrj device_arena_free(addr - pgoffset, ptob(npages)); 12407c478bd9Sstevel@tonic-gate 12417c478bd9Sstevel@tonic-gate /* 124212f080e7Smrj * Destroy the pointer - the mapping has logically gone 12437c478bd9Sstevel@tonic-gate */ 124412f080e7Smrj *vaddrp = NULL; 12457c478bd9Sstevel@tonic-gate 12467c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 12477c478bd9Sstevel@tonic-gate } 12487c478bd9Sstevel@tonic-gate 124912f080e7Smrj 125012f080e7Smrj /* 125112f080e7Smrj * rootnex_map_handle() 125212f080e7Smrj * 125312f080e7Smrj */ 12547c478bd9Sstevel@tonic-gate static int 125512f080e7Smrj rootnex_map_handle(ddi_map_req_t *mp) 12567c478bd9Sstevel@tonic-gate { 125712f080e7Smrj ddi_acc_hdl_t *hp; 125812f080e7Smrj ulong_t base; 125912f080e7Smrj uint_t pgoffset; 126012f080e7Smrj struct regspec *rp; 12617c478bd9Sstevel@tonic-gate 126212f080e7Smrj rp = mp->map_obj.rp; 12637c478bd9Sstevel@tonic-gate 126412f080e7Smrj #ifdef DDI_MAP_DEBUG 126512f080e7Smrj ddi_map_debug( 126612f080e7Smrj "rootnex_map_handle: <0x%x 0x%x 0x%x> handle 0x%x\n", 126712f080e7Smrj rp->regspec_bustype, rp->regspec_addr, 126812f080e7Smrj rp->regspec_size, mp->map_handlep); 126912f080e7Smrj #endif /* DDI_MAP_DEBUG */ 12707c478bd9Sstevel@tonic-gate 12717c478bd9Sstevel@tonic-gate /* 127212f080e7Smrj * I/O or memory mapping: 127312f080e7Smrj * 127412f080e7Smrj * <bustype=0, addr=x, len=x>: memory 127512f080e7Smrj * <bustype=1, addr=x, len=x>: i/o 127612f080e7Smrj * <bustype>1, addr=0, len=x>: x86-compatibility i/o 12777c478bd9Sstevel@tonic-gate */ 127812f080e7Smrj if (rp->regspec_bustype != 0) { 127912f080e7Smrj /* 128012f080e7Smrj * This refers to I/O space, and we don't support "mapping" 128112f080e7Smrj * I/O space to a user. 128212f080e7Smrj */ 12837c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 12847c478bd9Sstevel@tonic-gate } 12857c478bd9Sstevel@tonic-gate 12867c478bd9Sstevel@tonic-gate /* 128712f080e7Smrj * Set up the hat_flags for the mapping. 12887c478bd9Sstevel@tonic-gate */ 128912f080e7Smrj hp = mp->map_handlep; 12907c478bd9Sstevel@tonic-gate 129112f080e7Smrj switch (hp->ah_acc.devacc_attr_endian_flags) { 129212f080e7Smrj case DDI_NEVERSWAP_ACC: 129312f080e7Smrj hp->ah_hat_flags = HAT_NEVERSWAP | HAT_STRICTORDER; 12947c478bd9Sstevel@tonic-gate break; 129512f080e7Smrj case DDI_STRUCTURE_LE_ACC: 129612f080e7Smrj hp->ah_hat_flags = HAT_STRUCTURE_LE; 12977c478bd9Sstevel@tonic-gate break; 129812f080e7Smrj case DDI_STRUCTURE_BE_ACC: 12997c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13007c478bd9Sstevel@tonic-gate default: 130112f080e7Smrj return (DDI_REGS_ACC_CONFLICT); 13027c478bd9Sstevel@tonic-gate } 13037c478bd9Sstevel@tonic-gate 130412f080e7Smrj switch (hp->ah_acc.devacc_attr_dataorder) { 130512f080e7Smrj case DDI_STRICTORDER_ACC: 13067c478bd9Sstevel@tonic-gate break; 130712f080e7Smrj case DDI_UNORDERED_OK_ACC: 130812f080e7Smrj hp->ah_hat_flags |= HAT_UNORDERED_OK; 13097c478bd9Sstevel@tonic-gate break; 131012f080e7Smrj case DDI_MERGING_OK_ACC: 131112f080e7Smrj hp->ah_hat_flags |= HAT_MERGING_OK; 13127c478bd9Sstevel@tonic-gate break; 131312f080e7Smrj case DDI_LOADCACHING_OK_ACC: 131412f080e7Smrj hp->ah_hat_flags |= HAT_LOADCACHING_OK; 131512f080e7Smrj break; 131612f080e7Smrj case DDI_STORECACHING_OK_ACC: 131712f080e7Smrj hp->ah_hat_flags |= HAT_STORECACHING_OK; 131812f080e7Smrj break; 13197c478bd9Sstevel@tonic-gate default: 13207c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13217c478bd9Sstevel@tonic-gate } 13227c478bd9Sstevel@tonic-gate 132312f080e7Smrj base = (ulong_t)rp->regspec_addr & (~MMU_PAGEOFFSET); /* base addr */ 132412f080e7Smrj pgoffset = (ulong_t)rp->regspec_addr & MMU_PAGEOFFSET; /* offset */ 13257c478bd9Sstevel@tonic-gate 132612f080e7Smrj if (rp->regspec_size == 0) 132712f080e7Smrj return (DDI_ME_INVAL); 13287c478bd9Sstevel@tonic-gate 132912f080e7Smrj hp->ah_pfn = mmu_btop(base); 133012f080e7Smrj hp->ah_pnum = mmu_btopr(rp->regspec_size + pgoffset); 13317c478bd9Sstevel@tonic-gate 13327c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 13337c478bd9Sstevel@tonic-gate } 13347c478bd9Sstevel@tonic-gate 133512f080e7Smrj 133612f080e7Smrj 13377c478bd9Sstevel@tonic-gate /* 133812f080e7Smrj * ************************ 133912f080e7Smrj * interrupt related code 134012f080e7Smrj * ************************ 13417c478bd9Sstevel@tonic-gate */ 13427c478bd9Sstevel@tonic-gate 13437c478bd9Sstevel@tonic-gate /* 134412f080e7Smrj * rootnex_intr_ops() 13457c478bd9Sstevel@tonic-gate * bus_intr_op() function for interrupt support 13467c478bd9Sstevel@tonic-gate */ 13477c478bd9Sstevel@tonic-gate /* ARGSUSED */ 13487c478bd9Sstevel@tonic-gate static int 13497c478bd9Sstevel@tonic-gate rootnex_intr_ops(dev_info_t *pdip, dev_info_t *rdip, ddi_intr_op_t intr_op, 13507c478bd9Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 13517c478bd9Sstevel@tonic-gate { 13527c478bd9Sstevel@tonic-gate struct intrspec *ispec; 13537c478bd9Sstevel@tonic-gate struct ddi_parent_private_data *pdp; 13547c478bd9Sstevel@tonic-gate 13557c478bd9Sstevel@tonic-gate DDI_INTR_NEXDBG((CE_CONT, 13567c478bd9Sstevel@tonic-gate "rootnex_intr_ops: pdip = %p, rdip = %p, intr_op = %x, hdlp = %p\n", 13577c478bd9Sstevel@tonic-gate (void *)pdip, (void *)rdip, intr_op, (void *)hdlp)); 13587c478bd9Sstevel@tonic-gate 13597c478bd9Sstevel@tonic-gate /* Process the interrupt operation */ 13607c478bd9Sstevel@tonic-gate switch (intr_op) { 13617c478bd9Sstevel@tonic-gate case DDI_INTROP_GETCAP: 13627c478bd9Sstevel@tonic-gate /* First check with pcplusmp */ 13637c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 13647c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13657c478bd9Sstevel@tonic-gate 13667c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_GET_CAP, result)) { 13677c478bd9Sstevel@tonic-gate *(int *)result = 0; 13687c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13697c478bd9Sstevel@tonic-gate } 13707c478bd9Sstevel@tonic-gate break; 13717c478bd9Sstevel@tonic-gate case DDI_INTROP_SETCAP: 13727c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 13737c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13747c478bd9Sstevel@tonic-gate 13757c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_CAP, result)) 13767c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13777c478bd9Sstevel@tonic-gate break; 13787c478bd9Sstevel@tonic-gate case DDI_INTROP_ALLOC: 13797c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 13807c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 13817c478bd9Sstevel@tonic-gate hdlp->ih_pri = ispec->intrspec_pri; 13827c478bd9Sstevel@tonic-gate *(int *)result = hdlp->ih_scratch1; 13837c478bd9Sstevel@tonic-gate break; 13847c478bd9Sstevel@tonic-gate case DDI_INTROP_FREE: 13857c478bd9Sstevel@tonic-gate pdp = ddi_get_parent_data(rdip); 13867c478bd9Sstevel@tonic-gate /* 13877c478bd9Sstevel@tonic-gate * Special case for 'pcic' driver' only. 13887c478bd9Sstevel@tonic-gate * If an intrspec was created for it, clean it up here 13897c478bd9Sstevel@tonic-gate * See detailed comments on this in the function 13907c478bd9Sstevel@tonic-gate * rootnex_get_ispec(). 13917c478bd9Sstevel@tonic-gate */ 13927c478bd9Sstevel@tonic-gate if (pdp->par_intr && strcmp(ddi_get_name(rdip), "pcic") == 0) { 13937c478bd9Sstevel@tonic-gate kmem_free(pdp->par_intr, sizeof (struct intrspec) * 13947c478bd9Sstevel@tonic-gate pdp->par_nintr); 13957c478bd9Sstevel@tonic-gate /* 13967c478bd9Sstevel@tonic-gate * Set it to zero; so that 13977c478bd9Sstevel@tonic-gate * DDI framework doesn't free it again 13987c478bd9Sstevel@tonic-gate */ 13997c478bd9Sstevel@tonic-gate pdp->par_intr = NULL; 14007c478bd9Sstevel@tonic-gate pdp->par_nintr = 0; 14017c478bd9Sstevel@tonic-gate } 14027c478bd9Sstevel@tonic-gate break; 14037c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPRI: 14047c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 14057c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14067c478bd9Sstevel@tonic-gate *(int *)result = ispec->intrspec_pri; 14077c478bd9Sstevel@tonic-gate break; 14087c478bd9Sstevel@tonic-gate case DDI_INTROP_SETPRI: 14097c478bd9Sstevel@tonic-gate /* Validate the interrupt priority passed to us */ 14107c478bd9Sstevel@tonic-gate if (*(int *)result > LOCK_LEVEL) 14117c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14127c478bd9Sstevel@tonic-gate 14137c478bd9Sstevel@tonic-gate /* Ensure that PSM is all initialized and ispec is ok */ 14147c478bd9Sstevel@tonic-gate if ((psm_intr_ops == NULL) || 14157c478bd9Sstevel@tonic-gate ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL)) 14167c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14177c478bd9Sstevel@tonic-gate 14187c478bd9Sstevel@tonic-gate /* Change the priority */ 14197c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_PRI, result) == 14207c478bd9Sstevel@tonic-gate PSM_FAILURE) 14217c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14227c478bd9Sstevel@tonic-gate 14237c478bd9Sstevel@tonic-gate /* update the ispec with the new priority */ 14247c478bd9Sstevel@tonic-gate ispec->intrspec_pri = *(int *)result; 14257c478bd9Sstevel@tonic-gate break; 14267c478bd9Sstevel@tonic-gate case DDI_INTROP_ADDISR: 14277c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 14287c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14297c478bd9Sstevel@tonic-gate ispec->intrspec_func = hdlp->ih_cb_func; 14307c478bd9Sstevel@tonic-gate break; 14317c478bd9Sstevel@tonic-gate case DDI_INTROP_REMISR: 14327c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 14337c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14347c478bd9Sstevel@tonic-gate ispec->intrspec_func = (uint_t (*)()) 0; 14357c478bd9Sstevel@tonic-gate break; 14367c478bd9Sstevel@tonic-gate case DDI_INTROP_ENABLE: 14377c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 14387c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14397c478bd9Sstevel@tonic-gate 14407c478bd9Sstevel@tonic-gate /* Call psmi to translate irq with the dip */ 14417c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14427c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14437c478bd9Sstevel@tonic-gate 14447a364d25Sschwartz ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec; 14457c478bd9Sstevel@tonic-gate (void) (*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_XLATE_VECTOR, 14467c478bd9Sstevel@tonic-gate (int *)&hdlp->ih_vector); 14477c478bd9Sstevel@tonic-gate 14487c478bd9Sstevel@tonic-gate /* Add the interrupt handler */ 14497c478bd9Sstevel@tonic-gate if (!add_avintr((void *)hdlp, ispec->intrspec_pri, 14507c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, DEVI(rdip)->devi_name, hdlp->ih_vector, 14517a364d25Sschwartz hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, NULL, rdip)) 14527c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14537c478bd9Sstevel@tonic-gate break; 14547c478bd9Sstevel@tonic-gate case DDI_INTROP_DISABLE: 14557c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 14567c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14577c478bd9Sstevel@tonic-gate 14587c478bd9Sstevel@tonic-gate /* Call psm_ops() to translate irq with the dip */ 14597c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14607c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14617c478bd9Sstevel@tonic-gate 14627a364d25Sschwartz ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispec; 14637c478bd9Sstevel@tonic-gate (void) (*psm_intr_ops)(rdip, hdlp, 14647c478bd9Sstevel@tonic-gate PSM_INTR_OP_XLATE_VECTOR, (int *)&hdlp->ih_vector); 14657c478bd9Sstevel@tonic-gate 14667c478bd9Sstevel@tonic-gate /* Remove the interrupt handler */ 14677c478bd9Sstevel@tonic-gate rem_avintr((void *)hdlp, ispec->intrspec_pri, 14687c478bd9Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_vector); 14697c478bd9Sstevel@tonic-gate break; 14707c478bd9Sstevel@tonic-gate case DDI_INTROP_SETMASK: 14717c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14727c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14737c478bd9Sstevel@tonic-gate 14747c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_SET_MASK, NULL)) 14757c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14767c478bd9Sstevel@tonic-gate break; 14777c478bd9Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 14787c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14797c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14807c478bd9Sstevel@tonic-gate 14817c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_CLEAR_MASK, NULL)) 14827c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14837c478bd9Sstevel@tonic-gate break; 14847c478bd9Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 14857c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) 14867c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14877c478bd9Sstevel@tonic-gate 14887c478bd9Sstevel@tonic-gate if ((*psm_intr_ops)(rdip, hdlp, PSM_INTR_OP_GET_PENDING, 14897c478bd9Sstevel@tonic-gate result)) { 14907c478bd9Sstevel@tonic-gate *(int *)result = 0; 14917c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14927c478bd9Sstevel@tonic-gate } 14937c478bd9Sstevel@tonic-gate break; 14947c478bd9Sstevel@tonic-gate case DDI_INTROP_NINTRS: 14957c478bd9Sstevel@tonic-gate if ((pdp = ddi_get_parent_data(rdip)) == NULL) 14967c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 14977c478bd9Sstevel@tonic-gate *(int *)result = pdp->par_nintr; 14987c478bd9Sstevel@tonic-gate if (pdp->par_nintr == 0) { 14997c478bd9Sstevel@tonic-gate /* 15007c478bd9Sstevel@tonic-gate * Special case for 'pcic' driver' only. This driver 15017c478bd9Sstevel@tonic-gate * driver is a child of 'isa' and 'rootnex' drivers. 15027c478bd9Sstevel@tonic-gate * 15037c478bd9Sstevel@tonic-gate * See detailed comments on this in the function 15047c478bd9Sstevel@tonic-gate * rootnex_get_ispec(). 15057c478bd9Sstevel@tonic-gate * 15067c478bd9Sstevel@tonic-gate * Children of 'pcic' send 'NINITR' request all the 15077c478bd9Sstevel@tonic-gate * way to rootnex driver. But, the 'pdp->par_nintr' 15087c478bd9Sstevel@tonic-gate * field may not initialized. So, we fake it here 15097c478bd9Sstevel@tonic-gate * to return 1 (a la what PCMCIA nexus does). 15107c478bd9Sstevel@tonic-gate */ 15117c478bd9Sstevel@tonic-gate if (strcmp(ddi_get_name(rdip), "pcic") == 0) 15127c478bd9Sstevel@tonic-gate *(int *)result = 1; 15137c478bd9Sstevel@tonic-gate } 15147c478bd9Sstevel@tonic-gate break; 15157c478bd9Sstevel@tonic-gate case DDI_INTROP_SUPPORTED_TYPES: 15167c478bd9Sstevel@tonic-gate *(int *)result = 0; 15177c478bd9Sstevel@tonic-gate *(int *)result |= DDI_INTR_TYPE_FIXED; /* Always ... */ 15187c478bd9Sstevel@tonic-gate break; 15197c478bd9Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 15207c478bd9Sstevel@tonic-gate if ((ispec = rootnex_get_ispec(rdip, hdlp->ih_inum)) == NULL) 15217c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 15227c478bd9Sstevel@tonic-gate 15237c478bd9Sstevel@tonic-gate if (psm_intr_ops == NULL) { 15247c478bd9Sstevel@tonic-gate *(int *)result = 1; 15257c478bd9Sstevel@tonic-gate break; 15267c478bd9Sstevel@tonic-gate } 15277c478bd9Sstevel@tonic-gate 15287c478bd9Sstevel@tonic-gate /* Priority in the handle not initialized yet */ 15297c478bd9Sstevel@tonic-gate hdlp->ih_pri = ispec->intrspec_pri; 15307c478bd9Sstevel@tonic-gate (void) (*psm_intr_ops)(rdip, hdlp, 15317c478bd9Sstevel@tonic-gate PSM_INTR_OP_NAVAIL_VECTORS, result); 15327c478bd9Sstevel@tonic-gate break; 15337c478bd9Sstevel@tonic-gate default: 15347c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 15357c478bd9Sstevel@tonic-gate } 15367c478bd9Sstevel@tonic-gate 15377c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 15387c478bd9Sstevel@tonic-gate } 15397c478bd9Sstevel@tonic-gate 15407c478bd9Sstevel@tonic-gate 15417c478bd9Sstevel@tonic-gate /* 154212f080e7Smrj * rootnex_get_ispec() 154312f080e7Smrj * convert an interrupt number to an interrupt specification. 154412f080e7Smrj * The interrupt number determines which interrupt spec will be 154512f080e7Smrj * returned if more than one exists. 154612f080e7Smrj * 154712f080e7Smrj * Look into the parent private data area of the 'rdip' to find out 154812f080e7Smrj * the interrupt specification. First check to make sure there is 154912f080e7Smrj * one that matchs "inumber" and then return a pointer to it. 155012f080e7Smrj * 155112f080e7Smrj * Return NULL if one could not be found. 155212f080e7Smrj * 155312f080e7Smrj * NOTE: This is needed for rootnex_intr_ops() 15547c478bd9Sstevel@tonic-gate */ 155512f080e7Smrj static struct intrspec * 155612f080e7Smrj rootnex_get_ispec(dev_info_t *rdip, int inum) 15577c478bd9Sstevel@tonic-gate { 155812f080e7Smrj struct ddi_parent_private_data *pdp = ddi_get_parent_data(rdip); 15597c478bd9Sstevel@tonic-gate 15607c478bd9Sstevel@tonic-gate /* 156112f080e7Smrj * Special case handling for drivers that provide their own 156212f080e7Smrj * intrspec structures instead of relying on the DDI framework. 156312f080e7Smrj * 156412f080e7Smrj * A broken hardware driver in ON could potentially provide its 156512f080e7Smrj * own intrspec structure, instead of relying on the hardware. 156612f080e7Smrj * If these drivers are children of 'rootnex' then we need to 156712f080e7Smrj * continue to provide backward compatibility to them here. 156812f080e7Smrj * 156912f080e7Smrj * Following check is a special case for 'pcic' driver which 157012f080e7Smrj * was found to have broken hardwre andby provides its own intrspec. 157112f080e7Smrj * 157212f080e7Smrj * Verbatim comments from this driver are shown here: 157312f080e7Smrj * "Don't use the ddi_add_intr since we don't have a 157412f080e7Smrj * default intrspec in all cases." 157512f080e7Smrj * 157612f080e7Smrj * Since an 'ispec' may not be always created for it, 157712f080e7Smrj * check for that and create one if so. 157812f080e7Smrj * 157912f080e7Smrj * NOTE: Currently 'pcic' is the only driver found to do this. 15807c478bd9Sstevel@tonic-gate */ 158112f080e7Smrj if (!pdp->par_intr && strcmp(ddi_get_name(rdip), "pcic") == 0) { 158212f080e7Smrj pdp->par_nintr = 1; 158312f080e7Smrj pdp->par_intr = kmem_zalloc(sizeof (struct intrspec) * 158412f080e7Smrj pdp->par_nintr, KM_SLEEP); 158512f080e7Smrj } 158612f080e7Smrj 158712f080e7Smrj /* Validate the interrupt number */ 158812f080e7Smrj if (inum >= pdp->par_nintr) 158912f080e7Smrj return (NULL); 159012f080e7Smrj 159112f080e7Smrj /* Get the interrupt structure pointer and return that */ 159212f080e7Smrj return ((struct intrspec *)&pdp->par_intr[inum]); 159312f080e7Smrj } 159412f080e7Smrj 159512f080e7Smrj 159612f080e7Smrj /* 159712f080e7Smrj * ****************** 159812f080e7Smrj * dma related code 159912f080e7Smrj * ****************** 160012f080e7Smrj */ 160112f080e7Smrj 160212f080e7Smrj /* 160312f080e7Smrj * rootnex_dma_allochdl() 160412f080e7Smrj * called from ddi_dma_alloc_handle(). 160512f080e7Smrj */ 160612f080e7Smrj /*ARGSUSED*/ 160712f080e7Smrj static int 160812f080e7Smrj rootnex_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attr, 160912f080e7Smrj int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep) 161012f080e7Smrj { 161112f080e7Smrj uint64_t maxsegmentsize_ll; 161212f080e7Smrj uint_t maxsegmentsize; 161312f080e7Smrj ddi_dma_impl_t *hp; 161412f080e7Smrj rootnex_dma_t *dma; 161512f080e7Smrj uint64_t count_max; 161612f080e7Smrj uint64_t seg; 161712f080e7Smrj int kmflag; 161812f080e7Smrj int e; 161912f080e7Smrj 162012f080e7Smrj 162112f080e7Smrj /* convert our sleep flags */ 162212f080e7Smrj if (waitfp == DDI_DMA_SLEEP) { 162312f080e7Smrj kmflag = KM_SLEEP; 162412f080e7Smrj } else { 162512f080e7Smrj kmflag = KM_NOSLEEP; 162612f080e7Smrj } 162712f080e7Smrj 162812f080e7Smrj /* 162912f080e7Smrj * We try to do only one memory allocation here. We'll do a little 163012f080e7Smrj * pointer manipulation later. If the bind ends up taking more than 163112f080e7Smrj * our prealloc's space, we'll have to allocate more memory in the 163212f080e7Smrj * bind operation. Not great, but much better than before and the 163312f080e7Smrj * best we can do with the current bind interfaces. 163412f080e7Smrj */ 163512f080e7Smrj hp = kmem_cache_alloc(rootnex_state->r_dmahdl_cache, kmflag); 163612f080e7Smrj if (hp == NULL) { 163712f080e7Smrj if (waitfp != DDI_DMA_DONTWAIT) { 163812f080e7Smrj ddi_set_callback(waitfp, arg, 163912f080e7Smrj &rootnex_state->r_dvma_call_list_id); 164012f080e7Smrj } 164112f080e7Smrj return (DDI_DMA_NORESOURCES); 164212f080e7Smrj } 164312f080e7Smrj 164412f080e7Smrj /* Do our pointer manipulation now, align the structures */ 164512f080e7Smrj hp->dmai_private = (void *)(((uintptr_t)hp + 164612f080e7Smrj (uintptr_t)sizeof (ddi_dma_impl_t) + 0x7) & ~0x7); 164712f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 164812f080e7Smrj dma->dp_prealloc_buffer = (uchar_t *)(((uintptr_t)dma + 164912f080e7Smrj sizeof (rootnex_dma_t) + 0x7) & ~0x7); 165012f080e7Smrj 165112f080e7Smrj /* setup the handle */ 165212f080e7Smrj rootnex_clean_dmahdl(hp); 165312f080e7Smrj dma->dp_dip = rdip; 165412f080e7Smrj dma->dp_sglinfo.si_min_addr = attr->dma_attr_addr_lo; 165512f080e7Smrj dma->dp_sglinfo.si_max_addr = attr->dma_attr_addr_hi; 165612f080e7Smrj hp->dmai_minxfer = attr->dma_attr_minxfer; 165712f080e7Smrj hp->dmai_burstsizes = attr->dma_attr_burstsizes; 165812f080e7Smrj hp->dmai_rdip = rdip; 165912f080e7Smrj hp->dmai_attr = *attr; 166012f080e7Smrj 166112f080e7Smrj /* we don't need to worry about the SPL since we do a tryenter */ 166212f080e7Smrj mutex_init(&dma->dp_mutex, NULL, MUTEX_DRIVER, NULL); 166312f080e7Smrj 166412f080e7Smrj /* 166512f080e7Smrj * Figure out our maximum segment size. If the segment size is greater 166612f080e7Smrj * than 4G, we will limit it to (4G - 1) since the max size of a dma 166712f080e7Smrj * object (ddi_dma_obj_t.dmao_size) is 32 bits. dma_attr_seg and 166812f080e7Smrj * dma_attr_count_max are size-1 type values. 166912f080e7Smrj * 167012f080e7Smrj * Maximum segment size is the largest physically contiguous chunk of 167112f080e7Smrj * memory that we can return from a bind (i.e. the maximum size of a 167212f080e7Smrj * single cookie). 167312f080e7Smrj */ 167412f080e7Smrj 167512f080e7Smrj /* handle the rollover cases */ 167612f080e7Smrj seg = attr->dma_attr_seg + 1; 167712f080e7Smrj if (seg < attr->dma_attr_seg) { 167812f080e7Smrj seg = attr->dma_attr_seg; 167912f080e7Smrj } 168012f080e7Smrj count_max = attr->dma_attr_count_max + 1; 168112f080e7Smrj if (count_max < attr->dma_attr_count_max) { 168212f080e7Smrj count_max = attr->dma_attr_count_max; 168312f080e7Smrj } 168412f080e7Smrj 168512f080e7Smrj /* 168612f080e7Smrj * granularity may or may not be a power of two. If it isn't, we can't 168712f080e7Smrj * use a simple mask. 168812f080e7Smrj */ 168912f080e7Smrj if (attr->dma_attr_granular & (attr->dma_attr_granular - 1)) { 169012f080e7Smrj dma->dp_granularity_power_2 = B_FALSE; 169112f080e7Smrj } else { 169212f080e7Smrj dma->dp_granularity_power_2 = B_TRUE; 169312f080e7Smrj } 169412f080e7Smrj 169512f080e7Smrj /* 169612f080e7Smrj * maxxfer should be a whole multiple of granularity. If we're going to 169712f080e7Smrj * break up a window because we're greater than maxxfer, we might as 169812f080e7Smrj * well make sure it's maxxfer is a whole multiple so we don't have to 169912f080e7Smrj * worry about triming the window later on for this case. 170012f080e7Smrj */ 170112f080e7Smrj if (attr->dma_attr_granular > 1) { 170212f080e7Smrj if (dma->dp_granularity_power_2) { 170312f080e7Smrj dma->dp_maxxfer = attr->dma_attr_maxxfer - 170412f080e7Smrj (attr->dma_attr_maxxfer & 170512f080e7Smrj (attr->dma_attr_granular - 1)); 170612f080e7Smrj } else { 170712f080e7Smrj dma->dp_maxxfer = attr->dma_attr_maxxfer - 170812f080e7Smrj (attr->dma_attr_maxxfer % attr->dma_attr_granular); 170912f080e7Smrj } 171012f080e7Smrj } else { 171112f080e7Smrj dma->dp_maxxfer = attr->dma_attr_maxxfer; 171212f080e7Smrj } 171312f080e7Smrj 171412f080e7Smrj maxsegmentsize_ll = MIN(seg, dma->dp_maxxfer); 171512f080e7Smrj maxsegmentsize_ll = MIN(maxsegmentsize_ll, count_max); 171612f080e7Smrj if (maxsegmentsize_ll == 0 || (maxsegmentsize_ll > 0xFFFFFFFF)) { 171712f080e7Smrj maxsegmentsize = 0xFFFFFFFF; 171812f080e7Smrj } else { 171912f080e7Smrj maxsegmentsize = maxsegmentsize_ll; 172012f080e7Smrj } 172112f080e7Smrj dma->dp_sglinfo.si_max_cookie_size = maxsegmentsize; 172212f080e7Smrj dma->dp_sglinfo.si_segmask = attr->dma_attr_seg; 172312f080e7Smrj 172412f080e7Smrj /* check the ddi_dma_attr arg to make sure it makes a little sense */ 172512f080e7Smrj if (rootnex_alloc_check_parms) { 172612f080e7Smrj e = rootnex_valid_alloc_parms(attr, maxsegmentsize); 172712f080e7Smrj if (e != DDI_SUCCESS) { 172812f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ALLOC_FAIL]); 172912f080e7Smrj (void) rootnex_dma_freehdl(dip, rdip, 173012f080e7Smrj (ddi_dma_handle_t)hp); 173112f080e7Smrj return (e); 173212f080e7Smrj } 173312f080e7Smrj } 173412f080e7Smrj 173512f080e7Smrj *handlep = (ddi_dma_handle_t)hp; 173612f080e7Smrj 173712f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]); 173812f080e7Smrj DTRACE_PROBE1(rootnex__alloc__handle, uint64_t, 173912f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]); 174012f080e7Smrj 174112f080e7Smrj return (DDI_SUCCESS); 174212f080e7Smrj } 174312f080e7Smrj 174412f080e7Smrj 174512f080e7Smrj /* 174612f080e7Smrj * rootnex_dma_freehdl() 174712f080e7Smrj * called from ddi_dma_free_handle(). 174812f080e7Smrj */ 174912f080e7Smrj /*ARGSUSED*/ 175012f080e7Smrj static int 175112f080e7Smrj rootnex_dma_freehdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle) 175212f080e7Smrj { 175312f080e7Smrj ddi_dma_impl_t *hp; 175412f080e7Smrj rootnex_dma_t *dma; 175512f080e7Smrj 175612f080e7Smrj 175712f080e7Smrj hp = (ddi_dma_impl_t *)handle; 175812f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 175912f080e7Smrj 176012f080e7Smrj /* unbind should have been called first */ 176112f080e7Smrj ASSERT(!dma->dp_inuse); 176212f080e7Smrj 176312f080e7Smrj mutex_destroy(&dma->dp_mutex); 176412f080e7Smrj kmem_cache_free(rootnex_state->r_dmahdl_cache, hp); 176512f080e7Smrj 176612f080e7Smrj ROOTNEX_PROF_DEC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]); 176712f080e7Smrj DTRACE_PROBE1(rootnex__free__handle, uint64_t, 176812f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_HDLS]); 176912f080e7Smrj 177012f080e7Smrj if (rootnex_state->r_dvma_call_list_id) 177112f080e7Smrj ddi_run_callback(&rootnex_state->r_dvma_call_list_id); 177212f080e7Smrj 177312f080e7Smrj return (DDI_SUCCESS); 177412f080e7Smrj } 177512f080e7Smrj 177612f080e7Smrj 177712f080e7Smrj /* 177812f080e7Smrj * rootnex_dma_bindhdl() 177912f080e7Smrj * called from ddi_dma_addr_bind_handle() and ddi_dma_buf_bind_handle(). 178012f080e7Smrj */ 178112f080e7Smrj /*ARGSUSED*/ 178212f080e7Smrj static int 178312f080e7Smrj rootnex_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 178412f080e7Smrj struct ddi_dma_req *dmareq, ddi_dma_cookie_t *cookiep, uint_t *ccountp) 178512f080e7Smrj { 178612f080e7Smrj rootnex_sglinfo_t *sinfo; 178712f080e7Smrj ddi_dma_attr_t *attr; 178812f080e7Smrj ddi_dma_impl_t *hp; 178912f080e7Smrj rootnex_dma_t *dma; 179012f080e7Smrj int kmflag; 179112f080e7Smrj int e; 179212f080e7Smrj 179312f080e7Smrj 179412f080e7Smrj hp = (ddi_dma_impl_t *)handle; 179512f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 179612f080e7Smrj sinfo = &dma->dp_sglinfo; 179712f080e7Smrj attr = &hp->dmai_attr; 179812f080e7Smrj 179912f080e7Smrj hp->dmai_rflags = dmareq->dmar_flags & DMP_DDIFLAGS; 180012f080e7Smrj 180112f080e7Smrj /* 180212f080e7Smrj * This is useful for debugging a driver. Not as useful in a production 180312f080e7Smrj * system. The only time this will fail is if you have a driver bug. 180412f080e7Smrj */ 180512f080e7Smrj if (rootnex_bind_check_inuse) { 180612f080e7Smrj /* 180712f080e7Smrj * No one else should ever have this lock unless someone else 180812f080e7Smrj * is trying to use this handle. So contention on the lock 180912f080e7Smrj * is the same as inuse being set. 181012f080e7Smrj */ 181112f080e7Smrj e = mutex_tryenter(&dma->dp_mutex); 181212f080e7Smrj if (e == 0) { 181312f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 181412f080e7Smrj return (DDI_DMA_INUSE); 181512f080e7Smrj } 181612f080e7Smrj if (dma->dp_inuse) { 181712f080e7Smrj mutex_exit(&dma->dp_mutex); 181812f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 181912f080e7Smrj return (DDI_DMA_INUSE); 182012f080e7Smrj } 182112f080e7Smrj dma->dp_inuse = B_TRUE; 182212f080e7Smrj mutex_exit(&dma->dp_mutex); 182312f080e7Smrj } 182412f080e7Smrj 182512f080e7Smrj /* check the ddi_dma_attr arg to make sure it makes a little sense */ 182612f080e7Smrj if (rootnex_bind_check_parms) { 182712f080e7Smrj e = rootnex_valid_bind_parms(dmareq, attr); 182812f080e7Smrj if (e != DDI_SUCCESS) { 182912f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 183012f080e7Smrj rootnex_clean_dmahdl(hp); 183112f080e7Smrj return (e); 183212f080e7Smrj } 183312f080e7Smrj } 183412f080e7Smrj 183512f080e7Smrj /* save away the original bind info */ 183612f080e7Smrj dma->dp_dma = dmareq->dmar_object; 183712f080e7Smrj 183812f080e7Smrj /* 183912f080e7Smrj * Figure out a rough estimate of what maximum number of pages this 184012f080e7Smrj * buffer could use (a high estimate of course). 184112f080e7Smrj */ 184212f080e7Smrj sinfo->si_max_pages = mmu_btopr(dma->dp_dma.dmao_size) + 1; 184312f080e7Smrj 184412f080e7Smrj /* 184512f080e7Smrj * We'll use the pre-allocated cookies for any bind that will *always* 184612f080e7Smrj * fit (more important to be consistent, we don't want to create 184712f080e7Smrj * additional degenerate cases). 184812f080e7Smrj */ 184912f080e7Smrj if (sinfo->si_max_pages <= rootnex_state->r_prealloc_cookies) { 185012f080e7Smrj dma->dp_cookies = (ddi_dma_cookie_t *)dma->dp_prealloc_buffer; 185112f080e7Smrj dma->dp_need_to_free_cookie = B_FALSE; 185212f080e7Smrj DTRACE_PROBE2(rootnex__bind__prealloc, dev_info_t *, rdip, 185312f080e7Smrj uint_t, sinfo->si_max_pages); 185412f080e7Smrj 185512f080e7Smrj /* 185612f080e7Smrj * For anything larger than that, we'll go ahead and allocate the 185712f080e7Smrj * maximum number of pages we expect to see. Hopefuly, we won't be 185812f080e7Smrj * seeing this path in the fast path for high performance devices very 185912f080e7Smrj * frequently. 186012f080e7Smrj * 186112f080e7Smrj * a ddi bind interface that allowed the driver to provide storage to 186212f080e7Smrj * the bind interface would speed this case up. 186312f080e7Smrj */ 186412f080e7Smrj } else { 186512f080e7Smrj /* convert the sleep flags */ 186612f080e7Smrj if (dmareq->dmar_fp == DDI_DMA_SLEEP) { 186712f080e7Smrj kmflag = KM_SLEEP; 186812f080e7Smrj } else { 186912f080e7Smrj kmflag = KM_NOSLEEP; 187012f080e7Smrj } 187112f080e7Smrj 187212f080e7Smrj /* 187312f080e7Smrj * Save away how much memory we allocated. If we're doing a 187412f080e7Smrj * nosleep, the alloc could fail... 187512f080e7Smrj */ 187612f080e7Smrj dma->dp_cookie_size = sinfo->si_max_pages * 187712f080e7Smrj sizeof (ddi_dma_cookie_t); 187812f080e7Smrj dma->dp_cookies = kmem_alloc(dma->dp_cookie_size, kmflag); 187912f080e7Smrj if (dma->dp_cookies == NULL) { 188012f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 188112f080e7Smrj rootnex_clean_dmahdl(hp); 188212f080e7Smrj return (DDI_DMA_NORESOURCES); 188312f080e7Smrj } 188412f080e7Smrj dma->dp_need_to_free_cookie = B_TRUE; 188512f080e7Smrj DTRACE_PROBE2(rootnex__bind__alloc, dev_info_t *, rdip, uint_t, 188612f080e7Smrj sinfo->si_max_pages); 188712f080e7Smrj } 188812f080e7Smrj hp->dmai_cookie = dma->dp_cookies; 188912f080e7Smrj 189012f080e7Smrj /* 189112f080e7Smrj * Get the real sgl. rootnex_get_sgl will fill in cookie array while 189212f080e7Smrj * looking at the contraints in the dma structure. It will then put some 189312f080e7Smrj * additional state about the sgl in the dma struct (i.e. is the sgl 189412f080e7Smrj * clean, or do we need to do some munging; how many pages need to be 189512f080e7Smrj * copied, etc.) 189612f080e7Smrj */ 189712f080e7Smrj rootnex_get_sgl(&dmareq->dmar_object, dma->dp_cookies, 189812f080e7Smrj &dma->dp_sglinfo); 189912f080e7Smrj ASSERT(sinfo->si_sgl_size <= sinfo->si_max_pages); 190012f080e7Smrj 190112f080e7Smrj /* if we don't need a copy buffer, we don't need to sync */ 190212f080e7Smrj if (sinfo->si_copybuf_req == 0) { 190312f080e7Smrj hp->dmai_rflags |= DMP_NOSYNC; 190412f080e7Smrj } 190512f080e7Smrj 190612f080e7Smrj /* 190712f080e7Smrj * if we don't need the copybuf and we don't need to do a partial, we 190812f080e7Smrj * hit the fast path. All the high performance devices should be trying 190912f080e7Smrj * to hit this path. To hit this path, a device should be able to reach 191012f080e7Smrj * all of memory, shouldn't try to bind more than it can transfer, and 191112f080e7Smrj * the buffer shouldn't require more cookies than the driver/device can 191212f080e7Smrj * handle [sgllen]). 191312f080e7Smrj */ 191412f080e7Smrj if ((sinfo->si_copybuf_req == 0) && 191512f080e7Smrj (sinfo->si_sgl_size <= attr->dma_attr_sgllen) && 191612f080e7Smrj (dma->dp_dma.dmao_size < dma->dp_maxxfer)) { 191712f080e7Smrj /* 191812f080e7Smrj * copy out the first cookie and ccountp, set the cookie 191912f080e7Smrj * pointer to the second cookie. The first cookie is passed 192012f080e7Smrj * back on the stack. Additional cookies are accessed via 192112f080e7Smrj * ddi_dma_nextcookie() 192212f080e7Smrj */ 192312f080e7Smrj *cookiep = dma->dp_cookies[0]; 192412f080e7Smrj *ccountp = sinfo->si_sgl_size; 192512f080e7Smrj hp->dmai_cookie++; 192612f080e7Smrj hp->dmai_rflags &= ~DDI_DMA_PARTIAL; 192712f080e7Smrj hp->dmai_nwin = 1; 192812f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]); 192912f080e7Smrj DTRACE_PROBE3(rootnex__bind__fast, dev_info_t *, rdip, uint64_t, 193012f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS], uint_t, 193112f080e7Smrj dma->dp_dma.dmao_size); 193212f080e7Smrj return (DDI_DMA_MAPPED); 193312f080e7Smrj } 193412f080e7Smrj 193512f080e7Smrj /* 193612f080e7Smrj * go to the slow path, we may need to alloc more memory, create 193712f080e7Smrj * multiple windows, and munge up a sgl to make the device happy. 193812f080e7Smrj */ 193912f080e7Smrj e = rootnex_bind_slowpath(hp, dmareq, dma, attr, kmflag); 194012f080e7Smrj if ((e != DDI_DMA_MAPPED) && (e != DDI_DMA_PARTIAL_MAP)) { 194112f080e7Smrj if (dma->dp_need_to_free_cookie) { 194212f080e7Smrj kmem_free(dma->dp_cookies, dma->dp_cookie_size); 194312f080e7Smrj } 194412f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_BIND_FAIL]); 194512f080e7Smrj rootnex_clean_dmahdl(hp); /* must be after free cookie */ 194612f080e7Smrj return (e); 194712f080e7Smrj } 194812f080e7Smrj 194912f080e7Smrj /* if the first window uses the copy buffer, sync it for the device */ 195012f080e7Smrj if ((dma->dp_window[dma->dp_current_win].wd_dosync) && 195112f080e7Smrj (hp->dmai_rflags & DDI_DMA_WRITE)) { 195212f080e7Smrj (void) rootnex_dma_sync(dip, rdip, handle, 0, 0, 195312f080e7Smrj DDI_DMA_SYNC_FORDEV); 195412f080e7Smrj } 195512f080e7Smrj 195612f080e7Smrj /* 195712f080e7Smrj * copy out the first cookie and ccountp, set the cookie pointer to the 195812f080e7Smrj * second cookie. Make sure the partial flag is set/cleared correctly. 195912f080e7Smrj * If we have a partial map (i.e. multiple windows), the number of 196012f080e7Smrj * cookies we return is the number of cookies in the first window. 196112f080e7Smrj */ 196212f080e7Smrj if (e == DDI_DMA_MAPPED) { 196312f080e7Smrj hp->dmai_rflags &= ~DDI_DMA_PARTIAL; 196412f080e7Smrj *ccountp = sinfo->si_sgl_size; 196512f080e7Smrj } else { 196612f080e7Smrj hp->dmai_rflags |= DDI_DMA_PARTIAL; 196712f080e7Smrj *ccountp = dma->dp_window[dma->dp_current_win].wd_cookie_cnt; 196812f080e7Smrj ASSERT(hp->dmai_nwin <= dma->dp_max_win); 196912f080e7Smrj } 197012f080e7Smrj *cookiep = dma->dp_cookies[0]; 197112f080e7Smrj hp->dmai_cookie++; 197212f080e7Smrj 197312f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]); 197412f080e7Smrj DTRACE_PROBE3(rootnex__bind__slow, dev_info_t *, rdip, uint64_t, 197512f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS], uint_t, 197612f080e7Smrj dma->dp_dma.dmao_size); 197712f080e7Smrj return (e); 197812f080e7Smrj } 197912f080e7Smrj 198012f080e7Smrj 198112f080e7Smrj /* 198212f080e7Smrj * rootnex_dma_unbindhdl() 198312f080e7Smrj * called from ddi_dma_unbind_handle() 198412f080e7Smrj */ 198512f080e7Smrj /*ARGSUSED*/ 198612f080e7Smrj static int 198712f080e7Smrj rootnex_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 198812f080e7Smrj ddi_dma_handle_t handle) 198912f080e7Smrj { 199012f080e7Smrj ddi_dma_impl_t *hp; 199112f080e7Smrj rootnex_dma_t *dma; 199212f080e7Smrj int e; 199312f080e7Smrj 199412f080e7Smrj 199512f080e7Smrj hp = (ddi_dma_impl_t *)handle; 199612f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 199712f080e7Smrj 199812f080e7Smrj /* make sure the buffer wasn't free'd before calling unbind */ 199912f080e7Smrj if (rootnex_unbind_verify_buffer) { 200012f080e7Smrj e = rootnex_verify_buffer(dma); 200112f080e7Smrj if (e != DDI_SUCCESS) { 200212f080e7Smrj ASSERT(0); 200312f080e7Smrj return (DDI_FAILURE); 200412f080e7Smrj } 200512f080e7Smrj } 200612f080e7Smrj 200712f080e7Smrj /* sync the current window before unbinding the buffer */ 200812f080e7Smrj if (dma->dp_window && dma->dp_window[dma->dp_current_win].wd_dosync && 200912f080e7Smrj (hp->dmai_rflags & DDI_DMA_READ)) { 201012f080e7Smrj (void) rootnex_dma_sync(dip, rdip, handle, 0, 0, 201112f080e7Smrj DDI_DMA_SYNC_FORCPU); 201212f080e7Smrj } 201312f080e7Smrj 201412f080e7Smrj /* 201512f080e7Smrj * cleanup and copy buffer or window state. if we didn't use the copy 201612f080e7Smrj * buffer or windows, there won't be much to do :-) 201712f080e7Smrj */ 201812f080e7Smrj rootnex_teardown_copybuf(dma); 201912f080e7Smrj rootnex_teardown_windows(dma); 202012f080e7Smrj 202112f080e7Smrj /* 202212f080e7Smrj * If we had to allocate space to for the worse case sgl (it didn't 202312f080e7Smrj * fit into our pre-allocate buffer), free that up now 202412f080e7Smrj */ 202512f080e7Smrj if (dma->dp_need_to_free_cookie) { 202612f080e7Smrj kmem_free(dma->dp_cookies, dma->dp_cookie_size); 202712f080e7Smrj } 202812f080e7Smrj 202912f080e7Smrj /* 203012f080e7Smrj * clean up the handle so it's ready for the next bind (i.e. if the 203112f080e7Smrj * handle is reused). 203212f080e7Smrj */ 203312f080e7Smrj rootnex_clean_dmahdl(hp); 203412f080e7Smrj 203512f080e7Smrj if (rootnex_state->r_dvma_call_list_id) 203612f080e7Smrj ddi_run_callback(&rootnex_state->r_dvma_call_list_id); 203712f080e7Smrj 203812f080e7Smrj ROOTNEX_PROF_DEC(&rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]); 203912f080e7Smrj DTRACE_PROBE1(rootnex__unbind, uint64_t, 204012f080e7Smrj rootnex_cnt[ROOTNEX_CNT_ACTIVE_BINDS]); 204112f080e7Smrj 204212f080e7Smrj return (DDI_SUCCESS); 204312f080e7Smrj } 204412f080e7Smrj 204512f080e7Smrj 204612f080e7Smrj /* 204712f080e7Smrj * rootnex_verify_buffer() 204812f080e7Smrj * verify buffer wasn't free'd 204912f080e7Smrj */ 205012f080e7Smrj static int 205112f080e7Smrj rootnex_verify_buffer(rootnex_dma_t *dma) 205212f080e7Smrj { 205312f080e7Smrj peekpoke_ctlops_t peek; 205412f080e7Smrj page_t **pplist; 205512f080e7Smrj caddr_t vaddr; 205612f080e7Smrj uint_t pcnt; 205712f080e7Smrj uint_t poff; 205812f080e7Smrj page_t *pp; 205912f080e7Smrj uint8_t b; 206012f080e7Smrj int i; 206112f080e7Smrj int e; 206212f080e7Smrj 206312f080e7Smrj 206412f080e7Smrj /* Figure out how many pages this buffer occupies */ 206512f080e7Smrj if (dma->dp_dma.dmao_type == DMA_OTYP_PAGES) { 206612f080e7Smrj poff = dma->dp_dma.dmao_obj.pp_obj.pp_offset & MMU_PAGEOFFSET; 206712f080e7Smrj } else { 206812f080e7Smrj vaddr = dma->dp_dma.dmao_obj.virt_obj.v_addr; 206912f080e7Smrj poff = (uintptr_t)vaddr & MMU_PAGEOFFSET; 207012f080e7Smrj } 207112f080e7Smrj pcnt = mmu_btopr(dma->dp_dma.dmao_size + poff); 207212f080e7Smrj 207312f080e7Smrj switch (dma->dp_dma.dmao_type) { 207412f080e7Smrj case DMA_OTYP_PAGES: 207512f080e7Smrj /* 207612f080e7Smrj * for a linked list of pp's walk through them to make sure 207712f080e7Smrj * they're locked and not free. 207812f080e7Smrj */ 207912f080e7Smrj pp = dma->dp_dma.dmao_obj.pp_obj.pp_pp; 208012f080e7Smrj for (i = 0; i < pcnt; i++) { 208112f080e7Smrj if (PP_ISFREE(pp) || !PAGE_LOCKED(pp)) { 208212f080e7Smrj return (DDI_FAILURE); 208312f080e7Smrj } 20847c478bd9Sstevel@tonic-gate pp = pp->p_next; 20857c478bd9Sstevel@tonic-gate } 20867c478bd9Sstevel@tonic-gate break; 208712f080e7Smrj 20887c478bd9Sstevel@tonic-gate case DMA_OTYP_VADDR: 20897c478bd9Sstevel@tonic-gate case DMA_OTYP_BUFVADDR: 209012f080e7Smrj pplist = dma->dp_dma.dmao_obj.virt_obj.v_priv; 209112f080e7Smrj /* 209212f080e7Smrj * for an array of pp's walk through them to make sure they're 209312f080e7Smrj * not free. It's possible that they may not be locked. 209412f080e7Smrj */ 209512f080e7Smrj if (pplist) { 209612f080e7Smrj for (i = 0; i < pcnt; i++) { 209712f080e7Smrj if (PP_ISFREE(pplist[i])) { 209812f080e7Smrj return (DDI_FAILURE); 209912f080e7Smrj } 210012f080e7Smrj } 210112f080e7Smrj 210212f080e7Smrj /* For a virtual address, try to peek at each page */ 210312f080e7Smrj } else { 210412f080e7Smrj if (dma->dp_sglinfo.si_asp == &kas) { 210512f080e7Smrj bzero(&peek, sizeof (peekpoke_ctlops_t)); 210612f080e7Smrj peek.host_addr = (uintptr_t)&b; 210712f080e7Smrj peek.size = sizeof (uint8_t); 210812f080e7Smrj peek.dev_addr = (uintptr_t)vaddr; 210912f080e7Smrj for (i = 0; i < pcnt; i++) { 211012f080e7Smrj e = rootnex_ctlops_peek(&peek, &b); 211112f080e7Smrj if (e != DDI_SUCCESS) { 211212f080e7Smrj return (DDI_FAILURE); 211312f080e7Smrj } 211412f080e7Smrj peek.dev_addr += MMU_PAGESIZE; 211512f080e7Smrj } 211612f080e7Smrj } 211712f080e7Smrj } 211812f080e7Smrj break; 211912f080e7Smrj 212012f080e7Smrj default: 212112f080e7Smrj ASSERT(0); 212212f080e7Smrj break; 212312f080e7Smrj } 212412f080e7Smrj 212512f080e7Smrj return (DDI_SUCCESS); 212612f080e7Smrj } 212712f080e7Smrj 212812f080e7Smrj 212912f080e7Smrj /* 213012f080e7Smrj * rootnex_clean_dmahdl() 213112f080e7Smrj * Clean the dma handle. This should be called on a handle alloc and an 213212f080e7Smrj * unbind handle. Set the handle state to the default settings. 213312f080e7Smrj */ 213412f080e7Smrj static void 213512f080e7Smrj rootnex_clean_dmahdl(ddi_dma_impl_t *hp) 213612f080e7Smrj { 213712f080e7Smrj rootnex_dma_t *dma; 213812f080e7Smrj 213912f080e7Smrj 214012f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 214112f080e7Smrj 214212f080e7Smrj hp->dmai_nwin = 0; 214312f080e7Smrj dma->dp_current_cookie = 0; 214412f080e7Smrj dma->dp_copybuf_size = 0; 214512f080e7Smrj dma->dp_window = NULL; 214612f080e7Smrj dma->dp_cbaddr = NULL; 214712f080e7Smrj dma->dp_inuse = B_FALSE; 214812f080e7Smrj dma->dp_need_to_free_cookie = B_FALSE; 214912f080e7Smrj dma->dp_need_to_free_window = B_FALSE; 215012f080e7Smrj dma->dp_partial_required = B_FALSE; 215112f080e7Smrj dma->dp_trim_required = B_FALSE; 215212f080e7Smrj dma->dp_sglinfo.si_copybuf_req = 0; 215312f080e7Smrj #if !defined(__amd64) 215412f080e7Smrj dma->dp_cb_remaping = B_FALSE; 215512f080e7Smrj dma->dp_kva = NULL; 215612f080e7Smrj #endif 215712f080e7Smrj 215812f080e7Smrj /* FMA related initialization */ 215912f080e7Smrj hp->dmai_fault = 0; 216012f080e7Smrj hp->dmai_fault_check = NULL; 216112f080e7Smrj hp->dmai_fault_notify = NULL; 216212f080e7Smrj hp->dmai_error.err_ena = 0; 216312f080e7Smrj hp->dmai_error.err_status = DDI_FM_OK; 216412f080e7Smrj hp->dmai_error.err_expected = DDI_FM_ERR_UNEXPECTED; 216512f080e7Smrj hp->dmai_error.err_ontrap = NULL; 216612f080e7Smrj hp->dmai_error.err_fep = NULL; 216712f080e7Smrj } 216812f080e7Smrj 216912f080e7Smrj 217012f080e7Smrj /* 217112f080e7Smrj * rootnex_valid_alloc_parms() 217212f080e7Smrj * Called in ddi_dma_alloc_handle path to validate its parameters. 217312f080e7Smrj */ 217412f080e7Smrj static int 217512f080e7Smrj rootnex_valid_alloc_parms(ddi_dma_attr_t *attr, uint_t maxsegmentsize) 217612f080e7Smrj { 217712f080e7Smrj if ((attr->dma_attr_seg < MMU_PAGEOFFSET) || 217812f080e7Smrj (attr->dma_attr_count_max < MMU_PAGEOFFSET) || 217912f080e7Smrj (attr->dma_attr_granular > MMU_PAGESIZE) || 218012f080e7Smrj (attr->dma_attr_maxxfer < MMU_PAGESIZE)) { 218112f080e7Smrj return (DDI_DMA_BADATTR); 218212f080e7Smrj } 218312f080e7Smrj 218412f080e7Smrj if (attr->dma_attr_addr_hi <= attr->dma_attr_addr_lo) { 218512f080e7Smrj return (DDI_DMA_BADATTR); 218612f080e7Smrj } 218712f080e7Smrj 218812f080e7Smrj if ((attr->dma_attr_seg & MMU_PAGEOFFSET) != MMU_PAGEOFFSET || 218912f080e7Smrj MMU_PAGESIZE & (attr->dma_attr_granular - 1) || 219012f080e7Smrj attr->dma_attr_sgllen <= 0) { 219112f080e7Smrj return (DDI_DMA_BADATTR); 219212f080e7Smrj } 219312f080e7Smrj 219412f080e7Smrj /* We should be able to DMA into every byte offset in a page */ 219512f080e7Smrj if (maxsegmentsize < MMU_PAGESIZE) { 219612f080e7Smrj return (DDI_DMA_BADATTR); 219712f080e7Smrj } 219812f080e7Smrj 219912f080e7Smrj return (DDI_SUCCESS); 220012f080e7Smrj } 220112f080e7Smrj 220212f080e7Smrj 220312f080e7Smrj /* 220412f080e7Smrj * rootnex_valid_bind_parms() 220512f080e7Smrj * Called in ddi_dma_*_bind_handle path to validate its parameters. 220612f080e7Smrj */ 220712f080e7Smrj /* ARGSUSED */ 220812f080e7Smrj static int 220912f080e7Smrj rootnex_valid_bind_parms(ddi_dma_req_t *dmareq, ddi_dma_attr_t *attr) 221012f080e7Smrj { 221112f080e7Smrj #if !defined(__amd64) 221212f080e7Smrj /* 221312f080e7Smrj * we only support up to a 2G-1 transfer size on 32-bit kernels so 221412f080e7Smrj * we can track the offset for the obsoleted interfaces. 221512f080e7Smrj */ 221612f080e7Smrj if (dmareq->dmar_object.dmao_size > 0x7FFFFFFF) { 221712f080e7Smrj return (DDI_DMA_TOOBIG); 221812f080e7Smrj } 221912f080e7Smrj #endif 222012f080e7Smrj 222112f080e7Smrj return (DDI_SUCCESS); 222212f080e7Smrj } 222312f080e7Smrj 222412f080e7Smrj 222512f080e7Smrj /* 222612f080e7Smrj * rootnex_get_sgl() 222712f080e7Smrj * Called in bind fastpath to get the sgl. Most of this will be replaced 222812f080e7Smrj * with a call to the vm layer when vm2.0 comes around... 222912f080e7Smrj */ 223012f080e7Smrj static void 223112f080e7Smrj rootnex_get_sgl(ddi_dma_obj_t *dmar_object, ddi_dma_cookie_t *sgl, 223212f080e7Smrj rootnex_sglinfo_t *sglinfo) 223312f080e7Smrj { 223412f080e7Smrj ddi_dma_atyp_t buftype; 223512f080e7Smrj uint64_t last_page; 223612f080e7Smrj uint64_t offset; 223712f080e7Smrj uint64_t addrhi; 223812f080e7Smrj uint64_t addrlo; 223912f080e7Smrj uint64_t maxseg; 224012f080e7Smrj page_t **pplist; 224112f080e7Smrj uint64_t paddr; 224212f080e7Smrj uint32_t psize; 224312f080e7Smrj uint32_t size; 224412f080e7Smrj caddr_t vaddr; 224512f080e7Smrj uint_t pcnt; 224612f080e7Smrj page_t *pp; 224712f080e7Smrj uint_t cnt; 224812f080e7Smrj 224912f080e7Smrj 225012f080e7Smrj /* shortcuts */ 225112f080e7Smrj pplist = dmar_object->dmao_obj.virt_obj.v_priv; 225212f080e7Smrj vaddr = dmar_object->dmao_obj.virt_obj.v_addr; 225312f080e7Smrj maxseg = sglinfo->si_max_cookie_size; 225412f080e7Smrj buftype = dmar_object->dmao_type; 225512f080e7Smrj addrhi = sglinfo->si_max_addr; 225612f080e7Smrj addrlo = sglinfo->si_min_addr; 225712f080e7Smrj size = dmar_object->dmao_size; 225812f080e7Smrj 225912f080e7Smrj pcnt = 0; 226012f080e7Smrj cnt = 0; 226112f080e7Smrj 226212f080e7Smrj /* 226312f080e7Smrj * if we were passed down a linked list of pages, i.e. pointer to 226412f080e7Smrj * page_t, use this to get our physical address and buf offset. 226512f080e7Smrj */ 226612f080e7Smrj if (buftype == DMA_OTYP_PAGES) { 226712f080e7Smrj pp = dmar_object->dmao_obj.pp_obj.pp_pp; 226812f080e7Smrj ASSERT(!PP_ISFREE(pp) && PAGE_LOCKED(pp)); 226912f080e7Smrj offset = dmar_object->dmao_obj.pp_obj.pp_offset & 227012f080e7Smrj MMU_PAGEOFFSET; 227112f080e7Smrj paddr = ptob64(pp->p_pagenum) + offset; 227212f080e7Smrj psize = MIN(size, (MMU_PAGESIZE - offset)); 227312f080e7Smrj pp = pp->p_next; 227412f080e7Smrj sglinfo->si_asp = NULL; 227512f080e7Smrj 227612f080e7Smrj /* 227712f080e7Smrj * We weren't passed down a linked list of pages, but if we were passed 227812f080e7Smrj * down an array of pages, use this to get our physical address and buf 227912f080e7Smrj * offset. 228012f080e7Smrj */ 228112f080e7Smrj } else if (pplist != NULL) { 228212f080e7Smrj ASSERT((buftype == DMA_OTYP_VADDR) || 228312f080e7Smrj (buftype == DMA_OTYP_BUFVADDR)); 228412f080e7Smrj 228512f080e7Smrj offset = (uintptr_t)vaddr & MMU_PAGEOFFSET; 228612f080e7Smrj sglinfo->si_asp = dmar_object->dmao_obj.virt_obj.v_as; 228712f080e7Smrj if (sglinfo->si_asp == NULL) { 228812f080e7Smrj sglinfo->si_asp = &kas; 228912f080e7Smrj } 229012f080e7Smrj 229112f080e7Smrj ASSERT(!PP_ISFREE(pplist[pcnt])); 229212f080e7Smrj paddr = ptob64(pplist[pcnt]->p_pagenum); 229312f080e7Smrj paddr += offset; 229412f080e7Smrj psize = MIN(size, (MMU_PAGESIZE - offset)); 229512f080e7Smrj pcnt++; 229612f080e7Smrj 229712f080e7Smrj /* 229812f080e7Smrj * All we have is a virtual address, we'll need to call into the VM 229912f080e7Smrj * to get the physical address. 230012f080e7Smrj */ 230112f080e7Smrj } else { 230212f080e7Smrj ASSERT((buftype == DMA_OTYP_VADDR) || 230312f080e7Smrj (buftype == DMA_OTYP_BUFVADDR)); 230412f080e7Smrj 230512f080e7Smrj offset = (uintptr_t)vaddr & MMU_PAGEOFFSET; 230612f080e7Smrj sglinfo->si_asp = dmar_object->dmao_obj.virt_obj.v_as; 230712f080e7Smrj if (sglinfo->si_asp == NULL) { 230812f080e7Smrj sglinfo->si_asp = &kas; 230912f080e7Smrj } 231012f080e7Smrj 231112f080e7Smrj paddr = ptob64(hat_getpfnum(sglinfo->si_asp->a_hat, vaddr)); 231212f080e7Smrj paddr += offset; 231312f080e7Smrj psize = MIN(size, (MMU_PAGESIZE - offset)); 231412f080e7Smrj vaddr += psize; 231512f080e7Smrj } 231612f080e7Smrj 231712f080e7Smrj /* 231812f080e7Smrj * Setup the first cookie with the physical address of the page and the 231912f080e7Smrj * size of the page (which takes into account the initial offset into 232012f080e7Smrj * the page. 232112f080e7Smrj */ 232212f080e7Smrj sgl[cnt].dmac_laddress = paddr; 232312f080e7Smrj sgl[cnt].dmac_size = psize; 232412f080e7Smrj sgl[cnt].dmac_type = 0; 232512f080e7Smrj 232612f080e7Smrj /* 232712f080e7Smrj * Save away the buffer offset into the page. We'll need this later in 232812f080e7Smrj * the copy buffer code to help figure out the page index within the 232912f080e7Smrj * buffer and the offset into the current page. 233012f080e7Smrj */ 233112f080e7Smrj sglinfo->si_buf_offset = offset; 233212f080e7Smrj 233312f080e7Smrj /* 233412f080e7Smrj * If the DMA engine can't reach the physical address, increase how 233512f080e7Smrj * much copy buffer we need. We always increase by pagesize so we don't 233612f080e7Smrj * have to worry about converting offsets. Set a flag in the cookies 233712f080e7Smrj * dmac_type to indicate that it uses the copy buffer. If this isn't the 233812f080e7Smrj * last cookie, go to the next cookie (since we separate each page which 233912f080e7Smrj * uses the copy buffer in case the copy buffer is not physically 234012f080e7Smrj * contiguous. 234112f080e7Smrj */ 234212f080e7Smrj if ((paddr < addrlo) || ((paddr + psize) > addrhi)) { 234312f080e7Smrj sglinfo->si_copybuf_req += MMU_PAGESIZE; 234412f080e7Smrj sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF; 234512f080e7Smrj if ((cnt + 1) < sglinfo->si_max_pages) { 234612f080e7Smrj cnt++; 234712f080e7Smrj sgl[cnt].dmac_laddress = 0; 234812f080e7Smrj sgl[cnt].dmac_size = 0; 234912f080e7Smrj sgl[cnt].dmac_type = 0; 235012f080e7Smrj } 235112f080e7Smrj } 235212f080e7Smrj 235312f080e7Smrj /* 235412f080e7Smrj * save this page's physical address so we can figure out if the next 235512f080e7Smrj * page is physically contiguous. Keep decrementing size until we are 235612f080e7Smrj * done with the buffer. 235712f080e7Smrj */ 235812f080e7Smrj last_page = paddr & MMU_PAGEMASK; 235912f080e7Smrj size -= psize; 236012f080e7Smrj 236112f080e7Smrj while (size > 0) { 236212f080e7Smrj /* Get the size for this page (i.e. partial or full page) */ 236312f080e7Smrj psize = MIN(size, MMU_PAGESIZE); 236412f080e7Smrj 236512f080e7Smrj if (buftype == DMA_OTYP_PAGES) { 236612f080e7Smrj /* get the paddr from the page_t */ 236712f080e7Smrj ASSERT(!PP_ISFREE(pp) && PAGE_LOCKED(pp)); 236812f080e7Smrj paddr = ptob64(pp->p_pagenum); 236912f080e7Smrj pp = pp->p_next; 237012f080e7Smrj } else if (pplist != NULL) { 237112f080e7Smrj /* index into the array of page_t's to get the paddr */ 237212f080e7Smrj ASSERT(!PP_ISFREE(pplist[pcnt])); 237312f080e7Smrj paddr = ptob64(pplist[pcnt]->p_pagenum); 237412f080e7Smrj pcnt++; 237512f080e7Smrj } else { 237612f080e7Smrj /* call into the VM to get the paddr */ 237712f080e7Smrj paddr = ptob64(hat_getpfnum(sglinfo->si_asp->a_hat, 237812f080e7Smrj vaddr)); 237912f080e7Smrj vaddr += psize; 238012f080e7Smrj } 238112f080e7Smrj 238212f080e7Smrj /* check to see if this page needs the copy buffer */ 238312f080e7Smrj if ((paddr < addrlo) || ((paddr + psize) > addrhi)) { 238412f080e7Smrj sglinfo->si_copybuf_req += MMU_PAGESIZE; 238512f080e7Smrj 238612f080e7Smrj /* 238712f080e7Smrj * if there is something in the current cookie, go to 238812f080e7Smrj * the next one. We only want one page in a cookie which 238912f080e7Smrj * uses the copybuf since the copybuf doesn't have to 239012f080e7Smrj * be physically contiguous. 239112f080e7Smrj */ 239212f080e7Smrj if (sgl[cnt].dmac_size != 0) { 239312f080e7Smrj cnt++; 239412f080e7Smrj } 239512f080e7Smrj sgl[cnt].dmac_laddress = paddr; 239612f080e7Smrj sgl[cnt].dmac_size = psize; 239712f080e7Smrj #if defined(__amd64) 239812f080e7Smrj sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF; 239912f080e7Smrj #else 240012f080e7Smrj /* 240112f080e7Smrj * save the buf offset for 32-bit kernel. used in the 240212f080e7Smrj * obsoleted interfaces. 240312f080e7Smrj */ 240412f080e7Smrj sgl[cnt].dmac_type = ROOTNEX_USES_COPYBUF | 240512f080e7Smrj (dmar_object->dmao_size - size); 240612f080e7Smrj #endif 240712f080e7Smrj /* if this isn't the last cookie, go to the next one */ 240812f080e7Smrj if ((cnt + 1) < sglinfo->si_max_pages) { 240912f080e7Smrj cnt++; 241012f080e7Smrj sgl[cnt].dmac_laddress = 0; 241112f080e7Smrj sgl[cnt].dmac_size = 0; 241212f080e7Smrj sgl[cnt].dmac_type = 0; 241312f080e7Smrj } 241412f080e7Smrj 241512f080e7Smrj /* 241612f080e7Smrj * this page didn't need the copy buffer, if it's not physically 241712f080e7Smrj * contiguous, or it would put us over a segment boundary, or it 241812f080e7Smrj * puts us over the max cookie size, or the current sgl doesn't 241912f080e7Smrj * have anything in it. 242012f080e7Smrj */ 242112f080e7Smrj } else if (((last_page + MMU_PAGESIZE) != paddr) || 242212f080e7Smrj !(paddr & sglinfo->si_segmask) || 242312f080e7Smrj ((sgl[cnt].dmac_size + psize) > maxseg) || 242412f080e7Smrj (sgl[cnt].dmac_size == 0)) { 242512f080e7Smrj /* 242612f080e7Smrj * if we're not already in a new cookie, go to the next 242712f080e7Smrj * cookie. 242812f080e7Smrj */ 242912f080e7Smrj if (sgl[cnt].dmac_size != 0) { 243012f080e7Smrj cnt++; 243112f080e7Smrj } 243212f080e7Smrj 243312f080e7Smrj /* save the cookie information */ 243412f080e7Smrj sgl[cnt].dmac_laddress = paddr; 243512f080e7Smrj sgl[cnt].dmac_size = psize; 243612f080e7Smrj #if defined(__amd64) 243712f080e7Smrj sgl[cnt].dmac_type = 0; 243812f080e7Smrj #else 243912f080e7Smrj /* 244012f080e7Smrj * save the buf offset for 32-bit kernel. used in the 244112f080e7Smrj * obsoleted interfaces. 244212f080e7Smrj */ 244312f080e7Smrj sgl[cnt].dmac_type = dmar_object->dmao_size - size; 244412f080e7Smrj #endif 244512f080e7Smrj 244612f080e7Smrj /* 244712f080e7Smrj * this page didn't need the copy buffer, it is physically 244812f080e7Smrj * contiguous with the last page, and it's <= the max cookie 244912f080e7Smrj * size. 245012f080e7Smrj */ 245112f080e7Smrj } else { 245212f080e7Smrj sgl[cnt].dmac_size += psize; 245312f080e7Smrj 245412f080e7Smrj /* 245512f080e7Smrj * if this exactly == the maximum cookie size, and 245612f080e7Smrj * it isn't the last cookie, go to the next cookie. 245712f080e7Smrj */ 245812f080e7Smrj if (((sgl[cnt].dmac_size + psize) == maxseg) && 245912f080e7Smrj ((cnt + 1) < sglinfo->si_max_pages)) { 246012f080e7Smrj cnt++; 246112f080e7Smrj sgl[cnt].dmac_laddress = 0; 246212f080e7Smrj sgl[cnt].dmac_size = 0; 246312f080e7Smrj sgl[cnt].dmac_type = 0; 246412f080e7Smrj } 246512f080e7Smrj } 246612f080e7Smrj 246712f080e7Smrj /* 246812f080e7Smrj * save this page's physical address so we can figure out if the 246912f080e7Smrj * next page is physically contiguous. Keep decrementing size 247012f080e7Smrj * until we are done with the buffer. 247112f080e7Smrj */ 247212f080e7Smrj last_page = paddr; 247312f080e7Smrj size -= psize; 247412f080e7Smrj } 247512f080e7Smrj 247612f080e7Smrj /* we're done, save away how many cookies the sgl has */ 247712f080e7Smrj if (sgl[cnt].dmac_size == 0) { 247812f080e7Smrj ASSERT(cnt < sglinfo->si_max_pages); 247912f080e7Smrj sglinfo->si_sgl_size = cnt; 248012f080e7Smrj } else { 248112f080e7Smrj sglinfo->si_sgl_size = cnt + 1; 248212f080e7Smrj } 248312f080e7Smrj } 248412f080e7Smrj 248512f080e7Smrj 248612f080e7Smrj /* 248712f080e7Smrj * rootnex_bind_slowpath() 248812f080e7Smrj * Call in the bind path if the calling driver can't use the sgl without 248912f080e7Smrj * modifying it. We either need to use the copy buffer and/or we will end up 249012f080e7Smrj * with a partial bind. 249112f080e7Smrj */ 249212f080e7Smrj static int 249312f080e7Smrj rootnex_bind_slowpath(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq, 249412f080e7Smrj rootnex_dma_t *dma, ddi_dma_attr_t *attr, int kmflag) 249512f080e7Smrj { 249612f080e7Smrj rootnex_sglinfo_t *sinfo; 249712f080e7Smrj rootnex_window_t *window; 249812f080e7Smrj ddi_dma_cookie_t *cookie; 249912f080e7Smrj size_t copybuf_used; 250012f080e7Smrj size_t dmac_size; 250112f080e7Smrj boolean_t partial; 250212f080e7Smrj off_t cur_offset; 250312f080e7Smrj page_t *cur_pp; 250412f080e7Smrj major_t mnum; 250512f080e7Smrj int e; 250612f080e7Smrj int i; 250712f080e7Smrj 250812f080e7Smrj 250912f080e7Smrj sinfo = &dma->dp_sglinfo; 251012f080e7Smrj copybuf_used = 0; 251112f080e7Smrj partial = B_FALSE; 251212f080e7Smrj 251312f080e7Smrj /* 251412f080e7Smrj * If we're using the copybuf, set the copybuf state in dma struct. 251512f080e7Smrj * Needs to be first since it sets the copy buffer size. 251612f080e7Smrj */ 251712f080e7Smrj if (sinfo->si_copybuf_req != 0) { 251812f080e7Smrj e = rootnex_setup_copybuf(hp, dmareq, dma, attr); 251912f080e7Smrj if (e != DDI_SUCCESS) { 252012f080e7Smrj return (e); 252112f080e7Smrj } 252212f080e7Smrj } else { 252312f080e7Smrj dma->dp_copybuf_size = 0; 252412f080e7Smrj } 252512f080e7Smrj 252612f080e7Smrj /* 252712f080e7Smrj * Figure out if we need to do a partial mapping. If so, figure out 252812f080e7Smrj * if we need to trim the buffers when we munge the sgl. 252912f080e7Smrj */ 253012f080e7Smrj if ((dma->dp_copybuf_size < sinfo->si_copybuf_req) || 253112f080e7Smrj (dma->dp_dma.dmao_size > dma->dp_maxxfer) || 253212f080e7Smrj (attr->dma_attr_sgllen < sinfo->si_sgl_size)) { 253312f080e7Smrj dma->dp_partial_required = B_TRUE; 253412f080e7Smrj if (attr->dma_attr_granular != 1) { 253512f080e7Smrj dma->dp_trim_required = B_TRUE; 253612f080e7Smrj } 253712f080e7Smrj } else { 253812f080e7Smrj dma->dp_partial_required = B_FALSE; 253912f080e7Smrj dma->dp_trim_required = B_FALSE; 254012f080e7Smrj } 254112f080e7Smrj 254212f080e7Smrj /* If we need to do a partial bind, make sure the driver supports it */ 254312f080e7Smrj if (dma->dp_partial_required && 254412f080e7Smrj !(dmareq->dmar_flags & DDI_DMA_PARTIAL)) { 254512f080e7Smrj 254612f080e7Smrj mnum = ddi_driver_major(dma->dp_dip); 254712f080e7Smrj /* 254812f080e7Smrj * patchable which allows us to print one warning per major 254912f080e7Smrj * number. 255012f080e7Smrj */ 255112f080e7Smrj if ((rootnex_bind_warn) && 255212f080e7Smrj ((rootnex_warn_list[mnum] & ROOTNEX_BIND_WARNING) == 0)) { 255312f080e7Smrj rootnex_warn_list[mnum] |= ROOTNEX_BIND_WARNING; 255412f080e7Smrj cmn_err(CE_WARN, "!%s: coding error detected, the " 255512f080e7Smrj "driver is using ddi_dma_attr(9S) incorrectly. " 255612f080e7Smrj "There is a small risk of data corruption in " 255712f080e7Smrj "particular with large I/Os. The driver should be " 255812f080e7Smrj "replaced with a corrected version for proper " 255912f080e7Smrj "system operation. To disable this warning, add " 256012f080e7Smrj "'set rootnex:rootnex_bind_warn=0' to " 256112f080e7Smrj "/etc/system(4).", ddi_driver_name(dma->dp_dip)); 256212f080e7Smrj } 256312f080e7Smrj return (DDI_DMA_TOOBIG); 256412f080e7Smrj } 256512f080e7Smrj 256612f080e7Smrj /* 256712f080e7Smrj * we might need multiple windows, setup state to handle them. In this 256812f080e7Smrj * code path, we will have at least one window. 256912f080e7Smrj */ 257012f080e7Smrj e = rootnex_setup_windows(hp, dma, attr, kmflag); 257112f080e7Smrj if (e != DDI_SUCCESS) { 257212f080e7Smrj rootnex_teardown_copybuf(dma); 257312f080e7Smrj return (e); 257412f080e7Smrj } 257512f080e7Smrj 257612f080e7Smrj window = &dma->dp_window[0]; 257712f080e7Smrj cookie = &dma->dp_cookies[0]; 257812f080e7Smrj cur_offset = 0; 257912f080e7Smrj rootnex_init_win(hp, dma, window, cookie, cur_offset); 258012f080e7Smrj if (dmareq->dmar_object.dmao_type == DMA_OTYP_PAGES) { 258112f080e7Smrj cur_pp = dmareq->dmar_object.dmao_obj.pp_obj.pp_pp; 258212f080e7Smrj } 258312f080e7Smrj 258412f080e7Smrj /* loop though all the cookies we got back from get_sgl() */ 258512f080e7Smrj for (i = 0; i < sinfo->si_sgl_size; i++) { 258612f080e7Smrj /* 258712f080e7Smrj * If we're using the copy buffer, check this cookie and setup 258812f080e7Smrj * its associated copy buffer state. If this cookie uses the 258912f080e7Smrj * copy buffer, make sure we sync this window during dma_sync. 259012f080e7Smrj */ 259112f080e7Smrj if (dma->dp_copybuf_size > 0) { 259212f080e7Smrj rootnex_setup_cookie(&dmareq->dmar_object, dma, cookie, 259312f080e7Smrj cur_offset, ©buf_used, &cur_pp); 259412f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 259512f080e7Smrj window->wd_dosync = B_TRUE; 259612f080e7Smrj } 259712f080e7Smrj } 259812f080e7Smrj 259912f080e7Smrj /* 260012f080e7Smrj * save away the cookie size, since it could be modified in 260112f080e7Smrj * the windowing code. 260212f080e7Smrj */ 260312f080e7Smrj dmac_size = cookie->dmac_size; 260412f080e7Smrj 260512f080e7Smrj /* if we went over max copybuf size */ 260612f080e7Smrj if (dma->dp_copybuf_size && 260712f080e7Smrj (copybuf_used > dma->dp_copybuf_size)) { 260812f080e7Smrj partial = B_TRUE; 260912f080e7Smrj e = rootnex_copybuf_window_boundary(hp, dma, &window, 261012f080e7Smrj cookie, cur_offset, ©buf_used); 261112f080e7Smrj if (e != DDI_SUCCESS) { 261212f080e7Smrj rootnex_teardown_copybuf(dma); 261312f080e7Smrj rootnex_teardown_windows(dma); 261412f080e7Smrj return (e); 261512f080e7Smrj } 261612f080e7Smrj 261712f080e7Smrj /* 261812f080e7Smrj * if the coookie uses the copy buffer, make sure the 261912f080e7Smrj * new window we just moved to is set to sync. 262012f080e7Smrj */ 262112f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 262212f080e7Smrj window->wd_dosync = B_TRUE; 262312f080e7Smrj } 262412f080e7Smrj DTRACE_PROBE1(rootnex__copybuf__window, dev_info_t *, 262512f080e7Smrj dma->dp_dip); 262612f080e7Smrj 262712f080e7Smrj /* if the cookie cnt == max sgllen, move to the next window */ 262812f080e7Smrj } else if (window->wd_cookie_cnt >= attr->dma_attr_sgllen) { 262912f080e7Smrj partial = B_TRUE; 263012f080e7Smrj ASSERT(window->wd_cookie_cnt == attr->dma_attr_sgllen); 263112f080e7Smrj e = rootnex_sgllen_window_boundary(hp, dma, &window, 263212f080e7Smrj cookie, attr, cur_offset); 263312f080e7Smrj if (e != DDI_SUCCESS) { 263412f080e7Smrj rootnex_teardown_copybuf(dma); 263512f080e7Smrj rootnex_teardown_windows(dma); 263612f080e7Smrj return (e); 263712f080e7Smrj } 263812f080e7Smrj 263912f080e7Smrj /* 264012f080e7Smrj * if the coookie uses the copy buffer, make sure the 264112f080e7Smrj * new window we just moved to is set to sync. 264212f080e7Smrj */ 264312f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 264412f080e7Smrj window->wd_dosync = B_TRUE; 264512f080e7Smrj } 264612f080e7Smrj DTRACE_PROBE1(rootnex__sgllen__window, dev_info_t *, 264712f080e7Smrj dma->dp_dip); 264812f080e7Smrj 264912f080e7Smrj /* else if we will be over maxxfer */ 265012f080e7Smrj } else if ((window->wd_size + dmac_size) > 265112f080e7Smrj dma->dp_maxxfer) { 265212f080e7Smrj partial = B_TRUE; 265312f080e7Smrj e = rootnex_maxxfer_window_boundary(hp, dma, &window, 265412f080e7Smrj cookie); 265512f080e7Smrj if (e != DDI_SUCCESS) { 265612f080e7Smrj rootnex_teardown_copybuf(dma); 265712f080e7Smrj rootnex_teardown_windows(dma); 265812f080e7Smrj return (e); 265912f080e7Smrj } 266012f080e7Smrj 266112f080e7Smrj /* 266212f080e7Smrj * if the coookie uses the copy buffer, make sure the 266312f080e7Smrj * new window we just moved to is set to sync. 266412f080e7Smrj */ 266512f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 266612f080e7Smrj window->wd_dosync = B_TRUE; 266712f080e7Smrj } 266812f080e7Smrj DTRACE_PROBE1(rootnex__maxxfer__window, dev_info_t *, 266912f080e7Smrj dma->dp_dip); 267012f080e7Smrj 267112f080e7Smrj /* else this cookie fits in the current window */ 267212f080e7Smrj } else { 267312f080e7Smrj window->wd_cookie_cnt++; 267412f080e7Smrj window->wd_size += dmac_size; 267512f080e7Smrj } 267612f080e7Smrj 267712f080e7Smrj /* track our offset into the buffer, go to the next cookie */ 267812f080e7Smrj ASSERT(dmac_size <= dma->dp_dma.dmao_size); 267912f080e7Smrj ASSERT(cookie->dmac_size <= dmac_size); 268012f080e7Smrj cur_offset += dmac_size; 268112f080e7Smrj cookie++; 268212f080e7Smrj } 268312f080e7Smrj 268412f080e7Smrj /* if we ended up with a zero sized window in the end, clean it up */ 268512f080e7Smrj if (window->wd_size == 0) { 268612f080e7Smrj hp->dmai_nwin--; 268712f080e7Smrj window--; 268812f080e7Smrj } 268912f080e7Smrj 269012f080e7Smrj ASSERT(window->wd_trim.tr_trim_last == B_FALSE); 269112f080e7Smrj 269212f080e7Smrj if (!partial) { 269312f080e7Smrj return (DDI_DMA_MAPPED); 269412f080e7Smrj } 269512f080e7Smrj 269612f080e7Smrj ASSERT(dma->dp_partial_required); 269712f080e7Smrj return (DDI_DMA_PARTIAL_MAP); 269812f080e7Smrj } 269912f080e7Smrj 270012f080e7Smrj 270112f080e7Smrj /* 270212f080e7Smrj * rootnex_setup_copybuf() 270312f080e7Smrj * Called in bind slowpath. Figures out if we're going to use the copy 270412f080e7Smrj * buffer, and if we do, sets up the basic state to handle it. 270512f080e7Smrj */ 270612f080e7Smrj static int 270712f080e7Smrj rootnex_setup_copybuf(ddi_dma_impl_t *hp, struct ddi_dma_req *dmareq, 270812f080e7Smrj rootnex_dma_t *dma, ddi_dma_attr_t *attr) 270912f080e7Smrj { 271012f080e7Smrj rootnex_sglinfo_t *sinfo; 271112f080e7Smrj ddi_dma_attr_t lattr; 271212f080e7Smrj size_t max_copybuf; 271312f080e7Smrj int cansleep; 271412f080e7Smrj int e; 271512f080e7Smrj #if !defined(__amd64) 271612f080e7Smrj int vmflag; 271712f080e7Smrj #endif 271812f080e7Smrj 271912f080e7Smrj 272012f080e7Smrj sinfo = &dma->dp_sglinfo; 272112f080e7Smrj 272212f080e7Smrj /* 272312f080e7Smrj * read this first so it's consistent through the routine so we can 272412f080e7Smrj * patch it on the fly. 272512f080e7Smrj */ 272612f080e7Smrj max_copybuf = rootnex_max_copybuf_size & MMU_PAGEMASK; 272712f080e7Smrj 272812f080e7Smrj /* We need to call into the rootnex on ddi_dma_sync() */ 272912f080e7Smrj hp->dmai_rflags &= ~DMP_NOSYNC; 273012f080e7Smrj 273112f080e7Smrj /* make sure the copybuf size <= the max size */ 273212f080e7Smrj dma->dp_copybuf_size = MIN(sinfo->si_copybuf_req, max_copybuf); 273312f080e7Smrj ASSERT((dma->dp_copybuf_size & MMU_PAGEOFFSET) == 0); 273412f080e7Smrj 273512f080e7Smrj #if !defined(__amd64) 273612f080e7Smrj /* 273712f080e7Smrj * if we don't have kva space to copy to/from, allocate the KVA space 273812f080e7Smrj * now. We only do this for the 32-bit kernel. We use seg kpm space for 273912f080e7Smrj * the 64-bit kernel. 274012f080e7Smrj */ 274112f080e7Smrj if ((dmareq->dmar_object.dmao_type == DMA_OTYP_PAGES) || 274212f080e7Smrj (dmareq->dmar_object.dmao_obj.virt_obj.v_as != NULL)) { 274312f080e7Smrj 274412f080e7Smrj /* convert the sleep flags */ 274512f080e7Smrj if (dmareq->dmar_fp == DDI_DMA_SLEEP) { 274612f080e7Smrj vmflag = VM_SLEEP; 274712f080e7Smrj } else { 274812f080e7Smrj vmflag = VM_NOSLEEP; 274912f080e7Smrj } 275012f080e7Smrj 275112f080e7Smrj /* allocate Kernel VA space that we can bcopy to/from */ 275212f080e7Smrj dma->dp_kva = vmem_alloc(heap_arena, dma->dp_copybuf_size, 275312f080e7Smrj vmflag); 275412f080e7Smrj if (dma->dp_kva == NULL) { 275512f080e7Smrj return (DDI_DMA_NORESOURCES); 275612f080e7Smrj } 275712f080e7Smrj } 275812f080e7Smrj #endif 275912f080e7Smrj 276012f080e7Smrj /* convert the sleep flags */ 276112f080e7Smrj if (dmareq->dmar_fp == DDI_DMA_SLEEP) { 276212f080e7Smrj cansleep = 1; 276312f080e7Smrj } else { 276412f080e7Smrj cansleep = 0; 276512f080e7Smrj } 276612f080e7Smrj 276712f080e7Smrj /* 276812f080e7Smrj * Allocated the actual copy buffer. This needs to fit within the DMA 276912f080e7Smrj * engines limits, so we can't use kmem_alloc... 277012f080e7Smrj */ 277112f080e7Smrj lattr = *attr; 277212f080e7Smrj lattr.dma_attr_align = MMU_PAGESIZE; 277312f080e7Smrj e = i_ddi_mem_alloc(dma->dp_dip, &lattr, dma->dp_copybuf_size, cansleep, 277412f080e7Smrj 0, NULL, &dma->dp_cbaddr, &dma->dp_cbsize, NULL); 277512f080e7Smrj if (e != DDI_SUCCESS) { 277612f080e7Smrj #if !defined(__amd64) 277712f080e7Smrj if (dma->dp_kva != NULL) { 277812f080e7Smrj vmem_free(heap_arena, dma->dp_kva, 277912f080e7Smrj dma->dp_copybuf_size); 278012f080e7Smrj } 278112f080e7Smrj #endif 278212f080e7Smrj return (DDI_DMA_NORESOURCES); 278312f080e7Smrj } 278412f080e7Smrj 278512f080e7Smrj DTRACE_PROBE2(rootnex__alloc__copybuf, dev_info_t *, dma->dp_dip, 278612f080e7Smrj size_t, dma->dp_copybuf_size); 278712f080e7Smrj 278812f080e7Smrj return (DDI_SUCCESS); 278912f080e7Smrj } 279012f080e7Smrj 279112f080e7Smrj 279212f080e7Smrj /* 279312f080e7Smrj * rootnex_setup_windows() 279412f080e7Smrj * Called in bind slowpath to setup the window state. We always have windows 279512f080e7Smrj * in the slowpath. Even if the window count = 1. 279612f080e7Smrj */ 279712f080e7Smrj static int 279812f080e7Smrj rootnex_setup_windows(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 279912f080e7Smrj ddi_dma_attr_t *attr, int kmflag) 280012f080e7Smrj { 280112f080e7Smrj rootnex_window_t *windowp; 280212f080e7Smrj rootnex_sglinfo_t *sinfo; 280312f080e7Smrj size_t copy_state_size; 280412f080e7Smrj size_t win_state_size; 280512f080e7Smrj size_t state_available; 280612f080e7Smrj size_t space_needed; 280712f080e7Smrj uint_t copybuf_win; 280812f080e7Smrj uint_t maxxfer_win; 280912f080e7Smrj size_t space_used; 281012f080e7Smrj uint_t sglwin; 281112f080e7Smrj 281212f080e7Smrj 281312f080e7Smrj sinfo = &dma->dp_sglinfo; 281412f080e7Smrj 281512f080e7Smrj dma->dp_current_win = 0; 281612f080e7Smrj hp->dmai_nwin = 0; 281712f080e7Smrj 281812f080e7Smrj /* If we don't need to do a partial, we only have one window */ 281912f080e7Smrj if (!dma->dp_partial_required) { 282012f080e7Smrj dma->dp_max_win = 1; 282112f080e7Smrj 282212f080e7Smrj /* 282312f080e7Smrj * we need multiple windows, need to figure out the worse case number 282412f080e7Smrj * of windows. 282512f080e7Smrj */ 28267c478bd9Sstevel@tonic-gate } else { 28277c478bd9Sstevel@tonic-gate /* 282812f080e7Smrj * if we need windows because we need more copy buffer that 282912f080e7Smrj * we allow, the worse case number of windows we could need 283012f080e7Smrj * here would be (copybuf space required / copybuf space that 283112f080e7Smrj * we have) plus one for remainder, and plus 2 to handle the 283212f080e7Smrj * extra pages on the trim for the first and last pages of the 283312f080e7Smrj * buffer (a page is the minimum window size so under the right 283412f080e7Smrj * attr settings, you could have a window for each page). 283512f080e7Smrj * The last page will only be hit here if the size is not a 283612f080e7Smrj * multiple of the granularity (which theoretically shouldn't 283712f080e7Smrj * be the case but never has been enforced, so we could have 283812f080e7Smrj * broken things without it). 28397c478bd9Sstevel@tonic-gate */ 284012f080e7Smrj if (sinfo->si_copybuf_req > dma->dp_copybuf_size) { 284112f080e7Smrj ASSERT(dma->dp_copybuf_size > 0); 284212f080e7Smrj copybuf_win = (sinfo->si_copybuf_req / 284312f080e7Smrj dma->dp_copybuf_size) + 1 + 2; 28447c478bd9Sstevel@tonic-gate } else { 284512f080e7Smrj copybuf_win = 0; 28467c478bd9Sstevel@tonic-gate } 284712f080e7Smrj 284812f080e7Smrj /* 284912f080e7Smrj * if we need windows because we have more cookies than the H/W 285012f080e7Smrj * can handle, the number of windows we would need here would 285112f080e7Smrj * be (cookie count / cookies count H/W supports) plus one for 285212f080e7Smrj * remainder, and plus 2 to handle the extra pages on the trim 285312f080e7Smrj * (see above comment about trim) 285412f080e7Smrj */ 285512f080e7Smrj if (attr->dma_attr_sgllen < sinfo->si_sgl_size) { 285612f080e7Smrj sglwin = ((sinfo->si_sgl_size / attr->dma_attr_sgllen) 285712f080e7Smrj + 1) + 2; 28587c478bd9Sstevel@tonic-gate } else { 285912f080e7Smrj sglwin = 0; 28607c478bd9Sstevel@tonic-gate } 286112f080e7Smrj 286212f080e7Smrj /* 286312f080e7Smrj * if we need windows because we're binding more memory than the 286412f080e7Smrj * H/W can transfer at once, the number of windows we would need 286512f080e7Smrj * here would be (xfer count / max xfer H/W supports) plus one 286612f080e7Smrj * for remainder, and plus 2 to handle the extra pages on the 286712f080e7Smrj * trim (see above comment about trim) 286812f080e7Smrj */ 286912f080e7Smrj if (dma->dp_dma.dmao_size > dma->dp_maxxfer) { 287012f080e7Smrj maxxfer_win = (dma->dp_dma.dmao_size / 287112f080e7Smrj dma->dp_maxxfer) + 1 + 2; 287212f080e7Smrj } else { 287312f080e7Smrj maxxfer_win = 0; 28747c478bd9Sstevel@tonic-gate } 287512f080e7Smrj dma->dp_max_win = copybuf_win + sglwin + maxxfer_win; 287612f080e7Smrj ASSERT(dma->dp_max_win > 0); 287712f080e7Smrj } 287812f080e7Smrj win_state_size = dma->dp_max_win * sizeof (rootnex_window_t); 287912f080e7Smrj 288012f080e7Smrj /* 288112f080e7Smrj * Get space for window and potential copy buffer state. Before we 288212f080e7Smrj * go and allocate memory, see if we can get away with using what's 288312f080e7Smrj * left in the pre-allocted state or the dynamically allocated sgl. 288412f080e7Smrj */ 288512f080e7Smrj space_used = (uintptr_t)(sinfo->si_sgl_size * 288612f080e7Smrj sizeof (ddi_dma_cookie_t)); 288712f080e7Smrj 288812f080e7Smrj /* if we dynamically allocated space for the cookies */ 288912f080e7Smrj if (dma->dp_need_to_free_cookie) { 289012f080e7Smrj /* if we have more space in the pre-allocted buffer, use it */ 289112f080e7Smrj ASSERT(space_used <= dma->dp_cookie_size); 289212f080e7Smrj if ((dma->dp_cookie_size - space_used) <= 289312f080e7Smrj rootnex_state->r_prealloc_size) { 289412f080e7Smrj state_available = rootnex_state->r_prealloc_size; 289512f080e7Smrj windowp = (rootnex_window_t *)dma->dp_prealloc_buffer; 289612f080e7Smrj 289712f080e7Smrj /* 289812f080e7Smrj * else, we have more free space in the dynamically allocated 289912f080e7Smrj * buffer, i.e. the buffer wasn't worse case fragmented so we 290012f080e7Smrj * didn't need a lot of cookies. 290112f080e7Smrj */ 290212f080e7Smrj } else { 290312f080e7Smrj state_available = dma->dp_cookie_size - space_used; 290412f080e7Smrj windowp = (rootnex_window_t *) 290512f080e7Smrj &dma->dp_cookies[sinfo->si_sgl_size]; 290612f080e7Smrj } 290712f080e7Smrj 290812f080e7Smrj /* we used the pre-alloced buffer */ 290912f080e7Smrj } else { 291012f080e7Smrj ASSERT(space_used <= rootnex_state->r_prealloc_size); 291112f080e7Smrj state_available = rootnex_state->r_prealloc_size - space_used; 291212f080e7Smrj windowp = (rootnex_window_t *) 291312f080e7Smrj &dma->dp_cookies[sinfo->si_sgl_size]; 291412f080e7Smrj } 291512f080e7Smrj 291612f080e7Smrj /* 291712f080e7Smrj * figure out how much state we need to track the copy buffer. Add an 291812f080e7Smrj * addition 8 bytes for pointer alignemnt later. 291912f080e7Smrj */ 292012f080e7Smrj if (dma->dp_copybuf_size > 0) { 292112f080e7Smrj copy_state_size = sinfo->si_max_pages * 292212f080e7Smrj sizeof (rootnex_pgmap_t); 292312f080e7Smrj } else { 292412f080e7Smrj copy_state_size = 0; 292512f080e7Smrj } 292612f080e7Smrj /* add an additional 8 bytes for pointer alignment */ 292712f080e7Smrj space_needed = win_state_size + copy_state_size + 0x8; 292812f080e7Smrj 292912f080e7Smrj /* if we have enough space already, use it */ 293012f080e7Smrj if (state_available >= space_needed) { 293112f080e7Smrj dma->dp_window = windowp; 293212f080e7Smrj dma->dp_need_to_free_window = B_FALSE; 293312f080e7Smrj 293412f080e7Smrj /* not enough space, need to allocate more. */ 293512f080e7Smrj } else { 293612f080e7Smrj dma->dp_window = kmem_alloc(space_needed, kmflag); 293712f080e7Smrj if (dma->dp_window == NULL) { 293812f080e7Smrj return (DDI_DMA_NORESOURCES); 293912f080e7Smrj } 294012f080e7Smrj dma->dp_need_to_free_window = B_TRUE; 294112f080e7Smrj dma->dp_window_size = space_needed; 294212f080e7Smrj DTRACE_PROBE2(rootnex__bind__sp__alloc, dev_info_t *, 294312f080e7Smrj dma->dp_dip, size_t, space_needed); 294412f080e7Smrj } 294512f080e7Smrj 294612f080e7Smrj /* 294712f080e7Smrj * we allocate copy buffer state and window state at the same time. 294812f080e7Smrj * setup our copy buffer state pointers. Make sure it's aligned. 294912f080e7Smrj */ 295012f080e7Smrj if (dma->dp_copybuf_size > 0) { 295112f080e7Smrj dma->dp_pgmap = (rootnex_pgmap_t *)(((uintptr_t) 295212f080e7Smrj &dma->dp_window[dma->dp_max_win] + 0x7) & ~0x7); 295312f080e7Smrj 295412f080e7Smrj #if !defined(__amd64) 295512f080e7Smrj /* 295612f080e7Smrj * make sure all pm_mapped, pm_vaddr, and pm_pp are set to 295712f080e7Smrj * false/NULL. Should be quicker to bzero vs loop and set. 295812f080e7Smrj */ 295912f080e7Smrj bzero(dma->dp_pgmap, copy_state_size); 296012f080e7Smrj #endif 296112f080e7Smrj } else { 296212f080e7Smrj dma->dp_pgmap = NULL; 296312f080e7Smrj } 296412f080e7Smrj 296512f080e7Smrj return (DDI_SUCCESS); 296612f080e7Smrj } 296712f080e7Smrj 296812f080e7Smrj 296912f080e7Smrj /* 297012f080e7Smrj * rootnex_teardown_copybuf() 297112f080e7Smrj * cleans up after rootnex_setup_copybuf() 297212f080e7Smrj */ 297312f080e7Smrj static void 297412f080e7Smrj rootnex_teardown_copybuf(rootnex_dma_t *dma) 297512f080e7Smrj { 297612f080e7Smrj #if !defined(__amd64) 297712f080e7Smrj int i; 297812f080e7Smrj 297912f080e7Smrj /* 298012f080e7Smrj * if we allocated kernel heap VMEM space, go through all the pages and 298112f080e7Smrj * map out any of the ones that we're mapped into the kernel heap VMEM 298212f080e7Smrj * arena. Then free the VMEM space. 298312f080e7Smrj */ 298412f080e7Smrj if (dma->dp_kva != NULL) { 298512f080e7Smrj for (i = 0; i < dma->dp_sglinfo.si_max_pages; i++) { 298612f080e7Smrj if (dma->dp_pgmap[i].pm_mapped) { 298712f080e7Smrj hat_unload(kas.a_hat, dma->dp_pgmap[i].pm_kaddr, 298812f080e7Smrj MMU_PAGESIZE, HAT_UNLOAD); 298912f080e7Smrj dma->dp_pgmap[i].pm_mapped = B_FALSE; 299012f080e7Smrj } 299112f080e7Smrj } 299212f080e7Smrj 299312f080e7Smrj vmem_free(heap_arena, dma->dp_kva, dma->dp_copybuf_size); 299412f080e7Smrj } 299512f080e7Smrj 299612f080e7Smrj #endif 299712f080e7Smrj 299812f080e7Smrj /* if we allocated a copy buffer, free it */ 299912f080e7Smrj if (dma->dp_cbaddr != NULL) { 300012f080e7Smrj i_ddi_mem_free(dma->dp_cbaddr, 0); 300112f080e7Smrj } 300212f080e7Smrj } 300312f080e7Smrj 300412f080e7Smrj 300512f080e7Smrj /* 300612f080e7Smrj * rootnex_teardown_windows() 300712f080e7Smrj * cleans up after rootnex_setup_windows() 300812f080e7Smrj */ 300912f080e7Smrj static void 301012f080e7Smrj rootnex_teardown_windows(rootnex_dma_t *dma) 301112f080e7Smrj { 301212f080e7Smrj /* 301312f080e7Smrj * if we had to allocate window state on the last bind (because we 301412f080e7Smrj * didn't have enough pre-allocated space in the handle), free it. 301512f080e7Smrj */ 301612f080e7Smrj if (dma->dp_need_to_free_window) { 301712f080e7Smrj kmem_free(dma->dp_window, dma->dp_window_size); 301812f080e7Smrj } 301912f080e7Smrj } 302012f080e7Smrj 302112f080e7Smrj 302212f080e7Smrj /* 302312f080e7Smrj * rootnex_init_win() 302412f080e7Smrj * Called in bind slow path during creation of a new window. Initializes 302512f080e7Smrj * window state to default values. 302612f080e7Smrj */ 302712f080e7Smrj /*ARGSUSED*/ 302812f080e7Smrj static void 302912f080e7Smrj rootnex_init_win(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 303012f080e7Smrj rootnex_window_t *window, ddi_dma_cookie_t *cookie, off_t cur_offset) 303112f080e7Smrj { 303212f080e7Smrj hp->dmai_nwin++; 303312f080e7Smrj window->wd_dosync = B_FALSE; 303412f080e7Smrj window->wd_offset = cur_offset; 303512f080e7Smrj window->wd_size = 0; 303612f080e7Smrj window->wd_first_cookie = cookie; 303712f080e7Smrj window->wd_cookie_cnt = 0; 303812f080e7Smrj window->wd_trim.tr_trim_first = B_FALSE; 303912f080e7Smrj window->wd_trim.tr_trim_last = B_FALSE; 304012f080e7Smrj window->wd_trim.tr_first_copybuf_win = B_FALSE; 304112f080e7Smrj window->wd_trim.tr_last_copybuf_win = B_FALSE; 304212f080e7Smrj #if !defined(__amd64) 304312f080e7Smrj window->wd_remap_copybuf = dma->dp_cb_remaping; 304412f080e7Smrj #endif 304512f080e7Smrj } 304612f080e7Smrj 304712f080e7Smrj 304812f080e7Smrj /* 304912f080e7Smrj * rootnex_setup_cookie() 305012f080e7Smrj * Called in the bind slow path when the sgl uses the copy buffer. If any of 305112f080e7Smrj * the sgl uses the copy buffer, we need to go through each cookie, figure 305212f080e7Smrj * out if it uses the copy buffer, and if it does, save away everything we'll 305312f080e7Smrj * need during sync. 305412f080e7Smrj */ 305512f080e7Smrj static void 305612f080e7Smrj rootnex_setup_cookie(ddi_dma_obj_t *dmar_object, rootnex_dma_t *dma, 305712f080e7Smrj ddi_dma_cookie_t *cookie, off_t cur_offset, size_t *copybuf_used, 305812f080e7Smrj page_t **cur_pp) 305912f080e7Smrj { 306012f080e7Smrj boolean_t copybuf_sz_power_2; 306112f080e7Smrj rootnex_sglinfo_t *sinfo; 306212f080e7Smrj uint_t pidx; 306312f080e7Smrj uint_t pcnt; 306412f080e7Smrj off_t poff; 306512f080e7Smrj #if defined(__amd64) 306612f080e7Smrj pfn_t pfn; 306712f080e7Smrj #else 306812f080e7Smrj page_t **pplist; 306912f080e7Smrj #endif 307012f080e7Smrj 307112f080e7Smrj sinfo = &dma->dp_sglinfo; 307212f080e7Smrj 307312f080e7Smrj /* 307412f080e7Smrj * Calculate the page index relative to the start of the buffer. The 307512f080e7Smrj * index to the current page for our buffer is the offset into the 307612f080e7Smrj * first page of the buffer plus our current offset into the buffer 307712f080e7Smrj * itself, shifted of course... 307812f080e7Smrj */ 307912f080e7Smrj pidx = (sinfo->si_buf_offset + cur_offset) >> MMU_PAGESHIFT; 308012f080e7Smrj ASSERT(pidx < sinfo->si_max_pages); 308112f080e7Smrj 308212f080e7Smrj /* if this cookie uses the copy buffer */ 308312f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 308412f080e7Smrj /* 308512f080e7Smrj * NOTE: we know that since this cookie uses the copy buffer, it 308612f080e7Smrj * is <= MMU_PAGESIZE. 308712f080e7Smrj */ 308812f080e7Smrj 308912f080e7Smrj /* 309012f080e7Smrj * get the offset into the page. For the 64-bit kernel, get the 309112f080e7Smrj * pfn which we'll use with seg kpm. 309212f080e7Smrj */ 309312f080e7Smrj poff = cookie->_dmu._dmac_ll & MMU_PAGEOFFSET; 309412f080e7Smrj #if defined(__amd64) 309512f080e7Smrj pfn = cookie->_dmu._dmac_ll >> MMU_PAGESHIFT; 309612f080e7Smrj #endif 309712f080e7Smrj 309812f080e7Smrj /* figure out if the copybuf size is a power of 2 */ 309912f080e7Smrj if (dma->dp_copybuf_size & (dma->dp_copybuf_size - 1)) { 310012f080e7Smrj copybuf_sz_power_2 = B_FALSE; 310112f080e7Smrj } else { 310212f080e7Smrj copybuf_sz_power_2 = B_TRUE; 310312f080e7Smrj } 310412f080e7Smrj 310512f080e7Smrj /* This page uses the copy buffer */ 310612f080e7Smrj dma->dp_pgmap[pidx].pm_uses_copybuf = B_TRUE; 310712f080e7Smrj 310812f080e7Smrj /* 310912f080e7Smrj * save the copy buffer KVA that we'll use with this page. 311012f080e7Smrj * if we still fit within the copybuf, it's a simple add. 311112f080e7Smrj * otherwise, we need to wrap over using & or % accordingly. 311212f080e7Smrj */ 311312f080e7Smrj if ((*copybuf_used + MMU_PAGESIZE) <= dma->dp_copybuf_size) { 311412f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr = dma->dp_cbaddr + 311512f080e7Smrj *copybuf_used; 311612f080e7Smrj } else { 311712f080e7Smrj if (copybuf_sz_power_2) { 311812f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr = (caddr_t)( 311912f080e7Smrj (uintptr_t)dma->dp_cbaddr + 312012f080e7Smrj (*copybuf_used & 312112f080e7Smrj (dma->dp_copybuf_size - 1))); 312212f080e7Smrj } else { 312312f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr = (caddr_t)( 312412f080e7Smrj (uintptr_t)dma->dp_cbaddr + 312512f080e7Smrj (*copybuf_used % dma->dp_copybuf_size)); 312612f080e7Smrj } 312712f080e7Smrj } 312812f080e7Smrj 312912f080e7Smrj /* 313012f080e7Smrj * over write the cookie physical address with the address of 313112f080e7Smrj * the physical address of the copy buffer page that we will 313212f080e7Smrj * use. 313312f080e7Smrj */ 313412f080e7Smrj cookie->_dmu._dmac_ll = ptob64(hat_getpfnum(kas.a_hat, 313512f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr)) + poff; 313612f080e7Smrj 313712f080e7Smrj /* if we have a kernel VA, it's easy, just save that address */ 313812f080e7Smrj if ((dmar_object->dmao_type != DMA_OTYP_PAGES) && 313912f080e7Smrj (sinfo->si_asp == &kas)) { 314012f080e7Smrj /* 314112f080e7Smrj * save away the page aligned virtual address of the 314212f080e7Smrj * driver buffer. Offsets are handled in the sync code. 314312f080e7Smrj */ 314412f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = (caddr_t)(((uintptr_t) 314512f080e7Smrj dmar_object->dmao_obj.virt_obj.v_addr + cur_offset) 314612f080e7Smrj & MMU_PAGEMASK); 314712f080e7Smrj #if !defined(__amd64) 314812f080e7Smrj /* 314912f080e7Smrj * we didn't need to, and will never need to map this 315012f080e7Smrj * page. 315112f080e7Smrj */ 315212f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_FALSE; 315312f080e7Smrj #endif 315412f080e7Smrj 315512f080e7Smrj /* we don't have a kernel VA. We need one for the bcopy. */ 315612f080e7Smrj } else { 315712f080e7Smrj #if defined(__amd64) 315812f080e7Smrj /* 315912f080e7Smrj * for the 64-bit kernel, it's easy. We use seg kpm to 316012f080e7Smrj * get a Kernel VA for the corresponding pfn. 316112f080e7Smrj */ 316212f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = hat_kpm_pfn2va(pfn); 316312f080e7Smrj #else 316412f080e7Smrj /* 316512f080e7Smrj * for the 32-bit kernel, this is a pain. First we'll 316612f080e7Smrj * save away the page_t or user VA for this page. This 316712f080e7Smrj * is needed in rootnex_dma_win() when we switch to a 316812f080e7Smrj * new window which requires us to re-map the copy 316912f080e7Smrj * buffer. 317012f080e7Smrj */ 317112f080e7Smrj pplist = dmar_object->dmao_obj.virt_obj.v_priv; 317212f080e7Smrj if (dmar_object->dmao_type == DMA_OTYP_PAGES) { 317312f080e7Smrj dma->dp_pgmap[pidx].pm_pp = *cur_pp; 317412f080e7Smrj dma->dp_pgmap[pidx].pm_vaddr = NULL; 317512f080e7Smrj } else if (pplist != NULL) { 317612f080e7Smrj dma->dp_pgmap[pidx].pm_pp = pplist[pidx]; 317712f080e7Smrj dma->dp_pgmap[pidx].pm_vaddr = NULL; 317812f080e7Smrj } else { 317912f080e7Smrj dma->dp_pgmap[pidx].pm_pp = NULL; 318012f080e7Smrj dma->dp_pgmap[pidx].pm_vaddr = (caddr_t) 318112f080e7Smrj (((uintptr_t) 318212f080e7Smrj dmar_object->dmao_obj.virt_obj.v_addr + 318312f080e7Smrj cur_offset) & MMU_PAGEMASK); 318412f080e7Smrj } 318512f080e7Smrj 318612f080e7Smrj /* 318712f080e7Smrj * save away the page aligned virtual address which was 318812f080e7Smrj * allocated from the kernel heap arena (taking into 318912f080e7Smrj * account if we need more copy buffer than we alloced 319012f080e7Smrj * and use multiple windows to handle this, i.e. &,%). 319112f080e7Smrj * NOTE: there isn't and physical memory backing up this 319212f080e7Smrj * virtual address space currently. 319312f080e7Smrj */ 319412f080e7Smrj if ((*copybuf_used + MMU_PAGESIZE) <= 319512f080e7Smrj dma->dp_copybuf_size) { 319612f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = (caddr_t) 319712f080e7Smrj (((uintptr_t)dma->dp_kva + *copybuf_used) & 319812f080e7Smrj MMU_PAGEMASK); 319912f080e7Smrj } else { 320012f080e7Smrj if (copybuf_sz_power_2) { 320112f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = (caddr_t) 320212f080e7Smrj (((uintptr_t)dma->dp_kva + 320312f080e7Smrj (*copybuf_used & 320412f080e7Smrj (dma->dp_copybuf_size - 1))) & 320512f080e7Smrj MMU_PAGEMASK); 320612f080e7Smrj } else { 320712f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr = (caddr_t) 320812f080e7Smrj (((uintptr_t)dma->dp_kva + 320912f080e7Smrj (*copybuf_used % 321012f080e7Smrj dma->dp_copybuf_size)) & 321112f080e7Smrj MMU_PAGEMASK); 321212f080e7Smrj } 321312f080e7Smrj } 321412f080e7Smrj 321512f080e7Smrj /* 321612f080e7Smrj * if we haven't used up the available copy buffer yet, 321712f080e7Smrj * map the kva to the physical page. 321812f080e7Smrj */ 321912f080e7Smrj if (!dma->dp_cb_remaping && ((*copybuf_used + 322012f080e7Smrj MMU_PAGESIZE) <= dma->dp_copybuf_size)) { 322112f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_TRUE; 322212f080e7Smrj if (dma->dp_pgmap[pidx].pm_pp != NULL) { 322312f080e7Smrj i86_pp_map(dma->dp_pgmap[pidx].pm_pp, 322412f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr); 322512f080e7Smrj } else { 322612f080e7Smrj i86_va_map(dma->dp_pgmap[pidx].pm_vaddr, 322712f080e7Smrj sinfo->si_asp, 322812f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr); 322912f080e7Smrj } 323012f080e7Smrj 323112f080e7Smrj /* 323212f080e7Smrj * we've used up the available copy buffer, this page 323312f080e7Smrj * will have to be mapped during rootnex_dma_win() when 323412f080e7Smrj * we switch to a new window which requires a re-map 323512f080e7Smrj * the copy buffer. (32-bit kernel only) 323612f080e7Smrj */ 323712f080e7Smrj } else { 323812f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_FALSE; 323912f080e7Smrj } 324012f080e7Smrj #endif 324112f080e7Smrj /* go to the next page_t */ 324212f080e7Smrj if (dmar_object->dmao_type == DMA_OTYP_PAGES) { 324312f080e7Smrj *cur_pp = (*cur_pp)->p_next; 324412f080e7Smrj } 324512f080e7Smrj } 324612f080e7Smrj 324712f080e7Smrj /* add to the copy buffer count */ 324812f080e7Smrj *copybuf_used += MMU_PAGESIZE; 324912f080e7Smrj 325012f080e7Smrj /* 325112f080e7Smrj * This cookie doesn't use the copy buffer. Walk through the pages this 325212f080e7Smrj * cookie occupies to reflect this. 325312f080e7Smrj */ 325412f080e7Smrj } else { 325512f080e7Smrj /* 325612f080e7Smrj * figure out how many pages the cookie occupies. We need to 325712f080e7Smrj * use the original page offset of the buffer and the cookies 325812f080e7Smrj * offset in the buffer to do this. 325912f080e7Smrj */ 326012f080e7Smrj poff = (sinfo->si_buf_offset + cur_offset) & MMU_PAGEOFFSET; 326112f080e7Smrj pcnt = mmu_btopr(cookie->dmac_size + poff); 326212f080e7Smrj 326312f080e7Smrj while (pcnt > 0) { 326412f080e7Smrj #if !defined(__amd64) 326512f080e7Smrj /* 326612f080e7Smrj * the 32-bit kernel doesn't have seg kpm, so we need 326712f080e7Smrj * to map in the driver buffer (if it didn't come down 326812f080e7Smrj * with a kernel VA) on the fly. Since this page doesn't 326912f080e7Smrj * use the copy buffer, it's not, or will it ever, have 327012f080e7Smrj * to be mapped in. 327112f080e7Smrj */ 327212f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_FALSE; 327312f080e7Smrj #endif 327412f080e7Smrj dma->dp_pgmap[pidx].pm_uses_copybuf = B_FALSE; 327512f080e7Smrj 327612f080e7Smrj /* 327712f080e7Smrj * we need to update pidx and cur_pp or we'll loose 327812f080e7Smrj * track of where we are. 327912f080e7Smrj */ 328012f080e7Smrj if (dmar_object->dmao_type == DMA_OTYP_PAGES) { 328112f080e7Smrj *cur_pp = (*cur_pp)->p_next; 328212f080e7Smrj } 328312f080e7Smrj pidx++; 328412f080e7Smrj pcnt--; 328512f080e7Smrj } 328612f080e7Smrj } 328712f080e7Smrj } 328812f080e7Smrj 328912f080e7Smrj 329012f080e7Smrj /* 329112f080e7Smrj * rootnex_sgllen_window_boundary() 329212f080e7Smrj * Called in the bind slow path when the next cookie causes us to exceed (in 329312f080e7Smrj * this case == since we start at 0 and sgllen starts at 1) the maximum sgl 329412f080e7Smrj * length supported by the DMA H/W. 329512f080e7Smrj */ 329612f080e7Smrj static int 329712f080e7Smrj rootnex_sgllen_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 329812f080e7Smrj rootnex_window_t **windowp, ddi_dma_cookie_t *cookie, ddi_dma_attr_t *attr, 329912f080e7Smrj off_t cur_offset) 330012f080e7Smrj { 330112f080e7Smrj off_t new_offset; 330212f080e7Smrj size_t trim_sz; 330312f080e7Smrj off_t coffset; 330412f080e7Smrj 330512f080e7Smrj 330612f080e7Smrj /* 330712f080e7Smrj * if we know we'll never have to trim, it's pretty easy. Just move to 330812f080e7Smrj * the next window and init it. We're done. 330912f080e7Smrj */ 331012f080e7Smrj if (!dma->dp_trim_required) { 331112f080e7Smrj (*windowp)++; 331212f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, cur_offset); 331312f080e7Smrj (*windowp)->wd_cookie_cnt++; 331412f080e7Smrj (*windowp)->wd_size = cookie->dmac_size; 331512f080e7Smrj return (DDI_SUCCESS); 331612f080e7Smrj } 331712f080e7Smrj 331812f080e7Smrj /* figure out how much we need to trim from the window */ 331912f080e7Smrj ASSERT(attr->dma_attr_granular != 0); 332012f080e7Smrj if (dma->dp_granularity_power_2) { 332112f080e7Smrj trim_sz = (*windowp)->wd_size & (attr->dma_attr_granular - 1); 332212f080e7Smrj } else { 332312f080e7Smrj trim_sz = (*windowp)->wd_size % attr->dma_attr_granular; 332412f080e7Smrj } 332512f080e7Smrj 332612f080e7Smrj /* The window's a whole multiple of granularity. We're done */ 332712f080e7Smrj if (trim_sz == 0) { 332812f080e7Smrj (*windowp)++; 332912f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, cur_offset); 333012f080e7Smrj (*windowp)->wd_cookie_cnt++; 333112f080e7Smrj (*windowp)->wd_size = cookie->dmac_size; 333212f080e7Smrj return (DDI_SUCCESS); 333312f080e7Smrj } 333412f080e7Smrj 333512f080e7Smrj /* 333612f080e7Smrj * The window's not a whole multiple of granularity, since we know this 333712f080e7Smrj * is due to the sgllen, we need to go back to the last cookie and trim 333812f080e7Smrj * that one, add the left over part of the old cookie into the new 333912f080e7Smrj * window, and then add in the new cookie into the new window. 334012f080e7Smrj */ 334112f080e7Smrj 334212f080e7Smrj /* 334312f080e7Smrj * make sure the driver isn't making us do something bad... Trimming and 334412f080e7Smrj * sgllen == 1 don't go together. 334512f080e7Smrj */ 334612f080e7Smrj if (attr->dma_attr_sgllen == 1) { 334712f080e7Smrj return (DDI_DMA_NOMAPPING); 334812f080e7Smrj } 334912f080e7Smrj 335012f080e7Smrj /* 335112f080e7Smrj * first, setup the current window to account for the trim. Need to go 335212f080e7Smrj * back to the last cookie for this. 335312f080e7Smrj */ 335412f080e7Smrj cookie--; 335512f080e7Smrj (*windowp)->wd_trim.tr_trim_last = B_TRUE; 335612f080e7Smrj (*windowp)->wd_trim.tr_last_cookie = cookie; 335712f080e7Smrj (*windowp)->wd_trim.tr_last_paddr = cookie->_dmu._dmac_ll; 335812f080e7Smrj ASSERT(cookie->dmac_size > trim_sz); 335912f080e7Smrj (*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz; 336012f080e7Smrj (*windowp)->wd_size -= trim_sz; 336112f080e7Smrj 336212f080e7Smrj /* save the buffer offsets for the next window */ 336312f080e7Smrj coffset = cookie->dmac_size - trim_sz; 336412f080e7Smrj new_offset = (*windowp)->wd_offset + (*windowp)->wd_size; 336512f080e7Smrj 336612f080e7Smrj /* 336712f080e7Smrj * set this now in case this is the first window. all other cases are 336812f080e7Smrj * set in dma_win() 336912f080e7Smrj */ 337012f080e7Smrj cookie->dmac_size = (*windowp)->wd_trim.tr_last_size; 337112f080e7Smrj 337212f080e7Smrj /* 337312f080e7Smrj * initialize the next window using what's left over in the previous 337412f080e7Smrj * cookie. 337512f080e7Smrj */ 337612f080e7Smrj (*windowp)++; 337712f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, new_offset); 337812f080e7Smrj (*windowp)->wd_cookie_cnt++; 337912f080e7Smrj (*windowp)->wd_trim.tr_trim_first = B_TRUE; 338012f080e7Smrj (*windowp)->wd_trim.tr_first_paddr = cookie->_dmu._dmac_ll + coffset; 338112f080e7Smrj (*windowp)->wd_trim.tr_first_size = trim_sz; 338212f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 338312f080e7Smrj (*windowp)->wd_dosync = B_TRUE; 338412f080e7Smrj } 338512f080e7Smrj 338612f080e7Smrj /* 338712f080e7Smrj * now go back to the current cookie and add it to the new window. set 338812f080e7Smrj * the new window size to the what was left over from the previous 338912f080e7Smrj * cookie and what's in the current cookie. 339012f080e7Smrj */ 339112f080e7Smrj cookie++; 339212f080e7Smrj (*windowp)->wd_cookie_cnt++; 339312f080e7Smrj (*windowp)->wd_size = trim_sz + cookie->dmac_size; 339412f080e7Smrj 339512f080e7Smrj /* 339612f080e7Smrj * trim plus the next cookie could put us over maxxfer (a cookie can be 339712f080e7Smrj * a max size of maxxfer). Handle that case. 339812f080e7Smrj */ 339912f080e7Smrj if ((*windowp)->wd_size > dma->dp_maxxfer) { 340012f080e7Smrj /* 340112f080e7Smrj * maxxfer is already a whole multiple of granularity, and this 340212f080e7Smrj * trim will be <= the previous trim (since a cookie can't be 340312f080e7Smrj * larger than maxxfer). Make things simple here. 340412f080e7Smrj */ 340512f080e7Smrj trim_sz = (*windowp)->wd_size - dma->dp_maxxfer; 340612f080e7Smrj (*windowp)->wd_trim.tr_trim_last = B_TRUE; 340712f080e7Smrj (*windowp)->wd_trim.tr_last_cookie = cookie; 340812f080e7Smrj (*windowp)->wd_trim.tr_last_paddr = cookie->_dmu._dmac_ll; 340912f080e7Smrj (*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz; 341012f080e7Smrj (*windowp)->wd_size -= trim_sz; 341112f080e7Smrj ASSERT((*windowp)->wd_size == dma->dp_maxxfer); 341212f080e7Smrj 341312f080e7Smrj /* save the buffer offsets for the next window */ 341412f080e7Smrj coffset = cookie->dmac_size - trim_sz; 341512f080e7Smrj new_offset = (*windowp)->wd_offset + (*windowp)->wd_size; 341612f080e7Smrj 341712f080e7Smrj /* setup the next window */ 341812f080e7Smrj (*windowp)++; 341912f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, new_offset); 342012f080e7Smrj (*windowp)->wd_cookie_cnt++; 342112f080e7Smrj (*windowp)->wd_trim.tr_trim_first = B_TRUE; 342212f080e7Smrj (*windowp)->wd_trim.tr_first_paddr = cookie->_dmu._dmac_ll + 342312f080e7Smrj coffset; 342412f080e7Smrj (*windowp)->wd_trim.tr_first_size = trim_sz; 342512f080e7Smrj } 342612f080e7Smrj 342712f080e7Smrj return (DDI_SUCCESS); 342812f080e7Smrj } 342912f080e7Smrj 343012f080e7Smrj 343112f080e7Smrj /* 343212f080e7Smrj * rootnex_copybuf_window_boundary() 343312f080e7Smrj * Called in bind slowpath when we get to a window boundary because we used 343412f080e7Smrj * up all the copy buffer that we have. 343512f080e7Smrj */ 343612f080e7Smrj static int 343712f080e7Smrj rootnex_copybuf_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 343812f080e7Smrj rootnex_window_t **windowp, ddi_dma_cookie_t *cookie, off_t cur_offset, 343912f080e7Smrj size_t *copybuf_used) 344012f080e7Smrj { 344112f080e7Smrj rootnex_sglinfo_t *sinfo; 344212f080e7Smrj off_t new_offset; 344312f080e7Smrj size_t trim_sz; 344412f080e7Smrj off_t coffset; 344512f080e7Smrj uint_t pidx; 344612f080e7Smrj off_t poff; 344712f080e7Smrj 344812f080e7Smrj 344912f080e7Smrj sinfo = &dma->dp_sglinfo; 345012f080e7Smrj 345112f080e7Smrj /* 345212f080e7Smrj * the copy buffer should be a whole multiple of page size. We know that 345312f080e7Smrj * this cookie is <= MMU_PAGESIZE. 345412f080e7Smrj */ 345512f080e7Smrj ASSERT(cookie->dmac_size <= MMU_PAGESIZE); 345612f080e7Smrj 345712f080e7Smrj /* 345812f080e7Smrj * from now on, all new windows in this bind need to be re-mapped during 345912f080e7Smrj * ddi_dma_getwin() (32-bit kernel only). i.e. we ran out out copybuf 346012f080e7Smrj * space... 346112f080e7Smrj */ 346212f080e7Smrj #if !defined(__amd64) 346312f080e7Smrj dma->dp_cb_remaping = B_TRUE; 346412f080e7Smrj #endif 346512f080e7Smrj 346612f080e7Smrj /* reset copybuf used */ 346712f080e7Smrj *copybuf_used = 0; 346812f080e7Smrj 346912f080e7Smrj /* 347012f080e7Smrj * if we don't have to trim (since granularity is set to 1), go to the 347112f080e7Smrj * next window and add the current cookie to it. We know the current 347212f080e7Smrj * cookie uses the copy buffer since we're in this code path. 347312f080e7Smrj */ 347412f080e7Smrj if (!dma->dp_trim_required) { 347512f080e7Smrj (*windowp)++; 347612f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, cur_offset); 347712f080e7Smrj 347812f080e7Smrj /* Add this cookie to the new window */ 347912f080e7Smrj (*windowp)->wd_cookie_cnt++; 348012f080e7Smrj (*windowp)->wd_size += cookie->dmac_size; 348112f080e7Smrj *copybuf_used += MMU_PAGESIZE; 348212f080e7Smrj return (DDI_SUCCESS); 348312f080e7Smrj } 348412f080e7Smrj 348512f080e7Smrj /* 348612f080e7Smrj * *** may need to trim, figure it out. 348712f080e7Smrj */ 348812f080e7Smrj 348912f080e7Smrj /* figure out how much we need to trim from the window */ 349012f080e7Smrj if (dma->dp_granularity_power_2) { 349112f080e7Smrj trim_sz = (*windowp)->wd_size & 349212f080e7Smrj (hp->dmai_attr.dma_attr_granular - 1); 349312f080e7Smrj } else { 349412f080e7Smrj trim_sz = (*windowp)->wd_size % hp->dmai_attr.dma_attr_granular; 349512f080e7Smrj } 349612f080e7Smrj 349712f080e7Smrj /* 349812f080e7Smrj * if the window's a whole multiple of granularity, go to the next 349912f080e7Smrj * window, init it, then add in the current cookie. We know the current 350012f080e7Smrj * cookie uses the copy buffer since we're in this code path. 350112f080e7Smrj */ 350212f080e7Smrj if (trim_sz == 0) { 350312f080e7Smrj (*windowp)++; 350412f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, cur_offset); 350512f080e7Smrj 350612f080e7Smrj /* Add this cookie to the new window */ 350712f080e7Smrj (*windowp)->wd_cookie_cnt++; 350812f080e7Smrj (*windowp)->wd_size += cookie->dmac_size; 350912f080e7Smrj *copybuf_used += MMU_PAGESIZE; 351012f080e7Smrj return (DDI_SUCCESS); 351112f080e7Smrj } 351212f080e7Smrj 351312f080e7Smrj /* 351412f080e7Smrj * *** We figured it out, we definitly need to trim 351512f080e7Smrj */ 351612f080e7Smrj 351712f080e7Smrj /* 351812f080e7Smrj * make sure the driver isn't making us do something bad... 351912f080e7Smrj * Trimming and sgllen == 1 don't go together. 352012f080e7Smrj */ 352112f080e7Smrj if (hp->dmai_attr.dma_attr_sgllen == 1) { 352212f080e7Smrj return (DDI_DMA_NOMAPPING); 352312f080e7Smrj } 352412f080e7Smrj 352512f080e7Smrj /* 352612f080e7Smrj * first, setup the current window to account for the trim. Need to go 352712f080e7Smrj * back to the last cookie for this. Some of the last cookie will be in 352812f080e7Smrj * the current window, and some of the last cookie will be in the new 352912f080e7Smrj * window. All of the current cookie will be in the new window. 353012f080e7Smrj */ 353112f080e7Smrj cookie--; 353212f080e7Smrj (*windowp)->wd_trim.tr_trim_last = B_TRUE; 353312f080e7Smrj (*windowp)->wd_trim.tr_last_cookie = cookie; 353412f080e7Smrj (*windowp)->wd_trim.tr_last_paddr = cookie->_dmu._dmac_ll; 353512f080e7Smrj ASSERT(cookie->dmac_size > trim_sz); 353612f080e7Smrj (*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz; 353712f080e7Smrj (*windowp)->wd_size -= trim_sz; 353812f080e7Smrj 353912f080e7Smrj /* 354012f080e7Smrj * we're trimming the last cookie (not the current cookie). So that 354112f080e7Smrj * last cookie may have or may not have been using the copy buffer ( 354212f080e7Smrj * we know the cookie passed in uses the copy buffer since we're in 354312f080e7Smrj * this code path). 354412f080e7Smrj * 354512f080e7Smrj * If the last cookie doesn't use the copy buffer, nothing special to 354612f080e7Smrj * do. However, if it does uses the copy buffer, it will be both the 354712f080e7Smrj * last page in the current window and the first page in the next 354812f080e7Smrj * window. Since we are reusing the copy buffer (and KVA space on the 354912f080e7Smrj * 32-bit kernel), this page will use the end of the copy buffer in the 355012f080e7Smrj * current window, and the start of the copy buffer in the next window. 355112f080e7Smrj * Track that info... The cookie physical address was already set to 355212f080e7Smrj * the copy buffer physical address in setup_cookie.. 355312f080e7Smrj */ 355412f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 355512f080e7Smrj pidx = (sinfo->si_buf_offset + (*windowp)->wd_offset + 355612f080e7Smrj (*windowp)->wd_size) >> MMU_PAGESHIFT; 355712f080e7Smrj (*windowp)->wd_trim.tr_last_copybuf_win = B_TRUE; 355812f080e7Smrj (*windowp)->wd_trim.tr_last_pidx = pidx; 355912f080e7Smrj (*windowp)->wd_trim.tr_last_cbaddr = 356012f080e7Smrj dma->dp_pgmap[pidx].pm_cbaddr; 356112f080e7Smrj #if !defined(__amd64) 356212f080e7Smrj (*windowp)->wd_trim.tr_last_kaddr = 356312f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr; 356412f080e7Smrj #endif 356512f080e7Smrj } 356612f080e7Smrj 356712f080e7Smrj /* save the buffer offsets for the next window */ 356812f080e7Smrj coffset = cookie->dmac_size - trim_sz; 356912f080e7Smrj new_offset = (*windowp)->wd_offset + (*windowp)->wd_size; 357012f080e7Smrj 357112f080e7Smrj /* 357212f080e7Smrj * set this now in case this is the first window. all other cases are 357312f080e7Smrj * set in dma_win() 357412f080e7Smrj */ 357512f080e7Smrj cookie->dmac_size = (*windowp)->wd_trim.tr_last_size; 357612f080e7Smrj 357712f080e7Smrj /* 357812f080e7Smrj * initialize the next window using what's left over in the previous 357912f080e7Smrj * cookie. 358012f080e7Smrj */ 358112f080e7Smrj (*windowp)++; 358212f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, new_offset); 358312f080e7Smrj (*windowp)->wd_cookie_cnt++; 358412f080e7Smrj (*windowp)->wd_trim.tr_trim_first = B_TRUE; 358512f080e7Smrj (*windowp)->wd_trim.tr_first_paddr = cookie->_dmu._dmac_ll + coffset; 358612f080e7Smrj (*windowp)->wd_trim.tr_first_size = trim_sz; 358712f080e7Smrj 358812f080e7Smrj /* 358912f080e7Smrj * again, we're tracking if the last cookie uses the copy buffer. 359012f080e7Smrj * read the comment above for more info on why we need to track 359112f080e7Smrj * additional state. 359212f080e7Smrj * 359312f080e7Smrj * For the first cookie in the new window, we need reset the physical 359412f080e7Smrj * address to DMA into to the start of the copy buffer plus any 359512f080e7Smrj * initial page offset which may be present. 359612f080e7Smrj */ 359712f080e7Smrj if (cookie->dmac_type & ROOTNEX_USES_COPYBUF) { 359812f080e7Smrj (*windowp)->wd_dosync = B_TRUE; 359912f080e7Smrj (*windowp)->wd_trim.tr_first_copybuf_win = B_TRUE; 360012f080e7Smrj (*windowp)->wd_trim.tr_first_pidx = pidx; 360112f080e7Smrj (*windowp)->wd_trim.tr_first_cbaddr = dma->dp_cbaddr; 360212f080e7Smrj poff = (*windowp)->wd_trim.tr_first_paddr & MMU_PAGEOFFSET; 360312f080e7Smrj (*windowp)->wd_trim.tr_first_paddr = ptob64(hat_getpfnum( 360412f080e7Smrj kas.a_hat, dma->dp_cbaddr)) + poff; 360512f080e7Smrj #if !defined(__amd64) 360612f080e7Smrj (*windowp)->wd_trim.tr_first_kaddr = dma->dp_kva; 360712f080e7Smrj #endif 360812f080e7Smrj /* account for the cookie copybuf usage in the new window */ 360912f080e7Smrj *copybuf_used += MMU_PAGESIZE; 361012f080e7Smrj 361112f080e7Smrj /* 361212f080e7Smrj * every piece of code has to have a hack, and here is this 361312f080e7Smrj * ones :-) 361412f080e7Smrj * 361512f080e7Smrj * There is a complex interaction between setup_cookie and the 361612f080e7Smrj * copybuf window boundary. The complexity had to be in either 361712f080e7Smrj * the maxxfer window, or the copybuf window, and I chose the 361812f080e7Smrj * copybuf code. 361912f080e7Smrj * 362012f080e7Smrj * So in this code path, we have taken the last cookie, 362112f080e7Smrj * virtually broken it in half due to the trim, and it happens 362212f080e7Smrj * to use the copybuf which further complicates life. At the 362312f080e7Smrj * same time, we have already setup the current cookie, which 362412f080e7Smrj * is now wrong. More background info: the current cookie uses 362512f080e7Smrj * the copybuf, so it is only a page long max. So we need to 362612f080e7Smrj * fix the current cookies copy buffer address, physical 362712f080e7Smrj * address, and kva for the 32-bit kernel. We due this by 362812f080e7Smrj * bumping them by page size (of course, we can't due this on 362912f080e7Smrj * the physical address since the copy buffer may not be 363012f080e7Smrj * physically contiguous). 363112f080e7Smrj */ 363212f080e7Smrj cookie++; 363312f080e7Smrj dma->dp_pgmap[pidx + 1].pm_cbaddr += MMU_PAGESIZE; 363412f080e7Smrj poff = cookie->_dmu._dmac_ll & MMU_PAGEOFFSET; 363512f080e7Smrj cookie->_dmu._dmac_ll = ptob64(hat_getpfnum(kas.a_hat, 363612f080e7Smrj dma->dp_pgmap[pidx + 1].pm_cbaddr)) + poff; 363712f080e7Smrj #if !defined(__amd64) 363812f080e7Smrj ASSERT(dma->dp_pgmap[pidx + 1].pm_mapped == B_FALSE); 363912f080e7Smrj dma->dp_pgmap[pidx + 1].pm_kaddr += MMU_PAGESIZE; 364012f080e7Smrj #endif 364112f080e7Smrj } else { 364212f080e7Smrj /* go back to the current cookie */ 364312f080e7Smrj cookie++; 364412f080e7Smrj } 364512f080e7Smrj 364612f080e7Smrj /* 364712f080e7Smrj * add the current cookie to the new window. set the new window size to 364812f080e7Smrj * the what was left over from the previous cookie and what's in the 364912f080e7Smrj * current cookie. 365012f080e7Smrj */ 365112f080e7Smrj (*windowp)->wd_cookie_cnt++; 365212f080e7Smrj (*windowp)->wd_size = trim_sz + cookie->dmac_size; 365312f080e7Smrj ASSERT((*windowp)->wd_size < dma->dp_maxxfer); 365412f080e7Smrj 365512f080e7Smrj /* 365612f080e7Smrj * we know that the cookie passed in always uses the copy buffer. We 365712f080e7Smrj * wouldn't be here if it didn't. 365812f080e7Smrj */ 365912f080e7Smrj *copybuf_used += MMU_PAGESIZE; 366012f080e7Smrj 366112f080e7Smrj return (DDI_SUCCESS); 366212f080e7Smrj } 366312f080e7Smrj 366412f080e7Smrj 366512f080e7Smrj /* 366612f080e7Smrj * rootnex_maxxfer_window_boundary() 366712f080e7Smrj * Called in bind slowpath when we get to a window boundary because we will 366812f080e7Smrj * go over maxxfer. 366912f080e7Smrj */ 367012f080e7Smrj static int 367112f080e7Smrj rootnex_maxxfer_window_boundary(ddi_dma_impl_t *hp, rootnex_dma_t *dma, 367212f080e7Smrj rootnex_window_t **windowp, ddi_dma_cookie_t *cookie) 367312f080e7Smrj { 367412f080e7Smrj size_t dmac_size; 367512f080e7Smrj off_t new_offset; 367612f080e7Smrj size_t trim_sz; 367712f080e7Smrj off_t coffset; 367812f080e7Smrj 367912f080e7Smrj 368012f080e7Smrj /* 368112f080e7Smrj * calculate how much we have to trim off of the current cookie to equal 368212f080e7Smrj * maxxfer. We don't have to account for granularity here since our 368312f080e7Smrj * maxxfer already takes that into account. 368412f080e7Smrj */ 368512f080e7Smrj trim_sz = ((*windowp)->wd_size + cookie->dmac_size) - dma->dp_maxxfer; 368612f080e7Smrj ASSERT(trim_sz <= cookie->dmac_size); 368712f080e7Smrj ASSERT(trim_sz <= dma->dp_maxxfer); 368812f080e7Smrj 368912f080e7Smrj /* save cookie size since we need it later and we might change it */ 369012f080e7Smrj dmac_size = cookie->dmac_size; 369112f080e7Smrj 369212f080e7Smrj /* 369312f080e7Smrj * if we're not trimming the entire cookie, setup the current window to 369412f080e7Smrj * account for the trim. 369512f080e7Smrj */ 369612f080e7Smrj if (trim_sz < cookie->dmac_size) { 369712f080e7Smrj (*windowp)->wd_cookie_cnt++; 369812f080e7Smrj (*windowp)->wd_trim.tr_trim_last = B_TRUE; 369912f080e7Smrj (*windowp)->wd_trim.tr_last_cookie = cookie; 370012f080e7Smrj (*windowp)->wd_trim.tr_last_paddr = cookie->_dmu._dmac_ll; 370112f080e7Smrj (*windowp)->wd_trim.tr_last_size = cookie->dmac_size - trim_sz; 370212f080e7Smrj (*windowp)->wd_size = dma->dp_maxxfer; 370312f080e7Smrj 370412f080e7Smrj /* 370512f080e7Smrj * set the adjusted cookie size now in case this is the first 370612f080e7Smrj * window. All other windows are taken care of in get win 370712f080e7Smrj */ 370812f080e7Smrj cookie->dmac_size = (*windowp)->wd_trim.tr_last_size; 370912f080e7Smrj } 371012f080e7Smrj 371112f080e7Smrj /* 371212f080e7Smrj * coffset is the current offset within the cookie, new_offset is the 371312f080e7Smrj * current offset with the entire buffer. 371412f080e7Smrj */ 371512f080e7Smrj coffset = dmac_size - trim_sz; 371612f080e7Smrj new_offset = (*windowp)->wd_offset + (*windowp)->wd_size; 371712f080e7Smrj 371812f080e7Smrj /* initialize the next window */ 371912f080e7Smrj (*windowp)++; 372012f080e7Smrj rootnex_init_win(hp, dma, *windowp, cookie, new_offset); 372112f080e7Smrj (*windowp)->wd_cookie_cnt++; 372212f080e7Smrj (*windowp)->wd_size = trim_sz; 372312f080e7Smrj if (trim_sz < dmac_size) { 372412f080e7Smrj (*windowp)->wd_trim.tr_trim_first = B_TRUE; 372512f080e7Smrj (*windowp)->wd_trim.tr_first_paddr = cookie->_dmu._dmac_ll + 372612f080e7Smrj coffset; 372712f080e7Smrj (*windowp)->wd_trim.tr_first_size = trim_sz; 372812f080e7Smrj } 372912f080e7Smrj 373012f080e7Smrj return (DDI_SUCCESS); 373112f080e7Smrj } 373212f080e7Smrj 373312f080e7Smrj 373412f080e7Smrj /* 373512f080e7Smrj * rootnex_dma_sync() 373612f080e7Smrj * called from ddi_dma_sync() if DMP_NOSYNC is not set in hp->dmai_rflags. 373712f080e7Smrj * We set DMP_NOSYNC if we're not using the copy buffer. If DMP_NOSYNC 373812f080e7Smrj * is set, ddi_dma_sync() returns immediately passing back success. 373912f080e7Smrj */ 374012f080e7Smrj /*ARGSUSED*/ 374112f080e7Smrj static int 374212f080e7Smrj rootnex_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 374312f080e7Smrj off_t off, size_t len, uint_t cache_flags) 374412f080e7Smrj { 374512f080e7Smrj rootnex_sglinfo_t *sinfo; 374612f080e7Smrj rootnex_pgmap_t *cbpage; 374712f080e7Smrj rootnex_window_t *win; 374812f080e7Smrj ddi_dma_impl_t *hp; 374912f080e7Smrj rootnex_dma_t *dma; 375012f080e7Smrj caddr_t fromaddr; 375112f080e7Smrj caddr_t toaddr; 375212f080e7Smrj uint_t psize; 375312f080e7Smrj off_t offset; 375412f080e7Smrj uint_t pidx; 375512f080e7Smrj size_t size; 375612f080e7Smrj off_t poff; 375712f080e7Smrj int e; 375812f080e7Smrj 375912f080e7Smrj 376012f080e7Smrj hp = (ddi_dma_impl_t *)handle; 376112f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 376212f080e7Smrj sinfo = &dma->dp_sglinfo; 376312f080e7Smrj 376412f080e7Smrj /* 376512f080e7Smrj * if we don't have any windows, we don't need to sync. A copybuf 376612f080e7Smrj * will cause us to have at least one window. 376712f080e7Smrj */ 376812f080e7Smrj if (dma->dp_window == NULL) { 376912f080e7Smrj return (DDI_SUCCESS); 377012f080e7Smrj } 377112f080e7Smrj 377212f080e7Smrj /* This window may not need to be sync'd */ 377312f080e7Smrj win = &dma->dp_window[dma->dp_current_win]; 377412f080e7Smrj if (!win->wd_dosync) { 377512f080e7Smrj return (DDI_SUCCESS); 377612f080e7Smrj } 377712f080e7Smrj 377812f080e7Smrj /* handle off and len special cases */ 377912f080e7Smrj if ((off == 0) || (rootnex_sync_ignore_params)) { 378012f080e7Smrj offset = win->wd_offset; 378112f080e7Smrj } else { 378212f080e7Smrj offset = off; 378312f080e7Smrj } 378412f080e7Smrj if ((len == 0) || (rootnex_sync_ignore_params)) { 378512f080e7Smrj size = win->wd_size; 378612f080e7Smrj } else { 378712f080e7Smrj size = len; 378812f080e7Smrj } 378912f080e7Smrj 379012f080e7Smrj /* check the sync args to make sure they make a little sense */ 379112f080e7Smrj if (rootnex_sync_check_parms) { 379212f080e7Smrj e = rootnex_valid_sync_parms(hp, win, offset, size, 379312f080e7Smrj cache_flags); 379412f080e7Smrj if (e != DDI_SUCCESS) { 379512f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_SYNC_FAIL]); 379612f080e7Smrj return (DDI_FAILURE); 379712f080e7Smrj } 379812f080e7Smrj } 379912f080e7Smrj 380012f080e7Smrj /* 380112f080e7Smrj * special case the first page to handle the offset into the page. The 380212f080e7Smrj * offset to the current page for our buffer is the offset into the 380312f080e7Smrj * first page of the buffer plus our current offset into the buffer 380412f080e7Smrj * itself, masked of course. 380512f080e7Smrj */ 380612f080e7Smrj poff = (sinfo->si_buf_offset + offset) & MMU_PAGEOFFSET; 380712f080e7Smrj psize = MIN((MMU_PAGESIZE - poff), size); 380812f080e7Smrj 380912f080e7Smrj /* go through all the pages that we want to sync */ 381012f080e7Smrj while (size > 0) { 381112f080e7Smrj /* 381212f080e7Smrj * Calculate the page index relative to the start of the buffer. 381312f080e7Smrj * The index to the current page for our buffer is the offset 381412f080e7Smrj * into the first page of the buffer plus our current offset 381512f080e7Smrj * into the buffer itself, shifted of course... 381612f080e7Smrj */ 381712f080e7Smrj pidx = (sinfo->si_buf_offset + offset) >> MMU_PAGESHIFT; 381812f080e7Smrj ASSERT(pidx < sinfo->si_max_pages); 381912f080e7Smrj 382012f080e7Smrj /* 382112f080e7Smrj * if this page uses the copy buffer, we need to sync it, 382212f080e7Smrj * otherwise, go on to the next page. 382312f080e7Smrj */ 382412f080e7Smrj cbpage = &dma->dp_pgmap[pidx]; 382512f080e7Smrj ASSERT((cbpage->pm_uses_copybuf == B_TRUE) || 382612f080e7Smrj (cbpage->pm_uses_copybuf == B_FALSE)); 382712f080e7Smrj if (cbpage->pm_uses_copybuf) { 382812f080e7Smrj /* cbaddr and kaddr should be page aligned */ 382912f080e7Smrj ASSERT(((uintptr_t)cbpage->pm_cbaddr & 383012f080e7Smrj MMU_PAGEOFFSET) == 0); 383112f080e7Smrj ASSERT(((uintptr_t)cbpage->pm_kaddr & 383212f080e7Smrj MMU_PAGEOFFSET) == 0); 383312f080e7Smrj 383412f080e7Smrj /* 383512f080e7Smrj * if we're copying for the device, we are going to 383612f080e7Smrj * copy from the drivers buffer and to the rootnex 383712f080e7Smrj * allocated copy buffer. 383812f080e7Smrj */ 383912f080e7Smrj if (cache_flags == DDI_DMA_SYNC_FORDEV) { 384012f080e7Smrj fromaddr = cbpage->pm_kaddr + poff; 384112f080e7Smrj toaddr = cbpage->pm_cbaddr + poff; 384212f080e7Smrj DTRACE_PROBE2(rootnex__sync__dev, 384312f080e7Smrj dev_info_t *, dma->dp_dip, size_t, psize); 384412f080e7Smrj 384512f080e7Smrj /* 384612f080e7Smrj * if we're copying for the cpu/kernel, we are going to 384712f080e7Smrj * copy from the rootnex allocated copy buffer to the 384812f080e7Smrj * drivers buffer. 384912f080e7Smrj */ 385012f080e7Smrj } else { 385112f080e7Smrj fromaddr = cbpage->pm_cbaddr + poff; 385212f080e7Smrj toaddr = cbpage->pm_kaddr + poff; 385312f080e7Smrj DTRACE_PROBE2(rootnex__sync__cpu, 385412f080e7Smrj dev_info_t *, dma->dp_dip, size_t, psize); 385512f080e7Smrj } 385612f080e7Smrj 385712f080e7Smrj bcopy(fromaddr, toaddr, psize); 385812f080e7Smrj } 385912f080e7Smrj 386012f080e7Smrj /* 386112f080e7Smrj * decrement size until we're done, update our offset into the 386212f080e7Smrj * buffer, and get the next page size. 386312f080e7Smrj */ 386412f080e7Smrj size -= psize; 386512f080e7Smrj offset += psize; 386612f080e7Smrj psize = MIN(MMU_PAGESIZE, size); 386712f080e7Smrj 386812f080e7Smrj /* page offset is zero for the rest of this loop */ 386912f080e7Smrj poff = 0; 387012f080e7Smrj } 387112f080e7Smrj 387212f080e7Smrj return (DDI_SUCCESS); 387312f080e7Smrj } 387412f080e7Smrj 387512f080e7Smrj 387612f080e7Smrj /* 387712f080e7Smrj * rootnex_valid_sync_parms() 387812f080e7Smrj * checks the parameters passed to sync to verify they are correct. 387912f080e7Smrj */ 388012f080e7Smrj static int 388112f080e7Smrj rootnex_valid_sync_parms(ddi_dma_impl_t *hp, rootnex_window_t *win, 388212f080e7Smrj off_t offset, size_t size, uint_t cache_flags) 388312f080e7Smrj { 388412f080e7Smrj off_t woffset; 388512f080e7Smrj 388612f080e7Smrj 388712f080e7Smrj /* 388812f080e7Smrj * the first part of the test to make sure the offset passed in is 388912f080e7Smrj * within the window. 389012f080e7Smrj */ 389112f080e7Smrj if (offset < win->wd_offset) { 389212f080e7Smrj return (DDI_FAILURE); 389312f080e7Smrj } 389412f080e7Smrj 389512f080e7Smrj /* 389612f080e7Smrj * second and last part of the test to make sure the offset and length 389712f080e7Smrj * passed in is within the window. 389812f080e7Smrj */ 389912f080e7Smrj woffset = offset - win->wd_offset; 390012f080e7Smrj if ((woffset + size) > win->wd_size) { 390112f080e7Smrj return (DDI_FAILURE); 390212f080e7Smrj } 390312f080e7Smrj 390412f080e7Smrj /* 390512f080e7Smrj * if we are sync'ing for the device, the DDI_DMA_WRITE flag should 390612f080e7Smrj * be set too. 390712f080e7Smrj */ 390812f080e7Smrj if ((cache_flags == DDI_DMA_SYNC_FORDEV) && 390912f080e7Smrj (hp->dmai_rflags & DDI_DMA_WRITE)) { 391012f080e7Smrj return (DDI_SUCCESS); 391112f080e7Smrj } 391212f080e7Smrj 391312f080e7Smrj /* 391412f080e7Smrj * at this point, either DDI_DMA_SYNC_FORCPU or DDI_DMA_SYNC_FORKERNEL 391512f080e7Smrj * should be set. Also DDI_DMA_READ should be set in the flags. 391612f080e7Smrj */ 391712f080e7Smrj if (((cache_flags == DDI_DMA_SYNC_FORCPU) || 391812f080e7Smrj (cache_flags == DDI_DMA_SYNC_FORKERNEL)) && 391912f080e7Smrj (hp->dmai_rflags & DDI_DMA_READ)) { 392012f080e7Smrj return (DDI_SUCCESS); 392112f080e7Smrj } 392212f080e7Smrj 392312f080e7Smrj return (DDI_FAILURE); 392412f080e7Smrj } 392512f080e7Smrj 392612f080e7Smrj 392712f080e7Smrj /* 392812f080e7Smrj * rootnex_dma_win() 392912f080e7Smrj * called from ddi_dma_getwin() 393012f080e7Smrj */ 393112f080e7Smrj /*ARGSUSED*/ 393212f080e7Smrj static int 393312f080e7Smrj rootnex_dma_win(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 393412f080e7Smrj uint_t win, off_t *offp, size_t *lenp, ddi_dma_cookie_t *cookiep, 393512f080e7Smrj uint_t *ccountp) 393612f080e7Smrj { 393712f080e7Smrj rootnex_window_t *window; 393812f080e7Smrj rootnex_trim_t *trim; 393912f080e7Smrj ddi_dma_impl_t *hp; 394012f080e7Smrj rootnex_dma_t *dma; 394112f080e7Smrj #if !defined(__amd64) 394212f080e7Smrj rootnex_sglinfo_t *sinfo; 394312f080e7Smrj rootnex_pgmap_t *pmap; 394412f080e7Smrj uint_t pidx; 394512f080e7Smrj uint_t pcnt; 394612f080e7Smrj off_t poff; 394712f080e7Smrj int i; 394812f080e7Smrj #endif 394912f080e7Smrj 395012f080e7Smrj 395112f080e7Smrj hp = (ddi_dma_impl_t *)handle; 395212f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 395312f080e7Smrj #if !defined(__amd64) 395412f080e7Smrj sinfo = &dma->dp_sglinfo; 395512f080e7Smrj #endif 395612f080e7Smrj 395712f080e7Smrj /* If we try and get a window which doesn't exist, return failure */ 395812f080e7Smrj if (win >= hp->dmai_nwin) { 395912f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_GETWIN_FAIL]); 396012f080e7Smrj return (DDI_FAILURE); 396112f080e7Smrj } 396212f080e7Smrj 396312f080e7Smrj /* 396412f080e7Smrj * if we don't have any windows, and they're asking for the first 396512f080e7Smrj * window, setup the cookie pointer to the first cookie in the bind. 396612f080e7Smrj * setup our return values, then increment the cookie since we return 396712f080e7Smrj * the first cookie on the stack. 396812f080e7Smrj */ 396912f080e7Smrj if (dma->dp_window == NULL) { 397012f080e7Smrj if (win != 0) { 397112f080e7Smrj ROOTNEX_PROF_INC(&rootnex_cnt[ROOTNEX_CNT_GETWIN_FAIL]); 397212f080e7Smrj return (DDI_FAILURE); 397312f080e7Smrj } 397412f080e7Smrj hp->dmai_cookie = dma->dp_cookies; 397512f080e7Smrj *offp = 0; 397612f080e7Smrj *lenp = dma->dp_dma.dmao_size; 397712f080e7Smrj *ccountp = dma->dp_sglinfo.si_sgl_size; 397812f080e7Smrj *cookiep = hp->dmai_cookie[0]; 397912f080e7Smrj hp->dmai_cookie++; 398012f080e7Smrj return (DDI_SUCCESS); 398112f080e7Smrj } 398212f080e7Smrj 398312f080e7Smrj /* sync the old window before moving on to the new one */ 398412f080e7Smrj window = &dma->dp_window[dma->dp_current_win]; 398512f080e7Smrj if ((window->wd_dosync) && (hp->dmai_rflags & DDI_DMA_READ)) { 398612f080e7Smrj (void) rootnex_dma_sync(dip, rdip, handle, 0, 0, 398712f080e7Smrj DDI_DMA_SYNC_FORCPU); 398812f080e7Smrj } 398912f080e7Smrj 399012f080e7Smrj #if !defined(__amd64) 399112f080e7Smrj /* 399212f080e7Smrj * before we move to the next window, if we need to re-map, unmap all 399312f080e7Smrj * the pages in this window. 399412f080e7Smrj */ 399512f080e7Smrj if (dma->dp_cb_remaping) { 399612f080e7Smrj /* 399712f080e7Smrj * If we switch to this window again, we'll need to map in 399812f080e7Smrj * on the fly next time. 399912f080e7Smrj */ 400012f080e7Smrj window->wd_remap_copybuf = B_TRUE; 400112f080e7Smrj 400212f080e7Smrj /* 400312f080e7Smrj * calculate the page index into the buffer where this window 400412f080e7Smrj * starts, and the number of pages this window takes up. 400512f080e7Smrj */ 400612f080e7Smrj pidx = (sinfo->si_buf_offset + window->wd_offset) >> 400712f080e7Smrj MMU_PAGESHIFT; 400812f080e7Smrj poff = (sinfo->si_buf_offset + window->wd_offset) & 400912f080e7Smrj MMU_PAGEOFFSET; 401012f080e7Smrj pcnt = mmu_btopr(window->wd_size + poff); 401112f080e7Smrj ASSERT((pidx + pcnt) <= sinfo->si_max_pages); 401212f080e7Smrj 401312f080e7Smrj /* unmap pages which are currently mapped in this window */ 401412f080e7Smrj for (i = 0; i < pcnt; i++) { 401512f080e7Smrj if (dma->dp_pgmap[pidx].pm_mapped) { 401612f080e7Smrj hat_unload(kas.a_hat, 401712f080e7Smrj dma->dp_pgmap[pidx].pm_kaddr, MMU_PAGESIZE, 401812f080e7Smrj HAT_UNLOAD); 401912f080e7Smrj dma->dp_pgmap[pidx].pm_mapped = B_FALSE; 402012f080e7Smrj } 402112f080e7Smrj pidx++; 402212f080e7Smrj } 402312f080e7Smrj } 402412f080e7Smrj #endif 402512f080e7Smrj 402612f080e7Smrj /* 402712f080e7Smrj * Move to the new window. 402812f080e7Smrj * NOTE: current_win must be set for sync to work right 402912f080e7Smrj */ 403012f080e7Smrj dma->dp_current_win = win; 403112f080e7Smrj window = &dma->dp_window[win]; 403212f080e7Smrj 403312f080e7Smrj /* if needed, adjust the first and/or last cookies for trim */ 403412f080e7Smrj trim = &window->wd_trim; 403512f080e7Smrj if (trim->tr_trim_first) { 403612f080e7Smrj window->wd_first_cookie->_dmu._dmac_ll = trim->tr_first_paddr; 403712f080e7Smrj window->wd_first_cookie->dmac_size = trim->tr_first_size; 403812f080e7Smrj #if !defined(__amd64) 403912f080e7Smrj window->wd_first_cookie->dmac_type = 404012f080e7Smrj (window->wd_first_cookie->dmac_type & 404112f080e7Smrj ROOTNEX_USES_COPYBUF) + window->wd_offset; 404212f080e7Smrj #endif 404312f080e7Smrj if (trim->tr_first_copybuf_win) { 404412f080e7Smrj dma->dp_pgmap[trim->tr_first_pidx].pm_cbaddr = 404512f080e7Smrj trim->tr_first_cbaddr; 404612f080e7Smrj #if !defined(__amd64) 404712f080e7Smrj dma->dp_pgmap[trim->tr_first_pidx].pm_kaddr = 404812f080e7Smrj trim->tr_first_kaddr; 404912f080e7Smrj #endif 405012f080e7Smrj } 405112f080e7Smrj } 405212f080e7Smrj if (trim->tr_trim_last) { 405312f080e7Smrj trim->tr_last_cookie->_dmu._dmac_ll = trim->tr_last_paddr; 405412f080e7Smrj trim->tr_last_cookie->dmac_size = trim->tr_last_size; 405512f080e7Smrj if (trim->tr_last_copybuf_win) { 405612f080e7Smrj dma->dp_pgmap[trim->tr_last_pidx].pm_cbaddr = 405712f080e7Smrj trim->tr_last_cbaddr; 405812f080e7Smrj #if !defined(__amd64) 405912f080e7Smrj dma->dp_pgmap[trim->tr_last_pidx].pm_kaddr = 406012f080e7Smrj trim->tr_last_kaddr; 406112f080e7Smrj #endif 406212f080e7Smrj } 406312f080e7Smrj } 406412f080e7Smrj 406512f080e7Smrj /* 406612f080e7Smrj * setup the cookie pointer to the first cookie in the window. setup 406712f080e7Smrj * our return values, then increment the cookie since we return the 406812f080e7Smrj * first cookie on the stack. 406912f080e7Smrj */ 407012f080e7Smrj hp->dmai_cookie = window->wd_first_cookie; 407112f080e7Smrj *offp = window->wd_offset; 407212f080e7Smrj *lenp = window->wd_size; 407312f080e7Smrj *ccountp = window->wd_cookie_cnt; 407412f080e7Smrj *cookiep = hp->dmai_cookie[0]; 407512f080e7Smrj hp->dmai_cookie++; 407612f080e7Smrj 407712f080e7Smrj #if !defined(__amd64) 407812f080e7Smrj /* re-map copybuf if required for this window */ 407912f080e7Smrj if (dma->dp_cb_remaping) { 408012f080e7Smrj /* 408112f080e7Smrj * calculate the page index into the buffer where this 408212f080e7Smrj * window starts. 408312f080e7Smrj */ 408412f080e7Smrj pidx = (sinfo->si_buf_offset + window->wd_offset) >> 408512f080e7Smrj MMU_PAGESHIFT; 408612f080e7Smrj ASSERT(pidx < sinfo->si_max_pages); 408712f080e7Smrj 408812f080e7Smrj /* 408912f080e7Smrj * the first page can get unmapped if it's shared with the 409012f080e7Smrj * previous window. Even if the rest of this window is already 409112f080e7Smrj * mapped in, we need to still check this one. 409212f080e7Smrj */ 409312f080e7Smrj pmap = &dma->dp_pgmap[pidx]; 409412f080e7Smrj if ((pmap->pm_uses_copybuf) && (pmap->pm_mapped == B_FALSE)) { 409512f080e7Smrj if (pmap->pm_pp != NULL) { 409612f080e7Smrj pmap->pm_mapped = B_TRUE; 409712f080e7Smrj i86_pp_map(pmap->pm_pp, pmap->pm_kaddr); 409812f080e7Smrj } else if (pmap->pm_vaddr != NULL) { 409912f080e7Smrj pmap->pm_mapped = B_TRUE; 410012f080e7Smrj i86_va_map(pmap->pm_vaddr, sinfo->si_asp, 410112f080e7Smrj pmap->pm_kaddr); 410212f080e7Smrj } 410312f080e7Smrj } 410412f080e7Smrj pidx++; 410512f080e7Smrj 410612f080e7Smrj /* map in the rest of the pages if required */ 410712f080e7Smrj if (window->wd_remap_copybuf) { 410812f080e7Smrj window->wd_remap_copybuf = B_FALSE; 410912f080e7Smrj 411012f080e7Smrj /* figure out many pages this window takes up */ 411112f080e7Smrj poff = (sinfo->si_buf_offset + window->wd_offset) & 411212f080e7Smrj MMU_PAGEOFFSET; 411312f080e7Smrj pcnt = mmu_btopr(window->wd_size + poff); 411412f080e7Smrj ASSERT(((pidx - 1) + pcnt) <= sinfo->si_max_pages); 411512f080e7Smrj 411612f080e7Smrj /* map pages which require it */ 411712f080e7Smrj for (i = 1; i < pcnt; i++) { 411812f080e7Smrj pmap = &dma->dp_pgmap[pidx]; 411912f080e7Smrj if (pmap->pm_uses_copybuf) { 412012f080e7Smrj ASSERT(pmap->pm_mapped == B_FALSE); 412112f080e7Smrj if (pmap->pm_pp != NULL) { 412212f080e7Smrj pmap->pm_mapped = B_TRUE; 412312f080e7Smrj i86_pp_map(pmap->pm_pp, 412412f080e7Smrj pmap->pm_kaddr); 412512f080e7Smrj } else if (pmap->pm_vaddr != NULL) { 412612f080e7Smrj pmap->pm_mapped = B_TRUE; 412712f080e7Smrj i86_va_map(pmap->pm_vaddr, 412812f080e7Smrj sinfo->si_asp, 412912f080e7Smrj pmap->pm_kaddr); 413012f080e7Smrj } 413112f080e7Smrj } 413212f080e7Smrj pidx++; 413312f080e7Smrj } 413412f080e7Smrj } 413512f080e7Smrj } 413612f080e7Smrj #endif 413712f080e7Smrj 413812f080e7Smrj /* if the new window uses the copy buffer, sync it for the device */ 413912f080e7Smrj if ((window->wd_dosync) && (hp->dmai_rflags & DDI_DMA_WRITE)) { 414012f080e7Smrj (void) rootnex_dma_sync(dip, rdip, handle, 0, 0, 414112f080e7Smrj DDI_DMA_SYNC_FORDEV); 414212f080e7Smrj } 414312f080e7Smrj 414412f080e7Smrj return (DDI_SUCCESS); 414512f080e7Smrj } 414612f080e7Smrj 414712f080e7Smrj 414812f080e7Smrj 414912f080e7Smrj /* 415012f080e7Smrj * ************************ 415112f080e7Smrj * obsoleted dma routines 415212f080e7Smrj * ************************ 415312f080e7Smrj */ 415412f080e7Smrj 415512f080e7Smrj /* 415612f080e7Smrj * rootnex_dma_map() 415712f080e7Smrj * called from ddi_dma_setup() 415812f080e7Smrj */ 415912f080e7Smrj /* ARGSUSED */ 416012f080e7Smrj static int 416112f080e7Smrj rootnex_dma_map(dev_info_t *dip, dev_info_t *rdip, struct ddi_dma_req *dmareq, 416212f080e7Smrj ddi_dma_handle_t *handlep) 416312f080e7Smrj { 416412f080e7Smrj #if defined(__amd64) 416512f080e7Smrj /* 416612f080e7Smrj * this interface is not supported in 64-bit x86 kernel. See comment in 416712f080e7Smrj * rootnex_dma_mctl() 416812f080e7Smrj */ 416912f080e7Smrj return (DDI_DMA_NORESOURCES); 417012f080e7Smrj 417112f080e7Smrj #else /* 32-bit x86 kernel */ 417212f080e7Smrj ddi_dma_handle_t *lhandlep; 417312f080e7Smrj ddi_dma_handle_t lhandle; 417412f080e7Smrj ddi_dma_cookie_t cookie; 417512f080e7Smrj ddi_dma_attr_t dma_attr; 417612f080e7Smrj ddi_dma_lim_t *dma_lim; 417712f080e7Smrj uint_t ccnt; 417812f080e7Smrj int e; 417912f080e7Smrj 418012f080e7Smrj 418112f080e7Smrj /* 418212f080e7Smrj * if the driver is just testing to see if it's possible to do the bind, 418312f080e7Smrj * we'll use local state. Otherwise, use the handle pointer passed in. 418412f080e7Smrj */ 418512f080e7Smrj if (handlep == NULL) { 418612f080e7Smrj lhandlep = &lhandle; 418712f080e7Smrj } else { 418812f080e7Smrj lhandlep = handlep; 418912f080e7Smrj } 419012f080e7Smrj 419112f080e7Smrj /* convert the limit structure to a dma_attr one */ 419212f080e7Smrj dma_lim = dmareq->dmar_limits; 419312f080e7Smrj dma_attr.dma_attr_version = DMA_ATTR_V0; 419412f080e7Smrj dma_attr.dma_attr_addr_lo = dma_lim->dlim_addr_lo; 419512f080e7Smrj dma_attr.dma_attr_addr_hi = dma_lim->dlim_addr_hi; 419612f080e7Smrj dma_attr.dma_attr_minxfer = dma_lim->dlim_minxfer; 419712f080e7Smrj dma_attr.dma_attr_seg = dma_lim->dlim_adreg_max; 419812f080e7Smrj dma_attr.dma_attr_count_max = dma_lim->dlim_ctreg_max; 419912f080e7Smrj dma_attr.dma_attr_granular = dma_lim->dlim_granular; 420012f080e7Smrj dma_attr.dma_attr_sgllen = dma_lim->dlim_sgllen; 420112f080e7Smrj dma_attr.dma_attr_maxxfer = dma_lim->dlim_reqsize; 420212f080e7Smrj dma_attr.dma_attr_burstsizes = dma_lim->dlim_burstsizes; 420312f080e7Smrj dma_attr.dma_attr_align = MMU_PAGESIZE; 420412f080e7Smrj dma_attr.dma_attr_flags = 0; 420512f080e7Smrj 420612f080e7Smrj e = rootnex_dma_allochdl(dip, rdip, &dma_attr, dmareq->dmar_fp, 420712f080e7Smrj dmareq->dmar_arg, lhandlep); 420812f080e7Smrj if (e != DDI_SUCCESS) { 420912f080e7Smrj return (e); 421012f080e7Smrj } 421112f080e7Smrj 421212f080e7Smrj e = rootnex_dma_bindhdl(dip, rdip, *lhandlep, dmareq, &cookie, &ccnt); 421312f080e7Smrj if ((e != DDI_DMA_MAPPED) && (e != DDI_DMA_PARTIAL_MAP)) { 421412f080e7Smrj (void) rootnex_dma_freehdl(dip, rdip, *lhandlep); 421512f080e7Smrj return (e); 421612f080e7Smrj } 421712f080e7Smrj 421812f080e7Smrj /* 421912f080e7Smrj * if the driver is just testing to see if it's possible to do the bind, 422012f080e7Smrj * free up the local state and return the result. 422112f080e7Smrj */ 422212f080e7Smrj if (handlep == NULL) { 422312f080e7Smrj (void) rootnex_dma_unbindhdl(dip, rdip, *lhandlep); 422412f080e7Smrj (void) rootnex_dma_freehdl(dip, rdip, *lhandlep); 422512f080e7Smrj if (e == DDI_DMA_MAPPED) { 422612f080e7Smrj return (DDI_DMA_MAPOK); 422712f080e7Smrj } else { 422812f080e7Smrj return (DDI_DMA_NOMAPPING); 422912f080e7Smrj } 423012f080e7Smrj } 423112f080e7Smrj 423212f080e7Smrj return (e); 423312f080e7Smrj #endif /* defined(__amd64) */ 423412f080e7Smrj } 423512f080e7Smrj 423612f080e7Smrj 423712f080e7Smrj /* 423812f080e7Smrj * rootnex_dma_mctl() 423912f080e7Smrj * 424012f080e7Smrj */ 424112f080e7Smrj /* ARGSUSED */ 424212f080e7Smrj static int 424312f080e7Smrj rootnex_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 424412f080e7Smrj enum ddi_dma_ctlops request, off_t *offp, size_t *lenp, caddr_t *objpp, 424512f080e7Smrj uint_t cache_flags) 424612f080e7Smrj { 424712f080e7Smrj #if defined(__amd64) 424812f080e7Smrj /* 424912f080e7Smrj * DDI_DMA_SMEM_ALLOC & DDI_DMA_IOPB_ALLOC we're changed to have a 425012f080e7Smrj * common implementation in genunix, so they no longer have x86 425112f080e7Smrj * specific functionality which called into dma_ctl. 425212f080e7Smrj * 425312f080e7Smrj * The rest of the obsoleted interfaces were never supported in the 425412f080e7Smrj * 64-bit x86 kernel. For s10, the obsoleted DDI_DMA_SEGTOC interface 425512f080e7Smrj * was not ported to the x86 64-bit kernel do to serious x86 rootnex 425612f080e7Smrj * implementation issues. 425712f080e7Smrj * 425812f080e7Smrj * If you can't use DDI_DMA_SEGTOC; DDI_DMA_NEXTSEG, DDI_DMA_FREE, and 425912f080e7Smrj * DDI_DMA_NEXTWIN are useless since you can get to the cookie, so we 426012f080e7Smrj * reflect that now too... 426112f080e7Smrj * 426212f080e7Smrj * Even though we fixed the pointer problem in DDI_DMA_SEGTOC, we are 426312f080e7Smrj * not going to put this functionality into the 64-bit x86 kernel now. 426412f080e7Smrj * It wasn't ported to the 64-bit kernel for s10, no reason to change 426512f080e7Smrj * that in a future release. 426612f080e7Smrj */ 426712f080e7Smrj return (DDI_FAILURE); 426812f080e7Smrj 426912f080e7Smrj #else /* 32-bit x86 kernel */ 427012f080e7Smrj ddi_dma_cookie_t lcookie; 427112f080e7Smrj ddi_dma_cookie_t *cookie; 427212f080e7Smrj rootnex_window_t *window; 427312f080e7Smrj ddi_dma_impl_t *hp; 427412f080e7Smrj rootnex_dma_t *dma; 427512f080e7Smrj uint_t nwin; 427612f080e7Smrj uint_t ccnt; 427712f080e7Smrj size_t len; 427812f080e7Smrj off_t off; 427912f080e7Smrj int e; 428012f080e7Smrj 428112f080e7Smrj 428212f080e7Smrj /* 428312f080e7Smrj * DDI_DMA_SEGTOC, DDI_DMA_NEXTSEG, and DDI_DMA_NEXTWIN are a little 428412f080e7Smrj * hacky since were optimizing for the current interfaces and so we can 428512f080e7Smrj * cleanup the mess in genunix. Hopefully we will remove the this 428612f080e7Smrj * obsoleted routines someday soon. 428712f080e7Smrj */ 428812f080e7Smrj 428912f080e7Smrj switch (request) { 429012f080e7Smrj 429112f080e7Smrj case DDI_DMA_SEGTOC: /* ddi_dma_segtocookie() */ 429212f080e7Smrj hp = (ddi_dma_impl_t *)handle; 429312f080e7Smrj cookie = (ddi_dma_cookie_t *)objpp; 429412f080e7Smrj 429512f080e7Smrj /* 429612f080e7Smrj * convert segment to cookie. We don't distinguish between the 429712f080e7Smrj * two :-) 429812f080e7Smrj */ 429912f080e7Smrj *cookie = *hp->dmai_cookie; 430012f080e7Smrj *lenp = cookie->dmac_size; 430112f080e7Smrj *offp = cookie->dmac_type & ~ROOTNEX_USES_COPYBUF; 430212f080e7Smrj return (DDI_SUCCESS); 430312f080e7Smrj 430412f080e7Smrj case DDI_DMA_NEXTSEG: /* ddi_dma_nextseg() */ 430512f080e7Smrj hp = (ddi_dma_impl_t *)handle; 430612f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 430712f080e7Smrj 430812f080e7Smrj if ((*lenp != NULL) && ((uintptr_t)*lenp != (uintptr_t)hp)) { 430912f080e7Smrj return (DDI_DMA_STALE); 431012f080e7Smrj } 431112f080e7Smrj 431212f080e7Smrj /* handle the case where we don't have any windows */ 431312f080e7Smrj if (dma->dp_window == NULL) { 431412f080e7Smrj /* 431512f080e7Smrj * if seg == NULL, and we don't have any windows, 431612f080e7Smrj * return the first cookie in the sgl. 431712f080e7Smrj */ 431812f080e7Smrj if (*lenp == NULL) { 431912f080e7Smrj dma->dp_current_cookie = 0; 432012f080e7Smrj hp->dmai_cookie = dma->dp_cookies; 432112f080e7Smrj *objpp = (caddr_t)handle; 432212f080e7Smrj return (DDI_SUCCESS); 432312f080e7Smrj 432412f080e7Smrj /* if we have more cookies, go to the next cookie */ 432512f080e7Smrj } else { 432612f080e7Smrj if ((dma->dp_current_cookie + 1) >= 432712f080e7Smrj dma->dp_sglinfo.si_sgl_size) { 432812f080e7Smrj return (DDI_DMA_DONE); 432912f080e7Smrj } 433012f080e7Smrj dma->dp_current_cookie++; 433112f080e7Smrj hp->dmai_cookie++; 433212f080e7Smrj return (DDI_SUCCESS); 433312f080e7Smrj } 433412f080e7Smrj } 433512f080e7Smrj 433612f080e7Smrj /* We have one or more windows */ 433712f080e7Smrj window = &dma->dp_window[dma->dp_current_win]; 433812f080e7Smrj 433912f080e7Smrj /* 434012f080e7Smrj * if seg == NULL, return the first cookie in the current 434112f080e7Smrj * window 434212f080e7Smrj */ 434312f080e7Smrj if (*lenp == NULL) { 434412f080e7Smrj dma->dp_current_cookie = 0; 4345cf4e9a1dSmrj hp->dmai_cookie = window->wd_first_cookie; 434612f080e7Smrj 434712f080e7Smrj /* 434812f080e7Smrj * go to the next cookie in the window then see if we done with 434912f080e7Smrj * this window. 435012f080e7Smrj */ 435112f080e7Smrj } else { 435212f080e7Smrj if ((dma->dp_current_cookie + 1) >= 435312f080e7Smrj window->wd_cookie_cnt) { 435412f080e7Smrj return (DDI_DMA_DONE); 435512f080e7Smrj } 435612f080e7Smrj dma->dp_current_cookie++; 435712f080e7Smrj hp->dmai_cookie++; 435812f080e7Smrj } 435912f080e7Smrj *objpp = (caddr_t)handle; 436012f080e7Smrj return (DDI_SUCCESS); 436112f080e7Smrj 436212f080e7Smrj case DDI_DMA_NEXTWIN: /* ddi_dma_nextwin() */ 436312f080e7Smrj hp = (ddi_dma_impl_t *)handle; 436412f080e7Smrj dma = (rootnex_dma_t *)hp->dmai_private; 436512f080e7Smrj 436612f080e7Smrj if ((*offp != NULL) && ((uintptr_t)*offp != (uintptr_t)hp)) { 436712f080e7Smrj return (DDI_DMA_STALE); 436812f080e7Smrj } 436912f080e7Smrj 437012f080e7Smrj /* if win == NULL, return the first window in the bind */ 437112f080e7Smrj if (*offp == NULL) { 437212f080e7Smrj nwin = 0; 437312f080e7Smrj 437412f080e7Smrj /* 437512f080e7Smrj * else, go to the next window then see if we're done with all 437612f080e7Smrj * the windows. 437712f080e7Smrj */ 437812f080e7Smrj } else { 437912f080e7Smrj nwin = dma->dp_current_win + 1; 438012f080e7Smrj if (nwin >= hp->dmai_nwin) { 438112f080e7Smrj return (DDI_DMA_DONE); 438212f080e7Smrj } 438312f080e7Smrj } 438412f080e7Smrj 438512f080e7Smrj /* switch to the next window */ 438612f080e7Smrj e = rootnex_dma_win(dip, rdip, handle, nwin, &off, &len, 438712f080e7Smrj &lcookie, &ccnt); 438812f080e7Smrj ASSERT(e == DDI_SUCCESS); 438912f080e7Smrj if (e != DDI_SUCCESS) { 439012f080e7Smrj return (DDI_DMA_STALE); 439112f080e7Smrj } 439212f080e7Smrj 439312f080e7Smrj /* reset the cookie back to the first cookie in the window */ 439412f080e7Smrj if (dma->dp_window != NULL) { 439512f080e7Smrj window = &dma->dp_window[dma->dp_current_win]; 439612f080e7Smrj hp->dmai_cookie = window->wd_first_cookie; 439712f080e7Smrj } else { 439812f080e7Smrj hp->dmai_cookie = dma->dp_cookies; 439912f080e7Smrj } 440012f080e7Smrj 440112f080e7Smrj *objpp = (caddr_t)handle; 440212f080e7Smrj return (DDI_SUCCESS); 440312f080e7Smrj 440412f080e7Smrj case DDI_DMA_FREE: /* ddi_dma_free() */ 440512f080e7Smrj (void) rootnex_dma_unbindhdl(dip, rdip, handle); 440612f080e7Smrj (void) rootnex_dma_freehdl(dip, rdip, handle); 440712f080e7Smrj if (rootnex_state->r_dvma_call_list_id) { 440812f080e7Smrj ddi_run_callback(&rootnex_state->r_dvma_call_list_id); 440912f080e7Smrj } 441012f080e7Smrj return (DDI_SUCCESS); 441112f080e7Smrj 441212f080e7Smrj case DDI_DMA_IOPB_ALLOC: /* get contiguous DMA-able memory */ 441312f080e7Smrj case DDI_DMA_SMEM_ALLOC: /* get contiguous DMA-able memory */ 441412f080e7Smrj /* should never get here, handled in genunix */ 441512f080e7Smrj ASSERT(0); 441612f080e7Smrj return (DDI_FAILURE); 441712f080e7Smrj 441812f080e7Smrj case DDI_DMA_KVADDR: 441912f080e7Smrj case DDI_DMA_GETERR: 442012f080e7Smrj case DDI_DMA_COFF: 442112f080e7Smrj return (DDI_FAILURE); 442212f080e7Smrj } 442312f080e7Smrj 442412f080e7Smrj return (DDI_FAILURE); 442512f080e7Smrj #endif /* defined(__amd64) */ 44267c478bd9Sstevel@tonic-gate } 4427*7aec1d6eScindi 4428*7aec1d6eScindi /*ARGSUSED*/ 4429*7aec1d6eScindi static int 4430*7aec1d6eScindi rootnex_fm_callback(dev_info_t *dip, ddi_fm_error_t *derr, const void *no_used) 4431*7aec1d6eScindi { 4432*7aec1d6eScindi return (rootnex_fm_ma_ta_panic_flag ? DDI_FM_FATAL : DDI_FM_NONFATAL); 4433*7aec1d6eScindi } 4434