xref: /titanic_53/usr/src/uts/common/sys/ppmvar.h (revision 2df1fe9ca32bb227b9158c67f5c00b54c20b10fd)
15cff7825Smh27603 /*
25cff7825Smh27603  * CDDL HEADER START
35cff7825Smh27603  *
45cff7825Smh27603  * The contents of this file are subject to the terms of the
55cff7825Smh27603  * Common Development and Distribution License (the "License").
65cff7825Smh27603  * You may not use this file except in compliance with the License.
75cff7825Smh27603  *
85cff7825Smh27603  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
95cff7825Smh27603  * or http://www.opensolaris.org/os/licensing.
105cff7825Smh27603  * See the License for the specific language governing permissions
115cff7825Smh27603  * and limitations under the License.
125cff7825Smh27603  *
135cff7825Smh27603  * When distributing Covered Code, include this CDDL HEADER in each
145cff7825Smh27603  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
155cff7825Smh27603  * If applicable, add the following below this CDDL HEADER, with the
165cff7825Smh27603  * fields enclosed by brackets "[]" replaced with your own identifying
175cff7825Smh27603  * information: Portions Copyright [yyyy] [name of copyright owner]
185cff7825Smh27603  *
195cff7825Smh27603  * CDDL HEADER END
205cff7825Smh27603  */
215cff7825Smh27603 /*
225cff7825Smh27603  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
235cff7825Smh27603  * Use is subject to license terms.
245cff7825Smh27603  */
255cff7825Smh27603 
265cff7825Smh27603 #ifndef _SYS_PPMVAR_H
275cff7825Smh27603 #define	_SYS_PPMVAR_H
285cff7825Smh27603 
295cff7825Smh27603 #pragma ident	"%Z%%M%	%I%	%E% SMI"
305cff7825Smh27603 
315cff7825Smh27603 #include <sys/epm.h>
325cff7825Smh27603 #include <sys/sunldi.h>
335cff7825Smh27603 
345cff7825Smh27603 #ifdef	__cplusplus
355cff7825Smh27603 extern "C" {
365cff7825Smh27603 #endif
375cff7825Smh27603 
385cff7825Smh27603 
395cff7825Smh27603 typedef struct ppm_unit {
405cff7825Smh27603 	dev_info_t	*dip;		/* node dev info */
415cff7825Smh27603 	kmutex_t	lock;		/* global driver lock */
425cff7825Smh27603 	uint_t		states;		/* driver states */
435cff7825Smh27603 	timeout_id_t	led_tid;	/* timeout id for LED */
445cff7825Smh27603 } ppm_unit_t;
455cff7825Smh27603 
465cff7825Smh27603 /*
475cff7825Smh27603  * driver states
485cff7825Smh27603  */
495cff7825Smh27603 #define	PPM_STATE_SUSPENDED	0x1	/* driver is suspended */
505cff7825Smh27603 
515cff7825Smh27603 /*
525cff7825Smh27603  * Check for domain operational
535cff7825Smh27603  */
545cff7825Smh27603 #define	PPM_DOMAIN_UP(domp)	(!(domp->dflags & PPMD_OFFLINE))
555cff7825Smh27603 
565cff7825Smh27603 /*
575cff7825Smh27603  * LED constants
585cff7825Smh27603  */
595cff7825Smh27603 #define	PPM_LED_PULSE		(drv_usectohz(250000))	/* 0.25 seconds */
605cff7825Smh27603 #define	PPM_LEDON_INTERVAL	(1 * PPM_LED_PULSE)
615cff7825Smh27603 #define	PPM_LEDOFF_INTERVAL	(8 * PPM_LED_PULSE)
625cff7825Smh27603 #define	PPM_LEDON		1	/* (s10) */
635cff7825Smh27603 #define	PPM_LEDOFF		0	/* (s10) */
645cff7825Smh27603 
655cff7825Smh27603 /*
665cff7825Smh27603  * internal form of "ppm.conf" data
675cff7825Smh27603  */
685cff7825Smh27603 struct ppm_db {
695cff7825Smh27603 	struct ppm_db	*next;
705cff7825Smh27603 	char		*name;		/* device name */
715cff7825Smh27603 	int		plen;		/* strlen before wildcard(s10) */
725cff7825Smh27603 	int		wccnt;		/* upto 2 '*' allowed */
735cff7825Smh27603 	int		wcpos[2];	/* '*' location in pathname */
745cff7825Smh27603 };
755cff7825Smh27603 typedef struct ppm_db ppm_db_t;
765cff7825Smh27603 
775cff7825Smh27603 struct ppm_cdata {
785cff7825Smh27603 	char *name;			/* property name */
795cff7825Smh27603 	char **strings;			/* string array */
805cff7825Smh27603 	uint_t cnt;			/* property count */
815cff7825Smh27603 };
825cff7825Smh27603 
835cff7825Smh27603 /*
845cff7825Smh27603  * ppm device info
855cff7825Smh27603  */
865cff7825Smh27603 struct ppm_dev {
875cff7825Smh27603 	struct ppm_dev	*next;
885cff7825Smh27603 	struct ppm_domain *domp;
895cff7825Smh27603 	dev_info_t	*dip;
905cff7825Smh27603 	char		*path;		/* OBP device pathname */
915cff7825Smh27603 	int		cmpt;		/* component number */
925cff7825Smh27603 	int		rplvl;		/* last requested power level */
935cff7825Smh27603 	int		level;		/* actual current power level */
945cff7825Smh27603 	int		lowest;		/* lowest power level for device */
955cff7825Smh27603 	int		highest;	/* highest power level for device */
965cff7825Smh27603 	uint_t		flags;
975cff7825Smh27603 };
985cff7825Smh27603 typedef struct ppm_dev ppm_dev_t;
995cff7825Smh27603 
1005cff7825Smh27603 /*
1015cff7825Smh27603  * ppm_dev.flags field
1025cff7825Smh27603  */
1035cff7825Smh27603 #define	PPMDEV_PCI66_D2		0x1	/* device support D2 at pci 66mhz */
1045cff7825Smh27603 #define	PPMDEV_PCI_PROP_CLKPM	0x2	/* clock can be power managed */
1055cff7825Smh27603 #define	PPM_PM_POWEROP		0x10	/* power level change, initiated  */
1065cff7825Smh27603 					/* from PM is in progress.	  */
1075cff7825Smh27603 #define	PPM_PHC_WHILE_SET_POWER 0x20	/* power level of a device is	  */
1085cff7825Smh27603 					/* changed through		  */
1095cff7825Smh27603 					/* pm_power_has_changed path	  */
1105cff7825Smh27603 					/* while power level change,	  */
1115cff7825Smh27603 					/* initiated from PM is in	  */
1125cff7825Smh27603 					/* progress.			  */
1135cff7825Smh27603 
1145cff7825Smh27603 
1155cff7825Smh27603 /*
1165cff7825Smh27603  * per domain record of device _ever_ managed by ppm
1175cff7825Smh27603  */
1185cff7825Smh27603 struct ppm_owned {
1195cff7825Smh27603 	struct ppm_owned *next;
1205cff7825Smh27603 	char	*path;		/* device pathname */
1215cff7825Smh27603 	int	initializing;	/* initializing  flag */
1225cff7825Smh27603 };
1235cff7825Smh27603 typedef struct ppm_owned ppm_owned_t;
1245cff7825Smh27603 
1255cff7825Smh27603 
1265cff7825Smh27603 /*
1275cff7825Smh27603  * domain control data structure -
1285cff7825Smh27603  *   when you need to do an op for a domain, look up the op in the
1295cff7825Smh27603  *   cmd member of the struct, and then perform the method on the
1305cff7825Smh27603  *   path using iowr cmd with the args specified in val or val and
1315cff7825Smh27603  *   mask or the speed index.
1325cff7825Smh27603  */
1335cff7825Smh27603 struct ppm_dc {
1345cff7825Smh27603 	struct ppm_dc	*next;
1355cff7825Smh27603 	ldi_handle_t	lh;	/* layered (ldi) handle			*/
1365cff7825Smh27603 	char	*path;		/* control device prom pathname		*/
1375cff7825Smh27603 	uint_t	cmd;		/* search key: op to be performed	*/
138*2df1fe9cSrandyf 				/* one of: PPMDC_CPU_NEXT		*/
139*2df1fe9cSrandyf 				/* PPMDC_CPU_GO, PPMDC_FET_ON,		*/
140*2df1fe9cSrandyf 				/* PPMDC_FET_OFF, PPMDC_LED_ON,		*/
141*2df1fe9cSrandyf 				/* PPMDC_LED_OFF, PPMDC_PCI_ON,		*/
142*2df1fe9cSrandyf 				/* PPMDC_ENTER_S3, PPMDC_PCI_OFF	*/
143*2df1fe9cSrandyf 				/* PPMDC_EXIT_S3 commands		*/
1445cff7825Smh27603 	uint_t	method;		/* control method / union selector	*/
1455cff7825Smh27603 				/* one of PPMDC_KIO, PPMDC_I2CKIO,	*/
1465cff7825Smh27603 				/* PPMDC_CPUSPEEDKIO			*/
1475cff7825Smh27603 
1485cff7825Smh27603 	union {
1495cff7825Smh27603 		/* In each sub struct in union, the first three fields	*/
1505cff7825Smh27603 		/* must be .iord, .iowr and .val and in such order.	*/
1515cff7825Smh27603 		/* The .method field above selects a union sub struct	*/
1525cff7825Smh27603 		/* for a particular .cmd operation.			*/
1535cff7825Smh27603 		/* The association between .method and .cmd is platform	*/
1545cff7825Smh27603 		/* specific, therefore described in ppm.conf file.	*/
1555cff7825Smh27603 
1565cff7825Smh27603 		/* PPMDC_KIO: simple KIO 				*/
1575cff7825Smh27603 		struct m_kio {
1585cff7825Smh27603 			uint_t	iord;	/* IOCTL read cmd		*/
1595cff7825Smh27603 			uint_t	iowr;	/* IOCTL write cmd		*/
1605cff7825Smh27603 			uint_t	val;	/* ioctl arg			*/
1615cff7825Smh27603 			uint_t	delay;	/* total delay before this 	*/
1625cff7825Smh27603 					/* operation can be carried out	*/
1635cff7825Smh27603 			uint_t	post_delay; /* post delay, if any	*/
1645cff7825Smh27603 		} kio;
1655cff7825Smh27603 
166*2df1fe9cSrandyf #ifdef sun4u
1675cff7825Smh27603 		/* PPMDC_I2CKIO: KIO requires 'arg' as struct i2c_gpio	*/
1685cff7825Smh27603 		/*    (defined in i2c_client.h)				*/
1695cff7825Smh27603 		struct m_i2ckio {
1705cff7825Smh27603 			uint_t	iord;	/* IOCTL read cmd		*/
1715cff7825Smh27603 			uint_t	iowr;	/* IOCTL write cmd 		*/
1725cff7825Smh27603 			uint_t	val;	/* register content		*/
1735cff7825Smh27603 			uint_t	mask;	/* mask to select relevant bits	*/
1745cff7825Smh27603 					/* of register content		*/
1755cff7825Smh27603 			uint_t	delay;	/* total delay before this 	*/
1765cff7825Smh27603 					/* operation can be carried out	*/
1775cff7825Smh27603 			uint_t	post_delay; /* post delay, if any	*/
1785cff7825Smh27603 		} i2c;
179*2df1fe9cSrandyf #endif
1805cff7825Smh27603 
1815cff7825Smh27603 		/* PPMDC_CPUSPEEDKIO, PPMDC_VCORE: cpu estar related	*/
1825cff7825Smh27603 		/* simple KIO						*/
1835cff7825Smh27603 		struct m_cpu {
1845cff7825Smh27603 			uint_t	iord;	/* IOCTL read cmd 		*/
1855cff7825Smh27603 			uint_t	iowr;	/* IOCTL write cmd 		*/
1865cff7825Smh27603 			int	val;	/* new register value		*/
1875cff7825Smh27603 			uint_t	speeds;	/* number of speeds cpu supports */
1885cff7825Smh27603 			uint_t	delay;	/* microseconds post op delay	*/
1895cff7825Smh27603 		} cpu;
1905cff7825Smh27603 	} m_un;
1915cff7825Smh27603 };
1925cff7825Smh27603 typedef struct ppm_dc ppm_dc_t;
1935cff7825Smh27603 
1945cff7825Smh27603 /*
1955cff7825Smh27603  * ppm_dc.cmd field -
1965cff7825Smh27603  */
1975cff7825Smh27603 #define	PPMDC_CPU_NEXT		2
1985cff7825Smh27603 #define	PPMDC_PRE_CHNG		3
1995cff7825Smh27603 #define	PPMDC_CPU_GO		4
2005cff7825Smh27603 #define	PPMDC_POST_CHNG		5
2015cff7825Smh27603 #define	PPMDC_FET_ON		6
2025cff7825Smh27603 #define	PPMDC_FET_OFF		7
2035cff7825Smh27603 #define	PPMDC_LED_ON		8
2045cff7825Smh27603 #define	PPMDC_LED_OFF		9
2055cff7825Smh27603 #define	PPMDC_CLK_ON		10
2065cff7825Smh27603 #define	PPMDC_CLK_OFF		11
2075cff7825Smh27603 #define	PPMDC_PRE_PWR_OFF	12
2085cff7825Smh27603 #define	PPMDC_PRE_PWR_ON	13
2095cff7825Smh27603 #define	PPMDC_POST_PWR_ON	14
2105cff7825Smh27603 #define	PPMDC_PWR_OFF		15
2115cff7825Smh27603 #define	PPMDC_PWR_ON		16
2125cff7825Smh27603 #define	PPMDC_RESET_OFF		17
2135cff7825Smh27603 #define	PPMDC_RESET_ON		18
214*2df1fe9cSrandyf #define	PPMDC_ENTER_S3		19
215*2df1fe9cSrandyf #define	PPMDC_EXIT_S3		20
2165cff7825Smh27603 
2175cff7825Smh27603 /*
2185cff7825Smh27603  * ppm_dc.method field - select union element
2195cff7825Smh27603  */
2205cff7825Smh27603 #define	PPMDC_KIO  		1	/* simple ioctl with val as arg	*/
2215cff7825Smh27603 #define	PPMDC_CPUSPEEDKIO	2	/* ioctl with speed index arg	*/
2225cff7825Smh27603 #define	PPMDC_VCORE		3	/* CPU Vcore change operation */
223*2df1fe9cSrandyf #ifdef sun4u
2245cff7825Smh27603 #define	PPMDC_I2CKIO		4	/* ioctl with i2c_gpio_t as arg	*/
225*2df1fe9cSrandyf #endif
2265cff7825Smh27603 
2275cff7825Smh27603 /*
2285cff7825Smh27603  * devices that are powered by the same source
2295cff7825Smh27603  * are grouped by this struct as a "power domain"
2305cff7825Smh27603  */
2315cff7825Smh27603 struct ppm_domain {
2325cff7825Smh27603 	char		*name;		/* domain name */
2335cff7825Smh27603 	int		dflags;		/* domain flags */
2345cff7825Smh27603 	int		pwr_cnt;	/* number of powered up devices */
2355cff7825Smh27603 	ppm_db_t	*conflist;	/* all devices from ppm.conf file */
2365cff7825Smh27603 	ppm_dev_t	*devlist;	/* current attached devices */
2375cff7825Smh27603 	char		*propname;	/* domain property name */
2385cff7825Smh27603 	kmutex_t	lock;		/* domain lock */
2395cff7825Smh27603 	int		refcnt;		/* domain lock ref count */
2405cff7825Smh27603 	int		model;		/* pm model, CPU, FET or LED	*/
2415cff7825Smh27603 	int		status;		/* domain specific status */
2425cff7825Smh27603 	ppm_dc_t	*dc;		/* domain control method */
2435cff7825Smh27603 	ppm_owned_t	*owned;		/* list of ever owned devices */
2445cff7825Smh27603 	struct ppm_domain	*next;	/* a linked list */
2455cff7825Smh27603 	clock_t		last_off_time;	/* last time domain was off	*/
2465cff7825Smh27603 
2475cff7825Smh27603 };
2485cff7825Smh27603 typedef struct ppm_domain ppm_domain_t;
2495cff7825Smh27603 
2505cff7825Smh27603 
2515cff7825Smh27603 /*
2525cff7825Smh27603  * ppm_domain.model field -
2535cff7825Smh27603  */
2545cff7825Smh27603 #define	PPMD_CPU		1	/* cpu PM model */
2555cff7825Smh27603 #define	PPMD_FET		2	/* power FET pm model */
2565cff7825Smh27603 #define	PPMD_LED		3	/* LED pm model */
2575cff7825Smh27603 #define	PPMD_PCI		4	/* PCI pm model */
2585cff7825Smh27603 #define	PPMD_PCI_PROP		5	/* PCI_PROP pm model */
2595cff7825Smh27603 #define	PPMD_PCIE		6	/* PCI Express pm model */
260*2df1fe9cSrandyf #define	PPMD_SX			7	/* ACPI Sx pm model */
2615cff7825Smh27603 
2625cff7825Smh27603 #define	PPMD_IS_PCI(model) \
2635cff7825Smh27603 	((model) == PPMD_PCI || (model) == PPMD_PCI_PROP)
2645cff7825Smh27603 
2655cff7825Smh27603 /*
2665cff7825Smh27603  * ppm_domain.status field -
2675cff7825Smh27603  */
2685cff7825Smh27603 #define	PPMD_OFF		0x0	/* FET/LED/PCI clock: off */
2695cff7825Smh27603 #define	PPMD_ON			0x1	/* FET/LED/PCI clock: on */
2705cff7825Smh27603 
2715cff7825Smh27603 /*
2725cff7825Smh27603  * ppm_domain.dflags field -
2735cff7825Smh27603  */
2745cff7825Smh27603 #define	PPMD_LOCK_ONE		0x1
2755cff7825Smh27603 #define	PPMD_LOCK_ALL		0x4
2765cff7825Smh27603 #define	PPMD_PCI33MHZ		0x1000	/* 33mhz PCI slot */
2775cff7825Smh27603 #define	PPMD_PCI66MHZ		0x2000	/* 66mhz PCI slot */
2785cff7825Smh27603 #define	PPMD_INITCHILD_CLKON	0x4000	/* clk turned on in init_child */
2795cff7825Smh27603 #define	PPMD_OFFLINE		0x10000	/* domain is not functional */
2805cff7825Smh27603 #define	PPMD_CPU_READY		0x20000	/* CPU domain can process power call */
2815cff7825Smh27603 
2825cff7825Smh27603 struct ppm_domit {
2835cff7825Smh27603 	char	*name;
2845cff7825Smh27603 	int	model;
2855cff7825Smh27603 	int	dflags;
2865cff7825Smh27603 	int	status;
2875cff7825Smh27603 };
2885cff7825Smh27603 extern struct ppm_domit ppm_domit_data[];
2895cff7825Smh27603 
2905cff7825Smh27603 /*
2915cff7825Smh27603  * XXppm driver-specific routines called from common code (s10)
2925cff7825Smh27603  */
2935cff7825Smh27603 struct ppm_funcs {
2945cff7825Smh27603 	void	(*dev_init)(ppm_dev_t *);
2955cff7825Smh27603 	void	(*dev_fini)(ppm_dev_t *);
2965cff7825Smh27603 	void	(*iocset)(uint8_t);
2975cff7825Smh27603 	uint8_t	(*iocget)(void);
2985cff7825Smh27603 };
2995cff7825Smh27603 
3005cff7825Smh27603 extern ppm_domain_t	*ppm_domain_p;
3015cff7825Smh27603 extern void		*ppm_statep;
3025cff7825Smh27603 extern int		ppm_inst;
3035cff7825Smh27603 extern ppm_domain_t *ppm_domains[];	/* (s10) */
3045cff7825Smh27603 extern struct ppm_funcs ppmf;		/* (s10) */
3055cff7825Smh27603 
3065cff7825Smh27603 extern void		ppm_dev_init(ppm_dev_t *);
3075cff7825Smh27603 extern void		ppm_dev_fini(ppm_dev_t *);
3085cff7825Smh27603 extern int		ppm_create_db(dev_info_t *);
3095cff7825Smh27603 extern int		ppm_claim_dev(dev_info_t *);
3105cff7825Smh27603 extern void		ppm_rem_dev(dev_info_t *);
3115cff7825Smh27603 extern ppm_dev_t	*ppm_get_dev(dev_info_t *, ppm_domain_t *);
3125cff7825Smh27603 extern void		ppm_init_cb(dev_info_t *);
3135cff7825Smh27603 extern int		ppm_init_lyr(ppm_dc_t *, dev_info_t *);
3145cff7825Smh27603 extern ppm_domain_t	*ppm_lookup_dev(dev_info_t *);
3155cff7825Smh27603 extern ppm_domain_t	*ppm_lookup_domain(char *);
3165cff7825Smh27603 extern ppm_dc_t		*ppm_lookup_dc(ppm_domain_t *, int);
3175cff7825Smh27603 extern ppm_dc_t		*ppm_lookup_hndl(int, ppm_dc_t *);
3185cff7825Smh27603 extern ppm_domain_t	*ppm_get_domain_by_dev(const char *);
3195cff7825Smh27603 extern boolean_t	ppm_none_else_holds_power(ppm_domain_t *);
3205cff7825Smh27603 extern ppm_owned_t	*ppm_add_owned(dev_info_t *, ppm_domain_t *);
3215cff7825Smh27603 extern void		ppm_lock_one(ppm_dev_t *, power_req_t *, int *);
3225cff7825Smh27603 extern void		ppm_lock_all(ppm_domain_t *, power_req_t *, int *);
3235cff7825Smh27603 extern boolean_t	ppm_manage_early_cpus(dev_info_t *, int, int *);
3245cff7825Smh27603 extern int		ppm_change_cpu_power(ppm_dev_t *, int);
3255cff7825Smh27603 extern int		ppm_revert_cpu_power(ppm_dev_t *, int);
3265cff7825Smh27603 extern ppm_dev_t	*ppm_add_dev(dev_info_t *, ppm_domain_t *);
3275cff7825Smh27603 
3285cff7825Smh27603 #define	PPM_GET_PRIVATE(dip) \
3295cff7825Smh27603     DEVI(dip)->devi_pm_ppm_private
3305cff7825Smh27603 #define	PPM_SET_PRIVATE(dip, datap) \
3315cff7825Smh27603     DEVI(dip)->devi_pm_ppm_private = datap
3325cff7825Smh27603 
3335cff7825Smh27603 #define	PPM_LOCK_DOMAIN(domp) {			\
3345cff7825Smh27603 	if (!MUTEX_HELD(&(domp)->lock))		\
3355cff7825Smh27603 		mutex_enter(&(domp)->lock);	\
3365cff7825Smh27603 	(domp)->refcnt++;			\
3375cff7825Smh27603 }
3385cff7825Smh27603 
3395cff7825Smh27603 #define	PPM_UNLOCK_DOMAIN(domp) {		\
3405cff7825Smh27603 	ASSERT(MUTEX_HELD(&(domp)->lock) &&	\
3415cff7825Smh27603 		(domp)->refcnt > 0);		\
3425cff7825Smh27603 	if (--(domp)->refcnt == 0)		\
3435cff7825Smh27603 		mutex_exit(&(domp)->lock);	\
3445cff7825Smh27603 }
3455cff7825Smh27603 
3465cff7825Smh27603 /*
3475cff7825Smh27603  * debug support
3485cff7825Smh27603  */
3495cff7825Smh27603 #ifdef DEBUG
3505cff7825Smh27603 #include <sys/promif.h>
3515cff7825Smh27603 
3525cff7825Smh27603 extern char	*ppm_get_ctlstr(int, uint_t);
3535cff7825Smh27603 extern void	ppm_print_dc(struct ppm_dc *);
3545cff7825Smh27603 
3555cff7825Smh27603 extern uint_t ppm_debug;
3565cff7825Smh27603 
3575cff7825Smh27603 #define	D_CREATEDB	0x00000001
3585cff7825Smh27603 #define	D_CLAIMDEV	0x00000002
3595cff7825Smh27603 #define	D_ADDDEV	0x00000004
3605cff7825Smh27603 #define	D_REMDEV	0x00000008
3615cff7825Smh27603 #define	D_LOWEST	0x00000010
3625cff7825Smh27603 #define	D_SETLVL	0x00000020
3635cff7825Smh27603 #define	D_GPIO		0x00000040
3645cff7825Smh27603 #define	D_CPU		0x00000080
3655cff7825Smh27603 #define	D_FET		0x00000100
3665cff7825Smh27603 #define	D_PCIUPA	0x00000200
3675cff7825Smh27603 #define	D_1394		0x00000400
3685cff7825Smh27603 #define	D_CTLOPS1	0x00000800
3695cff7825Smh27603 #define	D_CTLOPS2	0x00001000
3705cff7825Smh27603 #define	D_SOME		0x00002000
3715cff7825Smh27603 #define	D_LOCKS		0x00004000
3725cff7825Smh27603 #define	D_IOCTL		0x00008000
3735cff7825Smh27603 #define	D_ATTACH	0x00010000
3745cff7825Smh27603 #define	D_DETACH	0x00020000
3755cff7825Smh27603 #define	D_OPEN		0x00040000
3765cff7825Smh27603 #define	D_CLOSE		0x00080000
3775cff7825Smh27603 #define	D_INIT		0x00100000
3785cff7825Smh27603 #define	D_FINI		0x00200000
3795cff7825Smh27603 #define	D_ERROR		0x00400000
3805cff7825Smh27603 #define	D_SETPWR	0x00800000
3815cff7825Smh27603 #define	D_LED		0x01000000
3825cff7825Smh27603 #define	D_PCI		0x02000000
3835cff7825Smh27603 #define	D_PPMDC		0x04000000
3845cff7825Smh27603 #define	D_CPR		0x08000000
3855cff7825Smh27603 
3865cff7825Smh27603 #define	PPMD(level, arglist) {			\
3875cff7825Smh27603 	if (ppm_debug & (level)) {		\
3885cff7825Smh27603 		pm_log arglist;			\
3895cff7825Smh27603 	}					\
3905cff7825Smh27603 }
3915cff7825Smh27603 /* (s10) */
3925cff7825Smh27603 #define	DPRINTF		PPMD
3935cff7825Smh27603 
3945cff7825Smh27603 #else	/* DEBUG */
3955cff7825Smh27603 #define	PPMD(level, arglist)
3965cff7825Smh27603 #define	DPRINTF(flag, args)	/* (s10) */
3975cff7825Smh27603 #endif	/* DEBUG */
3985cff7825Smh27603 
3995cff7825Smh27603 #ifdef	__cplusplus
4005cff7825Smh27603 }
4015cff7825Smh27603 #endif
4025cff7825Smh27603 
4035cff7825Smh27603 #endif	/* _SYS_PPMVAR_H */
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