xref: /titanic_53/usr/src/uts/common/sys/cmt.h (revision 0e7515250c8395f368aa45fb9acae7c4f8f8b786)
1fb2f18f8Sesaxe /*
2fb2f18f8Sesaxe  * CDDL HEADER START
3fb2f18f8Sesaxe  *
4fb2f18f8Sesaxe  * The contents of this file are subject to the terms of the
5fb2f18f8Sesaxe  * Common Development and Distribution License (the "License").
6fb2f18f8Sesaxe  * You may not use this file except in compliance with the License.
7fb2f18f8Sesaxe  *
8fb2f18f8Sesaxe  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9fb2f18f8Sesaxe  * or http://www.opensolaris.org/os/licensing.
10fb2f18f8Sesaxe  * See the License for the specific language governing permissions
11fb2f18f8Sesaxe  * and limitations under the License.
12fb2f18f8Sesaxe  *
13fb2f18f8Sesaxe  * When distributing Covered Code, include this CDDL HEADER in each
14fb2f18f8Sesaxe  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15fb2f18f8Sesaxe  * If applicable, add the following below this CDDL HEADER, with the
16fb2f18f8Sesaxe  * fields enclosed by brackets "[]" replaced with your own identifying
17fb2f18f8Sesaxe  * information: Portions Copyright [yyyy] [name of copyright owner]
18fb2f18f8Sesaxe  *
19fb2f18f8Sesaxe  * CDDL HEADER END
20fb2f18f8Sesaxe  */
21fb2f18f8Sesaxe /*
22*0e751525SEric Saxe  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23fb2f18f8Sesaxe  * Use is subject to license terms.
24fb2f18f8Sesaxe  */
25fb2f18f8Sesaxe 
26fb2f18f8Sesaxe #ifndef	_CMT_H
27fb2f18f8Sesaxe #define	_CMT_H
28fb2f18f8Sesaxe 
29fb2f18f8Sesaxe /*
30fb2f18f8Sesaxe  * CMT PG class
31fb2f18f8Sesaxe  */
32fb2f18f8Sesaxe 
33fb2f18f8Sesaxe #ifdef	__cplusplus
34fb2f18f8Sesaxe extern "C" {
35fb2f18f8Sesaxe #endif
36fb2f18f8Sesaxe 
37fb2f18f8Sesaxe #if (defined(_KERNEL) || defined(_KMEMUSER))
38fb2f18f8Sesaxe #include <sys/group.h>
39fb2f18f8Sesaxe #include <sys/pghw.h>
40*0e751525SEric Saxe #include <sys/lgrp.h>
41fb2f18f8Sesaxe #include <sys/types.h>
42fb2f18f8Sesaxe 
43fb2f18f8Sesaxe /*
44*0e751525SEric Saxe  * CMT related dispatcher policies
45*0e751525SEric Saxe  */
46*0e751525SEric Saxe #define	CMT_NO_POLICY	0x0
47*0e751525SEric Saxe #define	CMT_BALANCE	0x1
48*0e751525SEric Saxe #define	CMT_COALESCE	0x2
49*0e751525SEric Saxe #define	CMT_AFFINITY	0x4
50*0e751525SEric Saxe 
51*0e751525SEric Saxe typedef uint_t pg_cmt_policy_t;
52*0e751525SEric Saxe 
53*0e751525SEric Saxe /*
54fb2f18f8Sesaxe  * CMT pg structure
55fb2f18f8Sesaxe  */
56fb2f18f8Sesaxe typedef struct pg_cmt {
57fb2f18f8Sesaxe 	struct pghw	cmt_pg;			/* physical grouping */
58fb2f18f8Sesaxe 	struct group	*cmt_siblings;		/* CMT PGs to balance with */
59fb2f18f8Sesaxe 	struct pg_cmt	*cmt_parent;		/* Parent CMT PG */
60fb2f18f8Sesaxe 	struct group	*cmt_children;		/* Active children CMT PGs */
61*0e751525SEric Saxe 	pg_cmt_policy_t	cmt_policy;		/* Dispatcher policies to use */
62*0e751525SEric Saxe 	uint32_t	cmt_utilization;	/* Group's utilization */
63fb2f18f8Sesaxe 	int		cmt_nchildren;		/* # of children CMT PGs */
64*0e751525SEric Saxe 	int		cmt_hint;		/* hint for balancing */
65fb2f18f8Sesaxe 	struct group	cmt_cpus_actv;
666890d023SEric Saxe 	struct bitset	cmt_cpus_actv_set;	/* bitset of active CPUs */
67fb2f18f8Sesaxe } pg_cmt_t;
68fb2f18f8Sesaxe 
69fb2f18f8Sesaxe /*
70*0e751525SEric Saxe  * CMT lgroup structure
71*0e751525SEric Saxe  */
72*0e751525SEric Saxe typedef struct cmt_lgrp {
73*0e751525SEric Saxe 	group_t		cl_pgs;		/* Top level group of active CMT PGs */
74*0e751525SEric Saxe 	int		cl_npgs;	/* # of top level PGs in the lgroup */
75*0e751525SEric Saxe 	lgrp_handle_t	cl_hand;	/* lgroup's platform handle */
76*0e751525SEric Saxe 	struct cmt_lgrp	*cl_next;	/* next cmt_lgrp */
77*0e751525SEric Saxe } cmt_lgrp_t;
78*0e751525SEric Saxe 
79*0e751525SEric Saxe /*
80fb2f18f8Sesaxe  * Change the number of running threads on the pg
81fb2f18f8Sesaxe  */
82fb2f18f8Sesaxe #define	PG_NRUN_UPDATE(cp, n)		(pg_cmt_load((cp), (n)))
83fb2f18f8Sesaxe 
84*0e751525SEric Saxe /*
85*0e751525SEric Saxe  * Indicate that the given logical CPU is (or isn't) currently utilized
86*0e751525SEric Saxe  */
87*0e751525SEric Saxe #define	CMT_CPU_UTILIZED(cp)		(pg_cmt_load((cp), 1))
88*0e751525SEric Saxe #define	CMT_CPU_NOT_UTILIZED(cp)	(pg_cmt_load((cp), -1))
89*0e751525SEric Saxe 
90*0e751525SEric Saxe /*
91*0e751525SEric Saxe  * CMT PG's capacity
92*0e751525SEric Saxe  *
93*0e751525SEric Saxe  * Currently, this is defined to be the number of active
94*0e751525SEric Saxe  * logical CPUs in the group.
95*0e751525SEric Saxe  *
96*0e751525SEric Saxe  * This will be used in conjunction with the utilization, which is defined
97*0e751525SEric Saxe  * to be the number of threads actively running on CPUs in the group.
98*0e751525SEric Saxe  */
99*0e751525SEric Saxe #define	CMT_CAPACITY(pg)	(GROUP_SIZE(&((pg_cmt_t *)pg)->cmt_cpus_actv))
100*0e751525SEric Saxe 
101fb2f18f8Sesaxe void		pg_cmt_load(cpu_t *, int);
102fb2f18f8Sesaxe void		pg_cmt_cpu_startup(cpu_t *);
103fb2f18f8Sesaxe int		pg_cmt_can_migrate(cpu_t *, cpu_t *);
104fb2f18f8Sesaxe 
105*0e751525SEric Saxe /*
106*0e751525SEric Saxe  * CMT platform interfaces
107*0e751525SEric Saxe  */
108*0e751525SEric Saxe pg_cmt_policy_t	pg_plat_cmt_policy(pghw_type_t);
109*0e751525SEric Saxe int		pg_plat_cmt_rank(pg_cmt_t *, pg_cmt_t *);
110d129bde2Sesaxe 
111*0e751525SEric Saxe /*
112*0e751525SEric Saxe  * CMT dispatcher policy
113*0e751525SEric Saxe  */
1146890d023SEric Saxe cpu_t		*cmt_balance(kthread_t *, cpu_t *);
1156890d023SEric Saxe 
116*0e751525SEric Saxe /*
117*0e751525SEric Saxe  * Power Aware Dispatcher Interfaces
118*0e751525SEric Saxe  */
119*0e751525SEric Saxe int		cmt_pad_enable(pghw_type_t);
120*0e751525SEric Saxe int		cmt_pad_disable(pghw_type_t);
121*0e751525SEric Saxe 
122fb2f18f8Sesaxe #endif	/* !_KERNEL && !_KMEMUSER */
123fb2f18f8Sesaxe 
124fb2f18f8Sesaxe #ifdef	__cplusplus
125fb2f18f8Sesaxe }
126fb2f18f8Sesaxe #endif
127fb2f18f8Sesaxe 
128fb2f18f8Sesaxe #endif /* _CMT_H */
129