xref: /titanic_53/usr/src/uts/common/io/cpudrv.c (revision 5cff782560a1c3cf913ba5574a5123a299f3315e)
1*5cff7825Smh27603 /*
2*5cff7825Smh27603  * CDDL HEADER START
3*5cff7825Smh27603  *
4*5cff7825Smh27603  * The contents of this file are subject to the terms of the
5*5cff7825Smh27603  * Common Development and Distribution License (the "License").
6*5cff7825Smh27603  * You may not use this file except in compliance with the License.
7*5cff7825Smh27603  *
8*5cff7825Smh27603  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*5cff7825Smh27603  * or http://www.opensolaris.org/os/licensing.
10*5cff7825Smh27603  * See the License for the specific language governing permissions
11*5cff7825Smh27603  * and limitations under the License.
12*5cff7825Smh27603  *
13*5cff7825Smh27603  * When distributing Covered Code, include this CDDL HEADER in each
14*5cff7825Smh27603  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*5cff7825Smh27603  * If applicable, add the following below this CDDL HEADER, with the
16*5cff7825Smh27603  * fields enclosed by brackets "[]" replaced with your own identifying
17*5cff7825Smh27603  * information: Portions Copyright [yyyy] [name of copyright owner]
18*5cff7825Smh27603  *
19*5cff7825Smh27603  * CDDL HEADER END
20*5cff7825Smh27603  */
21*5cff7825Smh27603 /*
22*5cff7825Smh27603  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23*5cff7825Smh27603  * Use is subject to license terms.
24*5cff7825Smh27603  */
25*5cff7825Smh27603 
26*5cff7825Smh27603 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27*5cff7825Smh27603 
28*5cff7825Smh27603 /*
29*5cff7825Smh27603  * CPU Device driver. The driver is not DDI-compliant.
30*5cff7825Smh27603  *
31*5cff7825Smh27603  * The driver supports following features:
32*5cff7825Smh27603  *	- Power management.
33*5cff7825Smh27603  */
34*5cff7825Smh27603 
35*5cff7825Smh27603 #include <sys/types.h>
36*5cff7825Smh27603 #include <sys/param.h>
37*5cff7825Smh27603 #include <sys/errno.h>
38*5cff7825Smh27603 #include <sys/modctl.h>
39*5cff7825Smh27603 #include <sys/kmem.h>
40*5cff7825Smh27603 #include <sys/conf.h>
41*5cff7825Smh27603 #include <sys/cmn_err.h>
42*5cff7825Smh27603 #include <sys/stat.h>
43*5cff7825Smh27603 #include <sys/debug.h>
44*5cff7825Smh27603 #include <sys/systm.h>
45*5cff7825Smh27603 #include <sys/ddi.h>
46*5cff7825Smh27603 #include <sys/sunddi.h>
47*5cff7825Smh27603 
48*5cff7825Smh27603 #include <sys/machsystm.h>
49*5cff7825Smh27603 #include <sys/x_call.h>
50*5cff7825Smh27603 #include <sys/cpudrv.h>
51*5cff7825Smh27603 #include <sys/cpudrv_plat.h>
52*5cff7825Smh27603 #include <sys/msacct.h>
53*5cff7825Smh27603 
54*5cff7825Smh27603 /*
55*5cff7825Smh27603  * CPU power management
56*5cff7825Smh27603  *
57*5cff7825Smh27603  * The supported power saving model is to slow down the CPU (on SPARC by
58*5cff7825Smh27603  * dividing the CPU clock and on x86 by dropping down a P-state).
59*5cff7825Smh27603  * Periodically we determine the amount of time the CPU is running
60*5cff7825Smh27603  * idle thread and threads in user mode during the last quantum.  If the idle
61*5cff7825Smh27603  * thread was running less than its low water mark for current speed for
62*5cff7825Smh27603  * number of consecutive sampling periods, or number of running threads in
63*5cff7825Smh27603  * user mode are above its high water mark, we arrange to go to the higher
64*5cff7825Smh27603  * speed.  If the idle thread was running more than its high water mark without
65*5cff7825Smh27603  * dropping a number of consecutive times below the mark, and number of threads
66*5cff7825Smh27603  * running in user mode are below its low water mark, we arrange to go to the
67*5cff7825Smh27603  * next lower speed.  While going down, we go through all the speeds.  While
68*5cff7825Smh27603  * going up we go to the maximum speed to minimize impact on the user, but have
69*5cff7825Smh27603  * provisions in the driver to go to other speeds.
70*5cff7825Smh27603  *
71*5cff7825Smh27603  * The driver does not have knowledge of a particular implementation of this
72*5cff7825Smh27603  * scheme and will work with all CPUs supporting this model. On SPARC, the
73*5cff7825Smh27603  * driver determines supported speeds by looking at 'clock-divisors' property
74*5cff7825Smh27603  * created by OBP. On x86, the driver retrieves the supported speeds from
75*5cff7825Smh27603  * ACPI.
76*5cff7825Smh27603  */
77*5cff7825Smh27603 
78*5cff7825Smh27603 /*
79*5cff7825Smh27603  * Configuration function prototypes and data structures
80*5cff7825Smh27603  */
81*5cff7825Smh27603 static int cpudrv_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
82*5cff7825Smh27603 static int cpudrv_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
83*5cff7825Smh27603 static int cpudrv_power(dev_info_t *dip, int comp, int level);
84*5cff7825Smh27603 
85*5cff7825Smh27603 struct dev_ops cpudrv_ops = {
86*5cff7825Smh27603 	DEVO_REV,		/* rev */
87*5cff7825Smh27603 	0,			/* refcnt */
88*5cff7825Smh27603 	nodev,			/* getinfo */
89*5cff7825Smh27603 	nulldev,		/* identify */
90*5cff7825Smh27603 	nulldev,		/* probe */
91*5cff7825Smh27603 	cpudrv_attach,		/* attach */
92*5cff7825Smh27603 	cpudrv_detach,		/* detach */
93*5cff7825Smh27603 	nodev,			/* reset */
94*5cff7825Smh27603 	(struct cb_ops *)NULL,	/* cb_ops */
95*5cff7825Smh27603 	(struct bus_ops *)NULL,	/* bus_ops */
96*5cff7825Smh27603 	cpudrv_power		/* power */
97*5cff7825Smh27603 };
98*5cff7825Smh27603 
99*5cff7825Smh27603 static struct modldrv modldrv = {
100*5cff7825Smh27603 	&mod_driverops,			/* modops */
101*5cff7825Smh27603 	"CPU Driver %I%",		/* linkinfo */
102*5cff7825Smh27603 	&cpudrv_ops,			/* dev_ops */
103*5cff7825Smh27603 };
104*5cff7825Smh27603 
105*5cff7825Smh27603 static struct modlinkage modlinkage = {
106*5cff7825Smh27603 	MODREV_1,		/* rev */
107*5cff7825Smh27603 	&modldrv,		/* linkage */
108*5cff7825Smh27603 	NULL
109*5cff7825Smh27603 };
110*5cff7825Smh27603 
111*5cff7825Smh27603 /*
112*5cff7825Smh27603  * Function prototypes
113*5cff7825Smh27603  */
114*5cff7825Smh27603 static int cpudrv_pm_init(cpudrv_devstate_t *cpudsp);
115*5cff7825Smh27603 static void cpudrv_pm_free(cpudrv_devstate_t *cpudsp);
116*5cff7825Smh27603 static int cpudrv_pm_comp_create(cpudrv_devstate_t *cpudsp);
117*5cff7825Smh27603 static void cpudrv_pm_monitor_disp(void *arg);
118*5cff7825Smh27603 static void cpudrv_pm_monitor(void *arg);
119*5cff7825Smh27603 
120*5cff7825Smh27603 /*
121*5cff7825Smh27603  * Driver global variables
122*5cff7825Smh27603  */
123*5cff7825Smh27603 uint_t cpudrv_debug = 0;
124*5cff7825Smh27603 void *cpudrv_state;
125*5cff7825Smh27603 static uint_t cpudrv_pm_idle_hwm = CPUDRV_PM_IDLE_HWM;
126*5cff7825Smh27603 static uint_t cpudrv_pm_idle_lwm = CPUDRV_PM_IDLE_LWM;
127*5cff7825Smh27603 static uint_t cpudrv_pm_idle_buf_zone = CPUDRV_PM_IDLE_BUF_ZONE;
128*5cff7825Smh27603 static uint_t cpudrv_pm_idle_bhwm_cnt_max = CPUDRV_PM_IDLE_BHWM_CNT_MAX;
129*5cff7825Smh27603 static uint_t cpudrv_pm_idle_blwm_cnt_max = CPUDRV_PM_IDLE_BLWM_CNT_MAX;
130*5cff7825Smh27603 static uint_t cpudrv_pm_user_hwm = CPUDRV_PM_USER_HWM;
131*5cff7825Smh27603 
132*5cff7825Smh27603 /*
133*5cff7825Smh27603  * cpudrv_direct_pm allows user applications to directly control the
134*5cff7825Smh27603  * power state transitions (direct pm) without following the normal
135*5cff7825Smh27603  * direct pm protocol. This is needed because the normal protocol
136*5cff7825Smh27603  * requires that a device only be lowered when it is idle, and be
137*5cff7825Smh27603  * brought up when it request to do so by calling pm_raise_power().
138*5cff7825Smh27603  * Ignoring this protocol is harmless for CPU (other than speed).
139*5cff7825Smh27603  * Moreover it might be the case that CPU is never idle or wants
140*5cff7825Smh27603  * to be at higher speed because of the addition CPU cycles required
141*5cff7825Smh27603  * to run the user application.
142*5cff7825Smh27603  *
143*5cff7825Smh27603  * The driver will still report idle/busy status to the framework. Although
144*5cff7825Smh27603  * framework will ignore this information for direct pm devices and not
145*5cff7825Smh27603  * try to bring them down when idle, user applications can still use this
146*5cff7825Smh27603  * information if they wants.
147*5cff7825Smh27603  *
148*5cff7825Smh27603  * In the future, provide an ioctl to control setting of this mode. In
149*5cff7825Smh27603  * that case, this variable should move to the state structure and
150*5cff7825Smh27603  * be protected by the lock in the state structure.
151*5cff7825Smh27603  */
152*5cff7825Smh27603 int cpudrv_direct_pm = 0;
153*5cff7825Smh27603 
154*5cff7825Smh27603 /*
155*5cff7825Smh27603  * Arranges for the handler function to be called at the interval suitable
156*5cff7825Smh27603  * for current speed.
157*5cff7825Smh27603  */
158*5cff7825Smh27603 #define	CPUDRV_PM_MONITOR_INIT(cpudsp) { \
159*5cff7825Smh27603 	ASSERT(mutex_owned(&(cpudsp)->lock)); \
160*5cff7825Smh27603 	(cpudsp)->cpudrv_pm.timeout_id = timeout(cpudrv_pm_monitor_disp, \
161*5cff7825Smh27603 	    (cpudsp), (((cpudsp)->cpudrv_pm.cur_spd == NULL) ? \
162*5cff7825Smh27603 	    CPUDRV_PM_QUANT_CNT_OTHR : \
163*5cff7825Smh27603 	    (cpudsp)->cpudrv_pm.cur_spd->quant_cnt)); \
164*5cff7825Smh27603 }
165*5cff7825Smh27603 
166*5cff7825Smh27603 /*
167*5cff7825Smh27603  * Arranges for the handler function not to be called back.
168*5cff7825Smh27603  */
169*5cff7825Smh27603 #define	CPUDRV_PM_MONITOR_FINI(cpudsp) { \
170*5cff7825Smh27603 	timeout_id_t tmp_tid; \
171*5cff7825Smh27603 	ASSERT(mutex_owned(&(cpudsp)->lock)); \
172*5cff7825Smh27603 	ASSERT((cpudsp)->cpudrv_pm.timeout_id); \
173*5cff7825Smh27603 	tmp_tid = (cpudsp)->cpudrv_pm.timeout_id; \
174*5cff7825Smh27603 	(cpudsp)->cpudrv_pm.timeout_id = 0; \
175*5cff7825Smh27603 	mutex_exit(&(cpudsp)->lock); \
176*5cff7825Smh27603 	(void) untimeout(tmp_tid); \
177*5cff7825Smh27603 	mutex_enter(&(cpudsp)->cpudrv_pm.timeout_lock); \
178*5cff7825Smh27603 	while ((cpudsp)->cpudrv_pm.timeout_count != 0) \
179*5cff7825Smh27603 		cv_wait(&(cpudsp)->cpudrv_pm.timeout_cv, \
180*5cff7825Smh27603 		    &(cpudsp)->cpudrv_pm.timeout_lock); \
181*5cff7825Smh27603 	mutex_exit(&(cpudsp)->cpudrv_pm.timeout_lock); \
182*5cff7825Smh27603 	mutex_enter(&(cpudsp)->lock); \
183*5cff7825Smh27603 }
184*5cff7825Smh27603 
185*5cff7825Smh27603 int
186*5cff7825Smh27603 _init(void)
187*5cff7825Smh27603 {
188*5cff7825Smh27603 	int	error;
189*5cff7825Smh27603 
190*5cff7825Smh27603 	DPRINTF(D_INIT, (" _init: function called\n"));
191*5cff7825Smh27603 	if ((error = ddi_soft_state_init(&cpudrv_state,
192*5cff7825Smh27603 	    sizeof (cpudrv_devstate_t), 0)) != 0) {
193*5cff7825Smh27603 		return (error);
194*5cff7825Smh27603 	}
195*5cff7825Smh27603 
196*5cff7825Smh27603 	if ((error = mod_install(&modlinkage)) != 0)  {
197*5cff7825Smh27603 		ddi_soft_state_fini(&cpudrv_state);
198*5cff7825Smh27603 	}
199*5cff7825Smh27603 
200*5cff7825Smh27603 	/*
201*5cff7825Smh27603 	 * Callbacks used by the PPM driver.
202*5cff7825Smh27603 	 */
203*5cff7825Smh27603 	CPUDRV_PM_SET_PPM_CALLBACKS();
204*5cff7825Smh27603 	return (error);
205*5cff7825Smh27603 }
206*5cff7825Smh27603 
207*5cff7825Smh27603 int
208*5cff7825Smh27603 _fini(void)
209*5cff7825Smh27603 {
210*5cff7825Smh27603 	int	error;
211*5cff7825Smh27603 
212*5cff7825Smh27603 	DPRINTF(D_FINI, (" _fini: function called\n"));
213*5cff7825Smh27603 	if ((error = mod_remove(&modlinkage)) == 0) {
214*5cff7825Smh27603 		ddi_soft_state_fini(&cpudrv_state);
215*5cff7825Smh27603 	}
216*5cff7825Smh27603 
217*5cff7825Smh27603 	return (error);
218*5cff7825Smh27603 }
219*5cff7825Smh27603 
220*5cff7825Smh27603 int
221*5cff7825Smh27603 _info(struct modinfo *modinfop)
222*5cff7825Smh27603 {
223*5cff7825Smh27603 	return (mod_info(&modlinkage, modinfop));
224*5cff7825Smh27603 }
225*5cff7825Smh27603 
226*5cff7825Smh27603 /*
227*5cff7825Smh27603  * Driver attach(9e) entry point.
228*5cff7825Smh27603  */
229*5cff7825Smh27603 static int
230*5cff7825Smh27603 cpudrv_attach(dev_info_t *dip, ddi_attach_cmd_t cmd)
231*5cff7825Smh27603 {
232*5cff7825Smh27603 	int			instance;
233*5cff7825Smh27603 	cpudrv_devstate_t	*cpudsp;
234*5cff7825Smh27603 	extern pri_t		maxclsyspri;
235*5cff7825Smh27603 
236*5cff7825Smh27603 	instance = ddi_get_instance(dip);
237*5cff7825Smh27603 
238*5cff7825Smh27603 	switch (cmd) {
239*5cff7825Smh27603 	case DDI_ATTACH:
240*5cff7825Smh27603 		DPRINTF(D_ATTACH, ("cpudrv_attach: instance %d: "
241*5cff7825Smh27603 		    "DDI_ATTACH called\n", instance));
242*5cff7825Smh27603 		if (ddi_soft_state_zalloc(cpudrv_state, instance) !=
243*5cff7825Smh27603 		    DDI_SUCCESS) {
244*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_attach: instance %d: "
245*5cff7825Smh27603 			    "can't allocate state", instance);
246*5cff7825Smh27603 			CPUDRV_PM_DISABLE();
247*5cff7825Smh27603 			return (DDI_FAILURE);
248*5cff7825Smh27603 		}
249*5cff7825Smh27603 		if ((cpudsp = ddi_get_soft_state(cpudrv_state, instance)) ==
250*5cff7825Smh27603 		    NULL) {
251*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_attach: instance %d: "
252*5cff7825Smh27603 			    "can't get state", instance);
253*5cff7825Smh27603 			ddi_soft_state_free(cpudrv_state, instance);
254*5cff7825Smh27603 			CPUDRV_PM_DISABLE();
255*5cff7825Smh27603 			return (DDI_FAILURE);
256*5cff7825Smh27603 		}
257*5cff7825Smh27603 		cpudsp->dip = dip;
258*5cff7825Smh27603 
259*5cff7825Smh27603 		/*
260*5cff7825Smh27603 		 * Find CPU number for this dev_info node.
261*5cff7825Smh27603 		 */
262*5cff7825Smh27603 		if (!cpudrv_pm_get_cpu_id(dip, &(cpudsp->cpu_id))) {
263*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_attach: instance %d: "
264*5cff7825Smh27603 			    "can't convert dip to cpu_id", instance);
265*5cff7825Smh27603 			ddi_soft_state_free(cpudrv_state, instance);
266*5cff7825Smh27603 			CPUDRV_PM_DISABLE();
267*5cff7825Smh27603 			return (DDI_FAILURE);
268*5cff7825Smh27603 		}
269*5cff7825Smh27603 		if (cpudrv_pm_init(cpudsp) != DDI_SUCCESS) {
270*5cff7825Smh27603 			ddi_soft_state_free(cpudrv_state, instance);
271*5cff7825Smh27603 			CPUDRV_PM_DISABLE();
272*5cff7825Smh27603 			return (DDI_FAILURE);
273*5cff7825Smh27603 		}
274*5cff7825Smh27603 		if (cpudrv_pm_comp_create(cpudsp) != DDI_SUCCESS) {
275*5cff7825Smh27603 			ddi_soft_state_free(cpudrv_state, instance);
276*5cff7825Smh27603 			CPUDRV_PM_DISABLE();
277*5cff7825Smh27603 			cpudrv_pm_free(cpudsp);
278*5cff7825Smh27603 			return (DDI_FAILURE);
279*5cff7825Smh27603 		}
280*5cff7825Smh27603 		if (ddi_prop_update_string(DDI_DEV_T_NONE,
281*5cff7825Smh27603 		    dip, "pm-class", "CPU") != DDI_PROP_SUCCESS) {
282*5cff7825Smh27603 			ddi_soft_state_free(cpudrv_state, instance);
283*5cff7825Smh27603 			CPUDRV_PM_DISABLE();
284*5cff7825Smh27603 			cpudrv_pm_free(cpudsp);
285*5cff7825Smh27603 			return (DDI_FAILURE);
286*5cff7825Smh27603 		}
287*5cff7825Smh27603 
288*5cff7825Smh27603 		/*
289*5cff7825Smh27603 		 * Taskq is used to dispatch routine to monitor CPU activities.
290*5cff7825Smh27603 		 */
291*5cff7825Smh27603 		cpudsp->cpudrv_pm.tq = taskq_create_instance(
292*5cff7825Smh27603 		    "cpudrv_pm_monitor",
293*5cff7825Smh27603 		    ddi_get_instance(dip), CPUDRV_PM_TASKQ_THREADS,
294*5cff7825Smh27603 		    (maxclsyspri - 1), CPUDRV_PM_TASKQ_MIN,
295*5cff7825Smh27603 		    CPUDRV_PM_TASKQ_MAX, TASKQ_PREPOPULATE|TASKQ_CPR_SAFE);
296*5cff7825Smh27603 
297*5cff7825Smh27603 		mutex_init(&cpudsp->lock, NULL, MUTEX_DRIVER, NULL);
298*5cff7825Smh27603 		mutex_init(&cpudsp->cpudrv_pm.timeout_lock, NULL, MUTEX_DRIVER,
299*5cff7825Smh27603 		    NULL);
300*5cff7825Smh27603 		cv_init(&cpudsp->cpudrv_pm.timeout_cv, NULL, CV_DEFAULT, NULL);
301*5cff7825Smh27603 
302*5cff7825Smh27603 		/*
303*5cff7825Smh27603 		 * Driver needs to assume that CPU is running at unknown speed
304*5cff7825Smh27603 		 * at DDI_ATTACH and switch it to the needed speed. We assume
305*5cff7825Smh27603 		 * that initial needed speed is full speed for us.
306*5cff7825Smh27603 		 */
307*5cff7825Smh27603 		/*
308*5cff7825Smh27603 		 * We need to take the lock because cpudrv_pm_monitor()
309*5cff7825Smh27603 		 * will start running in parallel with attach().
310*5cff7825Smh27603 		 */
311*5cff7825Smh27603 		mutex_enter(&cpudsp->lock);
312*5cff7825Smh27603 		cpudsp->cpudrv_pm.cur_spd = NULL;
313*5cff7825Smh27603 		cpudsp->cpudrv_pm.targ_spd = cpudsp->cpudrv_pm.head_spd;
314*5cff7825Smh27603 		/*
315*5cff7825Smh27603 		 * We don't call pm_raise_power() directly from attach because
316*5cff7825Smh27603 		 * driver attach for a slave CPU node can happen before the
317*5cff7825Smh27603 		 * CPU is even initialized. We just start the monitoring
318*5cff7825Smh27603 		 * system which understands unknown speed and moves CPU
319*5cff7825Smh27603 		 * to targ_spd when it have been initialized.
320*5cff7825Smh27603 		 */
321*5cff7825Smh27603 		CPUDRV_PM_MONITOR_INIT(cpudsp);
322*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
323*5cff7825Smh27603 
324*5cff7825Smh27603 		CPUDRV_PM_INSTALL_TOPSPEED_CHANGE_HANDLER(cpudsp, dip);
325*5cff7825Smh27603 
326*5cff7825Smh27603 		ddi_report_dev(dip);
327*5cff7825Smh27603 		return (DDI_SUCCESS);
328*5cff7825Smh27603 
329*5cff7825Smh27603 	case DDI_RESUME:
330*5cff7825Smh27603 		DPRINTF(D_ATTACH, ("cpudrv_attach: instance %d: "
331*5cff7825Smh27603 		    "DDI_RESUME called\n", instance));
332*5cff7825Smh27603 		if ((cpudsp = ddi_get_soft_state(cpudrv_state, instance)) ==
333*5cff7825Smh27603 		    NULL) {
334*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_attach: instance %d: "
335*5cff7825Smh27603 			    "can't get state", instance);
336*5cff7825Smh27603 			return (DDI_FAILURE);
337*5cff7825Smh27603 		}
338*5cff7825Smh27603 		mutex_enter(&cpudsp->lock);
339*5cff7825Smh27603 		/*
340*5cff7825Smh27603 		 * Driver needs to assume that CPU is running at unknown speed
341*5cff7825Smh27603 		 * at DDI_RESUME and switch it to the needed speed. We assume
342*5cff7825Smh27603 		 * that the needed speed is full speed for us.
343*5cff7825Smh27603 		 */
344*5cff7825Smh27603 		cpudsp->cpudrv_pm.cur_spd = NULL;
345*5cff7825Smh27603 		cpudsp->cpudrv_pm.targ_spd = cpudsp->cpudrv_pm.head_spd;
346*5cff7825Smh27603 		CPUDRV_PM_MONITOR_INIT(cpudsp);
347*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
348*5cff7825Smh27603 		CPUDRV_PM_REDEFINE_TOPSPEED(dip);
349*5cff7825Smh27603 		return (DDI_SUCCESS);
350*5cff7825Smh27603 
351*5cff7825Smh27603 	default:
352*5cff7825Smh27603 		return (DDI_FAILURE);
353*5cff7825Smh27603 	}
354*5cff7825Smh27603 }
355*5cff7825Smh27603 
356*5cff7825Smh27603 /*
357*5cff7825Smh27603  * Driver detach(9e) entry point.
358*5cff7825Smh27603  */
359*5cff7825Smh27603 static int
360*5cff7825Smh27603 cpudrv_detach(dev_info_t *dip, ddi_detach_cmd_t cmd)
361*5cff7825Smh27603 {
362*5cff7825Smh27603 	int			instance;
363*5cff7825Smh27603 	cpudrv_devstate_t	*cpudsp;
364*5cff7825Smh27603 	cpudrv_pm_t		*cpupm;
365*5cff7825Smh27603 
366*5cff7825Smh27603 	instance = ddi_get_instance(dip);
367*5cff7825Smh27603 
368*5cff7825Smh27603 	switch (cmd) {
369*5cff7825Smh27603 	case DDI_DETACH:
370*5cff7825Smh27603 		DPRINTF(D_DETACH, ("cpudrv_detach: instance %d: "
371*5cff7825Smh27603 		    "DDI_DETACH called\n", instance));
372*5cff7825Smh27603 		/*
373*5cff7825Smh27603 		 * If the only thing supported by the driver is power
374*5cff7825Smh27603 		 * management, we can in future enhance the driver and
375*5cff7825Smh27603 		 * framework that loads it to unload the driver when
376*5cff7825Smh27603 		 * user has disabled CPU power management.
377*5cff7825Smh27603 		 */
378*5cff7825Smh27603 		return (DDI_FAILURE);
379*5cff7825Smh27603 
380*5cff7825Smh27603 	case DDI_SUSPEND:
381*5cff7825Smh27603 		DPRINTF(D_DETACH, ("cpudrv_detach: instance %d: "
382*5cff7825Smh27603 		    "DDI_SUSPEND called\n", instance));
383*5cff7825Smh27603 		if ((cpudsp = ddi_get_soft_state(cpudrv_state, instance)) ==
384*5cff7825Smh27603 		    NULL) {
385*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_detach: instance %d: "
386*5cff7825Smh27603 			    "can't get state", instance);
387*5cff7825Smh27603 			return (DDI_FAILURE);
388*5cff7825Smh27603 		}
389*5cff7825Smh27603 		/*
390*5cff7825Smh27603 		 * During a checkpoint-resume sequence, framework will
391*5cff7825Smh27603 		 * stop interrupts to quiesce kernel activity. This will
392*5cff7825Smh27603 		 * leave our monitoring system ineffective. Handle this
393*5cff7825Smh27603 		 * by stopping our monitoring system and bringing CPU
394*5cff7825Smh27603 		 * to full speed. In case we are in special direct pm
395*5cff7825Smh27603 		 * mode, we leave the CPU at whatever speed it is. This
396*5cff7825Smh27603 		 * is harmless other than speed.
397*5cff7825Smh27603 		 */
398*5cff7825Smh27603 		mutex_enter(&cpudsp->lock);
399*5cff7825Smh27603 		cpupm = &(cpudsp->cpudrv_pm);
400*5cff7825Smh27603 
401*5cff7825Smh27603 		DPRINTF(D_DETACH, ("cpudrv_detach: instance %d: DDI_SUSPEND - "
402*5cff7825Smh27603 		    "cur_spd %d, head_spd %d\n", instance,
403*5cff7825Smh27603 		    cpupm->cur_spd->pm_level, cpupm->head_spd->pm_level));
404*5cff7825Smh27603 
405*5cff7825Smh27603 		CPUDRV_PM_MONITOR_FINI(cpudsp);
406*5cff7825Smh27603 
407*5cff7825Smh27603 		if (!cpudrv_direct_pm && (cpupm->cur_spd != cpupm->head_spd)) {
408*5cff7825Smh27603 			if (cpupm->pm_busycnt < 1) {
409*5cff7825Smh27603 				if ((pm_busy_component(dip, CPUDRV_PM_COMP_NUM)
410*5cff7825Smh27603 				    == DDI_SUCCESS)) {
411*5cff7825Smh27603 					cpupm->pm_busycnt++;
412*5cff7825Smh27603 				} else {
413*5cff7825Smh27603 					CPUDRV_PM_MONITOR_INIT(cpudsp);
414*5cff7825Smh27603 					mutex_exit(&cpudsp->lock);
415*5cff7825Smh27603 					cmn_err(CE_WARN, "cpudrv_detach: "
416*5cff7825Smh27603 					    "instance %d: can't busy CPU "
417*5cff7825Smh27603 					    "component", instance);
418*5cff7825Smh27603 					return (DDI_FAILURE);
419*5cff7825Smh27603 				}
420*5cff7825Smh27603 			}
421*5cff7825Smh27603 			mutex_exit(&cpudsp->lock);
422*5cff7825Smh27603 			if (pm_raise_power(dip, CPUDRV_PM_COMP_NUM,
423*5cff7825Smh27603 			    cpupm->head_spd->pm_level) != DDI_SUCCESS) {
424*5cff7825Smh27603 				mutex_enter(&cpudsp->lock);
425*5cff7825Smh27603 				CPUDRV_PM_MONITOR_INIT(cpudsp);
426*5cff7825Smh27603 				mutex_exit(&cpudsp->lock);
427*5cff7825Smh27603 				cmn_err(CE_WARN, "cpudrv_detach: instance %d: "
428*5cff7825Smh27603 				    "can't raise CPU power level", instance);
429*5cff7825Smh27603 				return (DDI_FAILURE);
430*5cff7825Smh27603 			} else {
431*5cff7825Smh27603 				return (DDI_SUCCESS);
432*5cff7825Smh27603 			}
433*5cff7825Smh27603 		} else {
434*5cff7825Smh27603 			mutex_exit(&cpudsp->lock);
435*5cff7825Smh27603 			return (DDI_SUCCESS);
436*5cff7825Smh27603 		}
437*5cff7825Smh27603 
438*5cff7825Smh27603 	default:
439*5cff7825Smh27603 		return (DDI_FAILURE);
440*5cff7825Smh27603 	}
441*5cff7825Smh27603 }
442*5cff7825Smh27603 
443*5cff7825Smh27603 /*
444*5cff7825Smh27603  * Driver power(9e) entry point.
445*5cff7825Smh27603  *
446*5cff7825Smh27603  * Driver's notion of current power is set *only* in power(9e) entry point
447*5cff7825Smh27603  * after actual power change operation has been successfully completed.
448*5cff7825Smh27603  */
449*5cff7825Smh27603 /* ARGSUSED */
450*5cff7825Smh27603 static int
451*5cff7825Smh27603 cpudrv_power(dev_info_t *dip, int comp, int level)
452*5cff7825Smh27603 {
453*5cff7825Smh27603 	int			instance;
454*5cff7825Smh27603 	cpudrv_devstate_t	*cpudsp;
455*5cff7825Smh27603 	cpudrv_pm_t 		*cpupm;
456*5cff7825Smh27603 	cpudrv_pm_spd_t		*new_spd;
457*5cff7825Smh27603 	boolean_t		is_ready;
458*5cff7825Smh27603 	int			ret;
459*5cff7825Smh27603 
460*5cff7825Smh27603 	instance = ddi_get_instance(dip);
461*5cff7825Smh27603 
462*5cff7825Smh27603 	DPRINTF(D_POWER, ("cpudrv_power: instance %d: level %d\n",
463*5cff7825Smh27603 	    instance, level));
464*5cff7825Smh27603 	if ((cpudsp = ddi_get_soft_state(cpudrv_state, instance)) == NULL) {
465*5cff7825Smh27603 		cmn_err(CE_WARN, "cpudrv_power: instance %d: can't get state",
466*5cff7825Smh27603 		    instance);
467*5cff7825Smh27603 		return (DDI_FAILURE);
468*5cff7825Smh27603 	}
469*5cff7825Smh27603 
470*5cff7825Smh27603 	mutex_enter(&cpudsp->lock);
471*5cff7825Smh27603 	cpupm = &(cpudsp->cpudrv_pm);
472*5cff7825Smh27603 
473*5cff7825Smh27603 	/*
474*5cff7825Smh27603 	 * In normal operation, we fail if we are busy and request is
475*5cff7825Smh27603 	 * to lower the power level. We let this go through if the driver
476*5cff7825Smh27603 	 * is in special direct pm mode. On x86, we also let this through
477*5cff7825Smh27603 	 * if the change is due to a request to throttle the max speed.
478*5cff7825Smh27603 	 */
479*5cff7825Smh27603 	if (!cpudrv_direct_pm && (cpupm->pm_busycnt >= 1) &&
480*5cff7825Smh27603 		!cpudrv_pm_is_throttle_thread(cpupm)) {
481*5cff7825Smh27603 		if ((cpupm->cur_spd != NULL) &&
482*5cff7825Smh27603 		    (level < cpupm->cur_spd->pm_level)) {
483*5cff7825Smh27603 			mutex_exit(&cpudsp->lock);
484*5cff7825Smh27603 			return (DDI_FAILURE);
485*5cff7825Smh27603 		}
486*5cff7825Smh27603 	}
487*5cff7825Smh27603 
488*5cff7825Smh27603 	for (new_spd = cpupm->head_spd; new_spd; new_spd = new_spd->down_spd) {
489*5cff7825Smh27603 		if (new_spd->pm_level == level)
490*5cff7825Smh27603 			break;
491*5cff7825Smh27603 	}
492*5cff7825Smh27603 	if (!new_spd) {
493*5cff7825Smh27603 		CPUDRV_PM_RESET_THROTTLE_THREAD(cpupm);
494*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
495*5cff7825Smh27603 		cmn_err(CE_WARN, "cpudrv_power: instance %d: "
496*5cff7825Smh27603 		    "can't locate new CPU speed", instance);
497*5cff7825Smh27603 		return (DDI_FAILURE);
498*5cff7825Smh27603 	}
499*5cff7825Smh27603 
500*5cff7825Smh27603 	/*
501*5cff7825Smh27603 	 * We currently refuse to power manage if the CPU is not ready to
502*5cff7825Smh27603 	 * take cross calls (cross calls fail silently if CPU is not ready
503*5cff7825Smh27603 	 * for it).
504*5cff7825Smh27603 	 *
505*5cff7825Smh27603 	 * Additionally, for x86 platforms we cannot power manage
506*5cff7825Smh27603 	 * any one instance, until all instances have been initialized.
507*5cff7825Smh27603 	 * That's because we don't know what the CPU domains look like
508*5cff7825Smh27603 	 * until all instances have been initialized.
509*5cff7825Smh27603 	 */
510*5cff7825Smh27603 	is_ready = CPUDRV_PM_XCALL_IS_READY(cpudsp->cpu_id);
511*5cff7825Smh27603 	if (!is_ready) {
512*5cff7825Smh27603 		DPRINTF(D_POWER, ("cpudrv_power: instance %d: "
513*5cff7825Smh27603 		    "CPU not ready for x-calls\n", instance));
514*5cff7825Smh27603 	} else if (!(is_ready = cpudrv_pm_all_instances_ready())) {
515*5cff7825Smh27603 		DPRINTF(D_POWER, ("cpudrv_power: instance %d: "
516*5cff7825Smh27603 		    "waiting for all CPUs to be ready\n", instance));
517*5cff7825Smh27603 	}
518*5cff7825Smh27603 	if (!is_ready) {
519*5cff7825Smh27603 		CPUDRV_PM_RESET_THROTTLE_THREAD(cpupm);
520*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
521*5cff7825Smh27603 		return (DDI_FAILURE);
522*5cff7825Smh27603 	}
523*5cff7825Smh27603 
524*5cff7825Smh27603 	/*
525*5cff7825Smh27603 	 * Execute CPU specific routine on the requested CPU to change its
526*5cff7825Smh27603 	 * speed to normal-speed/divisor.
527*5cff7825Smh27603 	 */
528*5cff7825Smh27603 	if ((ret = cpudrv_pm_change_speed(cpudsp, new_spd)) != DDI_SUCCESS) {
529*5cff7825Smh27603 		cmn_err(CE_WARN, "cpudrv_power: cpudrv_pm_change_speed() "
530*5cff7825Smh27603 		    "return = %d", ret);
531*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
532*5cff7825Smh27603 		return (DDI_FAILURE);
533*5cff7825Smh27603 	}
534*5cff7825Smh27603 
535*5cff7825Smh27603 	/*
536*5cff7825Smh27603 	 * Reset idle threshold time for the new power level.
537*5cff7825Smh27603 	 */
538*5cff7825Smh27603 	if ((cpupm->cur_spd != NULL) && (level < cpupm->cur_spd->pm_level)) {
539*5cff7825Smh27603 		if (pm_idle_component(dip, CPUDRV_PM_COMP_NUM) ==
540*5cff7825Smh27603 		    DDI_SUCCESS) {
541*5cff7825Smh27603 			if (cpupm->pm_busycnt >= 1)
542*5cff7825Smh27603 				cpupm->pm_busycnt--;
543*5cff7825Smh27603 		} else
544*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_power: instance %d: can't "
545*5cff7825Smh27603 			    "idle CPU component", ddi_get_instance(dip));
546*5cff7825Smh27603 	}
547*5cff7825Smh27603 	/*
548*5cff7825Smh27603 	 * Reset various parameters because we are now running at new speed.
549*5cff7825Smh27603 	 */
550*5cff7825Smh27603 	cpupm->lastquan_mstate[CMS_IDLE] = 0;
551*5cff7825Smh27603 	cpupm->lastquan_mstate[CMS_SYSTEM] = 0;
552*5cff7825Smh27603 	cpupm->lastquan_mstate[CMS_USER] = 0;
553*5cff7825Smh27603 	cpupm->lastquan_lbolt = 0;
554*5cff7825Smh27603 	cpupm->cur_spd = new_spd;
555*5cff7825Smh27603 	CPUDRV_PM_RESET_THROTTLE_THREAD(cpupm);
556*5cff7825Smh27603 	mutex_exit(&cpudsp->lock);
557*5cff7825Smh27603 
558*5cff7825Smh27603 	return (DDI_SUCCESS);
559*5cff7825Smh27603 }
560*5cff7825Smh27603 
561*5cff7825Smh27603 /*
562*5cff7825Smh27603  * Initialize the field that will be used for reporting
563*5cff7825Smh27603  * the supported_frequencies_Hz cpu_info kstat.
564*5cff7825Smh27603  */
565*5cff7825Smh27603 static void
566*5cff7825Smh27603 set_supp_freqs(cpu_t *cp, cpudrv_pm_t *cpupm)
567*5cff7825Smh27603 {
568*5cff7825Smh27603 	char		*supp_freqs;
569*5cff7825Smh27603 	char		*sfptr;
570*5cff7825Smh27603 	uint64_t	*speeds;
571*5cff7825Smh27603 	cpudrv_pm_spd_t	*spd;
572*5cff7825Smh27603 	int		i;
573*5cff7825Smh27603 #define	UINT64_MAX_STRING (sizeof ("18446744073709551615"))
574*5cff7825Smh27603 
575*5cff7825Smh27603 	speeds = kmem_zalloc(cpupm->num_spd * sizeof (uint64_t), KM_SLEEP);
576*5cff7825Smh27603 	for (i = cpupm->num_spd - 1, spd = cpupm->head_spd; spd;
577*5cff7825Smh27603 	    i--, spd = spd->down_spd) {
578*5cff7825Smh27603 		speeds[i] =
579*5cff7825Smh27603 		    CPUDRV_PM_SPEED_HZ(cp->cpu_type_info.pi_clock, spd->speed);
580*5cff7825Smh27603 	}
581*5cff7825Smh27603 
582*5cff7825Smh27603 	supp_freqs = kmem_zalloc((UINT64_MAX_STRING * cpupm->num_spd),
583*5cff7825Smh27603 	    KM_SLEEP);
584*5cff7825Smh27603 	sfptr = supp_freqs;
585*5cff7825Smh27603 	for (i = 0; i < cpupm->num_spd; i++) {
586*5cff7825Smh27603 		if (i == cpupm->num_spd - 1) {
587*5cff7825Smh27603 			(void) sprintf(sfptr, "%"PRIu64, speeds[i]);
588*5cff7825Smh27603 		} else {
589*5cff7825Smh27603 			(void) sprintf(sfptr, "%"PRIu64":", speeds[i]);
590*5cff7825Smh27603 			sfptr = supp_freqs + strlen(supp_freqs);
591*5cff7825Smh27603 		}
592*5cff7825Smh27603 	}
593*5cff7825Smh27603 	cp->cpu_type_info.pi_supp_freqs = supp_freqs;
594*5cff7825Smh27603 	kmem_free(speeds, cpupm->num_spd * sizeof (uint64_t));
595*5cff7825Smh27603 }
596*5cff7825Smh27603 
597*5cff7825Smh27603 /*
598*5cff7825Smh27603  * Initialize power management data.
599*5cff7825Smh27603  */
600*5cff7825Smh27603 static int
601*5cff7825Smh27603 cpudrv_pm_init(cpudrv_devstate_t *cpudsp)
602*5cff7825Smh27603 {
603*5cff7825Smh27603 	cpudrv_pm_t 	*cpupm = &(cpudsp->cpudrv_pm);
604*5cff7825Smh27603 	cpudrv_pm_spd_t	*cur_spd;
605*5cff7825Smh27603 	cpudrv_pm_spd_t	*prev_spd = NULL;
606*5cff7825Smh27603 	int		*speeds;
607*5cff7825Smh27603 	uint_t		nspeeds;
608*5cff7825Smh27603 	int		idle_cnt_percent;
609*5cff7825Smh27603 	int		user_cnt_percent;
610*5cff7825Smh27603 	int		i;
611*5cff7825Smh27603 
612*5cff7825Smh27603 	if (!cpudrv_pm_init_module(cpudsp))
613*5cff7825Smh27603 		return (DDI_FAILURE);
614*5cff7825Smh27603 
615*5cff7825Smh27603 	CPUDRV_PM_GET_SPEEDS(cpudsp, speeds, nspeeds);
616*5cff7825Smh27603 	if (nspeeds < 2) {
617*5cff7825Smh27603 		/* Need at least two speeds to power manage */
618*5cff7825Smh27603 		CPUDRV_PM_FREE_SPEEDS(speeds, nspeeds);
619*5cff7825Smh27603 		cpudrv_pm_free_module(cpudsp);
620*5cff7825Smh27603 		return (DDI_FAILURE);
621*5cff7825Smh27603 	}
622*5cff7825Smh27603 	cpupm->num_spd = nspeeds;
623*5cff7825Smh27603 
624*5cff7825Smh27603 	/*
625*5cff7825Smh27603 	 * Calculate the watermarks and other parameters based on the
626*5cff7825Smh27603 	 * supplied speeds.
627*5cff7825Smh27603 	 *
628*5cff7825Smh27603 	 * One of the basic assumption is that for X amount of CPU work,
629*5cff7825Smh27603 	 * if CPU is slowed down by a factor of N, the time it takes to
630*5cff7825Smh27603 	 * do the same work will be N * X.
631*5cff7825Smh27603 	 *
632*5cff7825Smh27603 	 * The driver declares that a CPU is idle and ready for slowed down,
633*5cff7825Smh27603 	 * if amount of idle thread is more than the current speed idle_hwm
634*5cff7825Smh27603 	 * without dropping below idle_hwm a number of consecutive sampling
635*5cff7825Smh27603 	 * intervals and number of running threads in user mode are below
636*5cff7825Smh27603 	 * user_lwm.  We want to set the current user_lwm such that if we
637*5cff7825Smh27603 	 * just switched to the next slower speed with no change in real work
638*5cff7825Smh27603 	 * load, the amount of user threads at the slower speed will be such
639*5cff7825Smh27603 	 * that it falls below the slower speed's user_hwm.  If we didn't do
640*5cff7825Smh27603 	 * that then we will just come back to the higher speed as soon as we
641*5cff7825Smh27603 	 * go down even with no change in work load.
642*5cff7825Smh27603 	 * The user_hwm is a fixed precentage and not calculated dynamically.
643*5cff7825Smh27603 	 *
644*5cff7825Smh27603 	 * We bring the CPU up if idle thread at current speed is less than
645*5cff7825Smh27603 	 * the current speed idle_lwm for a number of consecutive sampling
646*5cff7825Smh27603 	 * intervals or user threads are above the user_hwm for the current
647*5cff7825Smh27603 	 * speed.
648*5cff7825Smh27603 	 */
649*5cff7825Smh27603 	for (i = 0; i < nspeeds; i++) {
650*5cff7825Smh27603 		cur_spd = kmem_zalloc(sizeof (cpudrv_pm_spd_t), KM_SLEEP);
651*5cff7825Smh27603 		cur_spd->speed = speeds[i];
652*5cff7825Smh27603 		if (i == 0) {	/* normal speed */
653*5cff7825Smh27603 			cpupm->head_spd = cur_spd;
654*5cff7825Smh27603 			cur_spd->quant_cnt = CPUDRV_PM_QUANT_CNT_NORMAL;
655*5cff7825Smh27603 			cur_spd->idle_hwm =
656*5cff7825Smh27603 			    (cpudrv_pm_idle_hwm * cur_spd->quant_cnt) / 100;
657*5cff7825Smh27603 			/* can't speed anymore */
658*5cff7825Smh27603 			cur_spd->idle_lwm = 0;
659*5cff7825Smh27603 			cur_spd->user_hwm = UINT_MAX;
660*5cff7825Smh27603 		} else {
661*5cff7825Smh27603 			cur_spd->quant_cnt = CPUDRV_PM_QUANT_CNT_OTHR;
662*5cff7825Smh27603 			ASSERT(prev_spd != NULL);
663*5cff7825Smh27603 			prev_spd->down_spd = cur_spd;
664*5cff7825Smh27603 			cur_spd->up_spd = cpupm->head_spd;
665*5cff7825Smh27603 
666*5cff7825Smh27603 			/*
667*5cff7825Smh27603 			 * Let's assume CPU is considered idle at full speed
668*5cff7825Smh27603 			 * when it is spending I% of time in running the idle
669*5cff7825Smh27603 			 * thread.  At full speed, CPU will be busy (100 - I) %
670*5cff7825Smh27603 			 * of times.  This % of busyness increases by factor of
671*5cff7825Smh27603 			 * N as CPU slows down.  CPU that is idle I% of times
672*5cff7825Smh27603 			 * in full speed, it is idle (100 - ((100 - I) * N)) %
673*5cff7825Smh27603 			 * of times in N speed.  The idle_lwm is a fixed
674*5cff7825Smh27603 			 * percentage.  A large value of N may result in
675*5cff7825Smh27603 			 * idle_hwm to go below idle_lwm.  We need to make sure
676*5cff7825Smh27603 			 * that there is at least a buffer zone seperation
677*5cff7825Smh27603 			 * between the idle_lwm and idle_hwm values.
678*5cff7825Smh27603 			 */
679*5cff7825Smh27603 			idle_cnt_percent = CPUDRV_PM_IDLE_CNT_PERCENT(
680*5cff7825Smh27603 			    cpudrv_pm_idle_hwm, speeds, i);
681*5cff7825Smh27603 			idle_cnt_percent = max(idle_cnt_percent,
682*5cff7825Smh27603 			    (cpudrv_pm_idle_lwm + cpudrv_pm_idle_buf_zone));
683*5cff7825Smh27603 			cur_spd->idle_hwm =
684*5cff7825Smh27603 			    (idle_cnt_percent * cur_spd->quant_cnt) / 100;
685*5cff7825Smh27603 			cur_spd->idle_lwm =
686*5cff7825Smh27603 			    (cpudrv_pm_idle_lwm * cur_spd->quant_cnt) / 100;
687*5cff7825Smh27603 
688*5cff7825Smh27603 			/*
689*5cff7825Smh27603 			 * The lwm for user threads are determined such that
690*5cff7825Smh27603 			 * if CPU slows down, the load of work in the
691*5cff7825Smh27603 			 * new speed would still keep the CPU at or below the
692*5cff7825Smh27603 			 * user_hwm in the new speed.  This is to prevent
693*5cff7825Smh27603 			 * the quick jump back up to higher speed.
694*5cff7825Smh27603 			 */
695*5cff7825Smh27603 			cur_spd->user_hwm = (cpudrv_pm_user_hwm *
696*5cff7825Smh27603 			    cur_spd->quant_cnt) / 100;
697*5cff7825Smh27603 			user_cnt_percent = CPUDRV_PM_USER_CNT_PERCENT(
698*5cff7825Smh27603 			    cpudrv_pm_user_hwm, speeds, i);
699*5cff7825Smh27603 			prev_spd->user_lwm =
700*5cff7825Smh27603 			    (user_cnt_percent * prev_spd->quant_cnt) / 100;
701*5cff7825Smh27603 		}
702*5cff7825Smh27603 		prev_spd = cur_spd;
703*5cff7825Smh27603 	}
704*5cff7825Smh27603 	/* Slowest speed. Can't slow down anymore */
705*5cff7825Smh27603 	cur_spd->idle_hwm = UINT_MAX;
706*5cff7825Smh27603 	cur_spd->user_lwm = -1;
707*5cff7825Smh27603 #ifdef	DEBUG
708*5cff7825Smh27603 	DPRINTF(D_PM_INIT, ("cpudrv_pm_init: instance %d: head_spd spd %d, "
709*5cff7825Smh27603 	    "num_spd %d\n", ddi_get_instance(cpudsp->dip),
710*5cff7825Smh27603 	    cpupm->head_spd->speed, cpupm->num_spd));
711*5cff7825Smh27603 	for (cur_spd = cpupm->head_spd; cur_spd; cur_spd = cur_spd->down_spd) {
712*5cff7825Smh27603 		DPRINTF(D_PM_INIT, ("cpudrv_pm_init: instance %d: speed %d, "
713*5cff7825Smh27603 		    "down_spd spd %d, idle_hwm %d, user_lwm %d, "
714*5cff7825Smh27603 		    "up_spd spd %d, idle_lwm %d, user_hwm %d, "
715*5cff7825Smh27603 		    "quant_cnt %d\n", ddi_get_instance(cpudsp->dip),
716*5cff7825Smh27603 		    cur_spd->speed,
717*5cff7825Smh27603 		    (cur_spd->down_spd ? cur_spd->down_spd->speed : 0),
718*5cff7825Smh27603 		    cur_spd->idle_hwm, cur_spd->user_lwm,
719*5cff7825Smh27603 		    (cur_spd->up_spd ? cur_spd->up_spd->speed : 0),
720*5cff7825Smh27603 		    cur_spd->idle_lwm, cur_spd->user_hwm,
721*5cff7825Smh27603 		    cur_spd->quant_cnt));
722*5cff7825Smh27603 	}
723*5cff7825Smh27603 #endif	/* DEBUG */
724*5cff7825Smh27603 	CPUDRV_PM_FREE_SPEEDS(speeds, nspeeds);
725*5cff7825Smh27603 	return (DDI_SUCCESS);
726*5cff7825Smh27603 }
727*5cff7825Smh27603 
728*5cff7825Smh27603 /*
729*5cff7825Smh27603  * Free CPU power management data.
730*5cff7825Smh27603  */
731*5cff7825Smh27603 static void
732*5cff7825Smh27603 cpudrv_pm_free(cpudrv_devstate_t *cpudsp)
733*5cff7825Smh27603 {
734*5cff7825Smh27603 	cpudrv_pm_t 	*cpupm = &(cpudsp->cpudrv_pm);
735*5cff7825Smh27603 	cpudrv_pm_spd_t	*cur_spd, *next_spd;
736*5cff7825Smh27603 
737*5cff7825Smh27603 	cur_spd = cpupm->head_spd;
738*5cff7825Smh27603 	while (cur_spd) {
739*5cff7825Smh27603 		next_spd = cur_spd->down_spd;
740*5cff7825Smh27603 		kmem_free(cur_spd, sizeof (cpudrv_pm_spd_t));
741*5cff7825Smh27603 		cur_spd = next_spd;
742*5cff7825Smh27603 	}
743*5cff7825Smh27603 	bzero(cpupm, sizeof (cpudrv_pm_t));
744*5cff7825Smh27603 	cpudrv_pm_free_module(cpudsp);
745*5cff7825Smh27603 }
746*5cff7825Smh27603 
747*5cff7825Smh27603 /*
748*5cff7825Smh27603  * Create pm-components property.
749*5cff7825Smh27603  */
750*5cff7825Smh27603 static int
751*5cff7825Smh27603 cpudrv_pm_comp_create(cpudrv_devstate_t *cpudsp)
752*5cff7825Smh27603 {
753*5cff7825Smh27603 	cpudrv_pm_t 	*cpupm = &(cpudsp->cpudrv_pm);
754*5cff7825Smh27603 	cpudrv_pm_spd_t	*cur_spd;
755*5cff7825Smh27603 	char		**pmc;
756*5cff7825Smh27603 	int		size;
757*5cff7825Smh27603 	char		name[] = "NAME=CPU Speed";
758*5cff7825Smh27603 	int		i, j;
759*5cff7825Smh27603 	uint_t		comp_spd;
760*5cff7825Smh27603 	int		result = DDI_FAILURE;
761*5cff7825Smh27603 
762*5cff7825Smh27603 	pmc = kmem_zalloc((cpupm->num_spd + 1) * sizeof (char *), KM_SLEEP);
763*5cff7825Smh27603 	size = CPUDRV_PM_COMP_SIZE();
764*5cff7825Smh27603 	if (cpupm->num_spd > CPUDRV_PM_COMP_MAX_VAL) {
765*5cff7825Smh27603 		cmn_err(CE_WARN, "cpudrv_pm_comp_create: instance %d: "
766*5cff7825Smh27603 		    "number of speeds exceeded limits",
767*5cff7825Smh27603 		    ddi_get_instance(cpudsp->dip));
768*5cff7825Smh27603 		kmem_free(pmc, (cpupm->num_spd + 1) * sizeof (char *));
769*5cff7825Smh27603 		return (result);
770*5cff7825Smh27603 	}
771*5cff7825Smh27603 
772*5cff7825Smh27603 	for (i = cpupm->num_spd, cur_spd = cpupm->head_spd; i > 0;
773*5cff7825Smh27603 	    i--, cur_spd = cur_spd->down_spd) {
774*5cff7825Smh27603 		cur_spd->pm_level = i;
775*5cff7825Smh27603 		pmc[i] = kmem_zalloc((size * sizeof (char)), KM_SLEEP);
776*5cff7825Smh27603 		comp_spd = CPUDRV_PM_COMP_SPEED(cpupm, cur_spd);
777*5cff7825Smh27603 		if (comp_spd > CPUDRV_PM_COMP_MAX_VAL) {
778*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_pm_comp_create: "
779*5cff7825Smh27603 			    "instance %d: speed exceeded limits",
780*5cff7825Smh27603 			    ddi_get_instance(cpudsp->dip));
781*5cff7825Smh27603 			for (j = cpupm->num_spd; j >= i; j--) {
782*5cff7825Smh27603 				kmem_free(pmc[j], size * sizeof (char));
783*5cff7825Smh27603 			}
784*5cff7825Smh27603 			kmem_free(pmc, (cpupm->num_spd + 1) *
785*5cff7825Smh27603 			    sizeof (char *));
786*5cff7825Smh27603 			return (result);
787*5cff7825Smh27603 		}
788*5cff7825Smh27603 		CPUDRV_PM_COMP_SPRINT(pmc[i], cpupm, cur_spd, comp_spd)
789*5cff7825Smh27603 		DPRINTF(D_PM_COMP_CREATE, ("cpudrv_pm_comp_create: "
790*5cff7825Smh27603 		    "instance %d: pm-components power level %d string '%s'\n",
791*5cff7825Smh27603 		    ddi_get_instance(cpudsp->dip), i, pmc[i]));
792*5cff7825Smh27603 	}
793*5cff7825Smh27603 	pmc[0] = kmem_zalloc(sizeof (name), KM_SLEEP);
794*5cff7825Smh27603 	(void) strcat(pmc[0], name);
795*5cff7825Smh27603 	DPRINTF(D_PM_COMP_CREATE, ("cpudrv_pm_comp_create: instance %d: "
796*5cff7825Smh27603 	    "pm-components component name '%s'\n",
797*5cff7825Smh27603 	    ddi_get_instance(cpudsp->dip), pmc[0]));
798*5cff7825Smh27603 
799*5cff7825Smh27603 	if (ddi_prop_update_string_array(DDI_DEV_T_NONE, cpudsp->dip,
800*5cff7825Smh27603 	    "pm-components", pmc, cpupm->num_spd + 1) == DDI_PROP_SUCCESS) {
801*5cff7825Smh27603 		result = DDI_SUCCESS;
802*5cff7825Smh27603 	} else {
803*5cff7825Smh27603 		cmn_err(CE_WARN, "cpudrv_pm_comp_create: instance %d: "
804*5cff7825Smh27603 		    "can't create pm-components property",
805*5cff7825Smh27603 		    ddi_get_instance(cpudsp->dip));
806*5cff7825Smh27603 	}
807*5cff7825Smh27603 
808*5cff7825Smh27603 	for (i = cpupm->num_spd; i > 0; i--) {
809*5cff7825Smh27603 		kmem_free(pmc[i], size * sizeof (char));
810*5cff7825Smh27603 	}
811*5cff7825Smh27603 	kmem_free(pmc[0], sizeof (name));
812*5cff7825Smh27603 	kmem_free(pmc, (cpupm->num_spd + 1) * sizeof (char *));
813*5cff7825Smh27603 	return (result);
814*5cff7825Smh27603 }
815*5cff7825Smh27603 
816*5cff7825Smh27603 /*
817*5cff7825Smh27603  * Mark a component idle.
818*5cff7825Smh27603  */
819*5cff7825Smh27603 #define	CPUDRV_PM_MONITOR_PM_IDLE_COMP(dip, cpupm) { \
820*5cff7825Smh27603 	if ((cpupm)->pm_busycnt >= 1) { \
821*5cff7825Smh27603 		if (pm_idle_component((dip), CPUDRV_PM_COMP_NUM) == \
822*5cff7825Smh27603 		    DDI_SUCCESS) { \
823*5cff7825Smh27603 			DPRINTF(D_PM_MONITOR, ("cpudrv_pm_monitor: " \
824*5cff7825Smh27603 			    "instance %d: pm_idle_component called\n", \
825*5cff7825Smh27603 			    ddi_get_instance((dip)))); \
826*5cff7825Smh27603 			(cpupm)->pm_busycnt--; \
827*5cff7825Smh27603 		} else { \
828*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_pm_monitor: instance %d: " \
829*5cff7825Smh27603 			    "can't idle CPU component", \
830*5cff7825Smh27603 			    ddi_get_instance((dip))); \
831*5cff7825Smh27603 		} \
832*5cff7825Smh27603 	} \
833*5cff7825Smh27603 }
834*5cff7825Smh27603 
835*5cff7825Smh27603 /*
836*5cff7825Smh27603  * Marks a component busy in both PM framework and driver state structure.
837*5cff7825Smh27603  */
838*5cff7825Smh27603 #define	CPUDRV_PM_MONITOR_PM_BUSY_COMP(dip, cpupm) { \
839*5cff7825Smh27603 	if ((cpupm)->pm_busycnt < 1) { \
840*5cff7825Smh27603 		if (pm_busy_component((dip), CPUDRV_PM_COMP_NUM) == \
841*5cff7825Smh27603 		    DDI_SUCCESS) { \
842*5cff7825Smh27603 			DPRINTF(D_PM_MONITOR, ("cpudrv_pm_monitor: " \
843*5cff7825Smh27603 			    "instance %d: pm_busy_component called\n", \
844*5cff7825Smh27603 			    ddi_get_instance((dip)))); \
845*5cff7825Smh27603 			(cpupm)->pm_busycnt++; \
846*5cff7825Smh27603 		} else { \
847*5cff7825Smh27603 			cmn_err(CE_WARN, "cpudrv_pm_monitor: instance %d: " \
848*5cff7825Smh27603 			    "can't busy CPU component", \
849*5cff7825Smh27603 			    ddi_get_instance((dip))); \
850*5cff7825Smh27603 		} \
851*5cff7825Smh27603 	} \
852*5cff7825Smh27603 }
853*5cff7825Smh27603 
854*5cff7825Smh27603 /*
855*5cff7825Smh27603  * Marks a component busy and calls pm_raise_power().
856*5cff7825Smh27603  */
857*5cff7825Smh27603 #define	CPUDRV_PM_MONITOR_PM_BUSY_AND_RAISE(dip, cpudsp, cpupm, new_level) { \
858*5cff7825Smh27603 	/* \
859*5cff7825Smh27603 	 * Mark driver and PM framework busy first so framework doesn't try \
860*5cff7825Smh27603 	 * to bring CPU to lower speed when we need to be at higher speed. \
861*5cff7825Smh27603 	 */ \
862*5cff7825Smh27603 	CPUDRV_PM_MONITOR_PM_BUSY_COMP((dip), (cpupm)); \
863*5cff7825Smh27603 	mutex_exit(&(cpudsp)->lock); \
864*5cff7825Smh27603 	DPRINTF(D_PM_MONITOR, ("cpudrv_pm_monitor: instance %d: " \
865*5cff7825Smh27603 	    "pm_raise_power called to %d\n", ddi_get_instance((dip)), \
866*5cff7825Smh27603 		(new_level))); \
867*5cff7825Smh27603 	if (pm_raise_power((dip), CPUDRV_PM_COMP_NUM, (new_level)) != \
868*5cff7825Smh27603 	    DDI_SUCCESS) { \
869*5cff7825Smh27603 		cmn_err(CE_WARN, "cpudrv_pm_monitor: instance %d: can't " \
870*5cff7825Smh27603 		    "raise CPU power level", ddi_get_instance((dip))); \
871*5cff7825Smh27603 	} \
872*5cff7825Smh27603 	mutex_enter(&(cpudsp)->lock); \
873*5cff7825Smh27603 }
874*5cff7825Smh27603 
875*5cff7825Smh27603 /*
876*5cff7825Smh27603  * In order to monitor a CPU, we need to hold cpu_lock to access CPU
877*5cff7825Smh27603  * statistics. Holding cpu_lock is not allowed from a callout routine.
878*5cff7825Smh27603  * We dispatch a taskq to do that job.
879*5cff7825Smh27603  */
880*5cff7825Smh27603 static void
881*5cff7825Smh27603 cpudrv_pm_monitor_disp(void *arg)
882*5cff7825Smh27603 {
883*5cff7825Smh27603 	cpudrv_devstate_t	*cpudsp = (cpudrv_devstate_t *)arg;
884*5cff7825Smh27603 
885*5cff7825Smh27603 	/*
886*5cff7825Smh27603 	 * We are here because the last task has scheduled a timeout.
887*5cff7825Smh27603 	 * The queue should be empty at this time.
888*5cff7825Smh27603 	 */
889*5cff7825Smh27603 	mutex_enter(&cpudsp->cpudrv_pm.timeout_lock);
890*5cff7825Smh27603 	if (!taskq_dispatch(cpudsp->cpudrv_pm.tq, cpudrv_pm_monitor, arg,
891*5cff7825Smh27603 	    TQ_NOSLEEP)) {
892*5cff7825Smh27603 		mutex_exit(&cpudsp->cpudrv_pm.timeout_lock);
893*5cff7825Smh27603 		DPRINTF(D_PM_MONITOR, ("cpudrv_pm_monitor_disp: failed to "
894*5cff7825Smh27603 		    "dispatch the cpudrv_pm_monitor taskq\n"));
895*5cff7825Smh27603 		mutex_enter(&cpudsp->lock);
896*5cff7825Smh27603 		CPUDRV_PM_MONITOR_INIT(cpudsp);
897*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
898*5cff7825Smh27603 		return;
899*5cff7825Smh27603 	}
900*5cff7825Smh27603 	cpudsp->cpudrv_pm.timeout_count++;
901*5cff7825Smh27603 	mutex_exit(&cpudsp->cpudrv_pm.timeout_lock);
902*5cff7825Smh27603 }
903*5cff7825Smh27603 
904*5cff7825Smh27603 /*
905*5cff7825Smh27603  * Get current CPU microstate times and scale them. We should probably be
906*5cff7825Smh27603  * using get_cpu_mstate() to get this data, but bugs in some of the ISRs
907*5cff7825Smh27603  * have led to inflated system times and prevented CPUs from being power
908*5cff7825Smh27603  * managed. We can probably safely ignore time spent in ISRs when
909*5cff7825Smh27603  * determining idleness.
910*5cff7825Smh27603  */
911*5cff7825Smh27603 static void
912*5cff7825Smh27603 cpudrv_get_cpu_mstate(cpu_t *cpu, hrtime_t *times)
913*5cff7825Smh27603 {
914*5cff7825Smh27603 	int i;
915*5cff7825Smh27603 
916*5cff7825Smh27603 	for (i = 0; i < NCMSTATES; i++) {
917*5cff7825Smh27603 		times[i] = cpu->cpu_acct[i];
918*5cff7825Smh27603 		scalehrtime(&times[i]);
919*5cff7825Smh27603 	}
920*5cff7825Smh27603 }
921*5cff7825Smh27603 
922*5cff7825Smh27603 /*
923*5cff7825Smh27603  * Monitors each CPU for the amount of time idle thread was running in the
924*5cff7825Smh27603  * last quantum and arranges for the CPU to go to the lower or higher speed.
925*5cff7825Smh27603  * Called at the time interval appropriate for the current speed. The
926*5cff7825Smh27603  * time interval for normal speed is CPUDRV_PM_QUANT_CNT_NORMAL. The time
927*5cff7825Smh27603  * interval for other speeds (including unknown speed) is
928*5cff7825Smh27603  * CPUDRV_PM_QUANT_CNT_OTHR.
929*5cff7825Smh27603  */
930*5cff7825Smh27603 static void
931*5cff7825Smh27603 cpudrv_pm_monitor(void *arg)
932*5cff7825Smh27603 {
933*5cff7825Smh27603 	cpudrv_devstate_t	*cpudsp = (cpudrv_devstate_t *)arg;
934*5cff7825Smh27603 	cpudrv_pm_t		*cpupm;
935*5cff7825Smh27603 	cpudrv_pm_spd_t		*cur_spd, *new_spd;
936*5cff7825Smh27603 	cpu_t			*cp;
937*5cff7825Smh27603 	dev_info_t		*dip;
938*5cff7825Smh27603 	uint_t			idle_cnt, user_cnt, system_cnt;
939*5cff7825Smh27603 	clock_t			lbolt_cnt;
940*5cff7825Smh27603 	hrtime_t		msnsecs[NCMSTATES];
941*5cff7825Smh27603 	boolean_t		is_ready;
942*5cff7825Smh27603 
943*5cff7825Smh27603 #define	GET_CPU_MSTATE_CNT(state, cnt) \
944*5cff7825Smh27603 	msnsecs[state] = NSEC_TO_TICK(msnsecs[state]); \
945*5cff7825Smh27603 	if (cpupm->lastquan_mstate[state] > msnsecs[state]) \
946*5cff7825Smh27603 		msnsecs[state] = cpupm->lastquan_mstate[state]; \
947*5cff7825Smh27603 	cnt = msnsecs[state] - cpupm->lastquan_mstate[state]; \
948*5cff7825Smh27603 	cpupm->lastquan_mstate[state] = msnsecs[state]
949*5cff7825Smh27603 
950*5cff7825Smh27603 	mutex_enter(&cpudsp->lock);
951*5cff7825Smh27603 	cpupm = &(cpudsp->cpudrv_pm);
952*5cff7825Smh27603 	if (cpupm->timeout_id == 0) {
953*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
954*5cff7825Smh27603 		goto do_return;
955*5cff7825Smh27603 	}
956*5cff7825Smh27603 	cur_spd = cpupm->cur_spd;
957*5cff7825Smh27603 	dip = cpudsp->dip;
958*5cff7825Smh27603 
959*5cff7825Smh27603 	/*
960*5cff7825Smh27603 	 * We assume that a CPU is initialized and has a valid cpu_t
961*5cff7825Smh27603 	 * structure, if it is ready for cross calls. If this changes,
962*5cff7825Smh27603 	 * additional checks might be needed.
963*5cff7825Smh27603 	 *
964*5cff7825Smh27603 	 * Additionally, for x86 platforms we cannot power manage
965*5cff7825Smh27603 	 * any one instance, until all instances have been initialized.
966*5cff7825Smh27603 	 * That's because we don't know what the CPU domains look like
967*5cff7825Smh27603 	 * until all instances have been initialized.
968*5cff7825Smh27603 	 */
969*5cff7825Smh27603 	is_ready = CPUDRV_PM_XCALL_IS_READY(cpudsp->cpu_id);
970*5cff7825Smh27603 	if (!is_ready) {
971*5cff7825Smh27603 		DPRINTF(D_PM_MONITOR, ("cpudrv_pm_monitor: instance %d: "
972*5cff7825Smh27603 		    "CPU not ready for x-calls\n", ddi_get_instance(dip)));
973*5cff7825Smh27603 	} else if (!(is_ready = cpudrv_pm_all_instances_ready())) {
974*5cff7825Smh27603 		DPRINTF(D_PM_MONITOR, ("cpudrv_pm_monitor: instance %d: "
975*5cff7825Smh27603 		    "waiting for all CPUs to be ready\n",
976*5cff7825Smh27603 		    ddi_get_instance(dip)));
977*5cff7825Smh27603 	}
978*5cff7825Smh27603 	if (!is_ready) {
979*5cff7825Smh27603 		/*
980*5cff7825Smh27603 		 * Make sure that we are busy so that framework doesn't
981*5cff7825Smh27603 		 * try to bring us down in this situation.
982*5cff7825Smh27603 		 */
983*5cff7825Smh27603 		CPUDRV_PM_MONITOR_PM_BUSY_COMP(dip, cpupm);
984*5cff7825Smh27603 		CPUDRV_PM_MONITOR_INIT(cpudsp);
985*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
986*5cff7825Smh27603 		goto do_return;
987*5cff7825Smh27603 	}
988*5cff7825Smh27603 
989*5cff7825Smh27603 	/*
990*5cff7825Smh27603 	 * Make sure that we are still not at unknown power level.
991*5cff7825Smh27603 	 */
992*5cff7825Smh27603 	if (cur_spd == NULL) {
993*5cff7825Smh27603 		DPRINTF(D_PM_MONITOR, ("cpudrv_pm_monitor: instance %d: "
994*5cff7825Smh27603 		    "cur_spd is unknown\n", ddi_get_instance(dip)));
995*5cff7825Smh27603 		CPUDRV_PM_MONITOR_PM_BUSY_AND_RAISE(dip, cpudsp, cpupm,
996*5cff7825Smh27603 		    cpupm->targ_spd->pm_level);
997*5cff7825Smh27603 		/*
998*5cff7825Smh27603 		 * We just changed the speed. Wait till at least next
999*5cff7825Smh27603 		 * call to this routine before proceeding ahead.
1000*5cff7825Smh27603 		 */
1001*5cff7825Smh27603 		CPUDRV_PM_MONITOR_INIT(cpudsp);
1002*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
1003*5cff7825Smh27603 		goto do_return;
1004*5cff7825Smh27603 	}
1005*5cff7825Smh27603 
1006*5cff7825Smh27603 	mutex_enter(&cpu_lock);
1007*5cff7825Smh27603 	if ((cp = cpu_get(cpudsp->cpu_id)) == NULL) {
1008*5cff7825Smh27603 		mutex_exit(&cpu_lock);
1009*5cff7825Smh27603 		CPUDRV_PM_MONITOR_INIT(cpudsp);
1010*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
1011*5cff7825Smh27603 		cmn_err(CE_WARN, "cpudrv_pm_monitor: instance %d: can't get "
1012*5cff7825Smh27603 		    "cpu_t", ddi_get_instance(dip));
1013*5cff7825Smh27603 		goto do_return;
1014*5cff7825Smh27603 	}
1015*5cff7825Smh27603 	if (cp->cpu_type_info.pi_supp_freqs == NULL)
1016*5cff7825Smh27603 		set_supp_freqs(cp, cpupm);
1017*5cff7825Smh27603 
1018*5cff7825Smh27603 	cpudrv_get_cpu_mstate(cp, msnsecs);
1019*5cff7825Smh27603 	GET_CPU_MSTATE_CNT(CMS_IDLE, idle_cnt);
1020*5cff7825Smh27603 	GET_CPU_MSTATE_CNT(CMS_USER, user_cnt);
1021*5cff7825Smh27603 	GET_CPU_MSTATE_CNT(CMS_SYSTEM, system_cnt);
1022*5cff7825Smh27603 
1023*5cff7825Smh27603 	/*
1024*5cff7825Smh27603 	 * We can't do anything when we have just switched to a state
1025*5cff7825Smh27603 	 * because there is no valid timestamp.
1026*5cff7825Smh27603 	 */
1027*5cff7825Smh27603 	if (cpupm->lastquan_lbolt == 0) {
1028*5cff7825Smh27603 		cpupm->lastquan_lbolt = lbolt;
1029*5cff7825Smh27603 		mutex_exit(&cpu_lock);
1030*5cff7825Smh27603 		CPUDRV_PM_MONITOR_INIT(cpudsp);
1031*5cff7825Smh27603 		mutex_exit(&cpudsp->lock);
1032*5cff7825Smh27603 		goto do_return;
1033*5cff7825Smh27603 	}
1034*5cff7825Smh27603 
1035*5cff7825Smh27603 	/*
1036*5cff7825Smh27603 	 * Various watermarks are based on this routine being called back
1037*5cff7825Smh27603 	 * exactly at the requested period. This is not guaranteed
1038*5cff7825Smh27603 	 * because this routine is called from a taskq that is dispatched
1039*5cff7825Smh27603 	 * from a timeout routine.  Handle this by finding out how many
1040*5cff7825Smh27603 	 * ticks have elapsed since the last call (lbolt_cnt) and adjusting
1041*5cff7825Smh27603 	 * the idle_cnt based on the delay added to the requested period
1042*5cff7825Smh27603 	 * by timeout and taskq.
1043*5cff7825Smh27603 	 */
1044*5cff7825Smh27603 	lbolt_cnt = lbolt - cpupm->lastquan_lbolt;
1045*5cff7825Smh27603 	cpupm->lastquan_lbolt = lbolt;
1046*5cff7825Smh27603 	mutex_exit(&cpu_lock);
1047*5cff7825Smh27603 	/*
1048*5cff7825Smh27603 	 * Time taken between recording the current counts and
1049*5cff7825Smh27603 	 * arranging the next call of this routine is an error in our
1050*5cff7825Smh27603 	 * calculation. We minimize the error by calling
1051*5cff7825Smh27603 	 * CPUDRV_PM_MONITOR_INIT() here instead of end of this routine.
1052*5cff7825Smh27603 	 */
1053*5cff7825Smh27603 	CPUDRV_PM_MONITOR_INIT(cpudsp);
1054*5cff7825Smh27603 	DPRINTF(D_PM_MONITOR_VERBOSE, ("cpudrv_pm_monitor: instance %d: "
1055*5cff7825Smh27603 	    "idle count %d, user count %d, system count %d, pm_level %d, "
1056*5cff7825Smh27603 	    "pm_busycnt %d\n", ddi_get_instance(dip), idle_cnt, user_cnt,
1057*5cff7825Smh27603 	    system_cnt, cur_spd->pm_level, cpupm->pm_busycnt));
1058*5cff7825Smh27603 
1059*5cff7825Smh27603 #ifdef	DEBUG
1060*5cff7825Smh27603 	/*
1061*5cff7825Smh27603 	 * Notify that timeout and taskq has caused delays and we need to
1062*5cff7825Smh27603 	 * scale our parameters accordingly.
1063*5cff7825Smh27603 	 *
1064*5cff7825Smh27603 	 * To get accurate result, don't turn on other DPRINTFs with
1065*5cff7825Smh27603 	 * the following DPRINTF. PROM calls generated by other
1066*5cff7825Smh27603 	 * DPRINTFs changes the timing.
1067*5cff7825Smh27603 	 */
1068*5cff7825Smh27603 	if (lbolt_cnt > cur_spd->quant_cnt) {
1069*5cff7825Smh27603 		DPRINTF(D_PM_MONITOR_DELAY, ("cpudrv_pm_monitor: instance %d: "
1070*5cff7825Smh27603 		    "lbolt count %ld > quantum_count %u\n",
1071*5cff7825Smh27603 		    ddi_get_instance(dip), lbolt_cnt, cur_spd->quant_cnt));
1072*5cff7825Smh27603 	}
1073*5cff7825Smh27603 #endif	/* DEBUG */
1074*5cff7825Smh27603 
1075*5cff7825Smh27603 	/*
1076*5cff7825Smh27603 	 * Adjust counts based on the delay added by timeout and taskq.
1077*5cff7825Smh27603 	 */
1078*5cff7825Smh27603 	idle_cnt = (idle_cnt * cur_spd->quant_cnt) / lbolt_cnt;
1079*5cff7825Smh27603 	user_cnt = (user_cnt * cur_spd->quant_cnt) / lbolt_cnt;
1080*5cff7825Smh27603 	if ((user_cnt > cur_spd->user_hwm) || (idle_cnt < cur_spd->idle_lwm &&
1081*5cff7825Smh27603 	    cur_spd->idle_blwm_cnt >= cpudrv_pm_idle_blwm_cnt_max)) {
1082*5cff7825Smh27603 		cur_spd->idle_blwm_cnt = 0;
1083*5cff7825Smh27603 		cur_spd->idle_bhwm_cnt = 0;
1084*5cff7825Smh27603 		/*
1085*5cff7825Smh27603 		 * In normal situation, arrange to go to next higher speed.
1086*5cff7825Smh27603 		 * If we are running in special direct pm mode, we just stay
1087*5cff7825Smh27603 		 * at the current speed.
1088*5cff7825Smh27603 		 */
1089*5cff7825Smh27603 		if (cur_spd == cur_spd->up_spd || cpudrv_direct_pm) {
1090*5cff7825Smh27603 			CPUDRV_PM_MONITOR_PM_BUSY_COMP(dip, cpupm);
1091*5cff7825Smh27603 		} else {
1092*5cff7825Smh27603 			new_spd = cur_spd->up_spd;
1093*5cff7825Smh27603 			CPUDRV_PM_MONITOR_PM_BUSY_AND_RAISE(dip, cpudsp, cpupm,
1094*5cff7825Smh27603 			    new_spd->pm_level);
1095*5cff7825Smh27603 		}
1096*5cff7825Smh27603 	} else if ((user_cnt <= cur_spd->user_lwm) &&
1097*5cff7825Smh27603 	    (idle_cnt >= cur_spd->idle_hwm) || !CPU_ACTIVE(cp)) {
1098*5cff7825Smh27603 		cur_spd->idle_blwm_cnt = 0;
1099*5cff7825Smh27603 		cur_spd->idle_bhwm_cnt = 0;
1100*5cff7825Smh27603 		/*
1101*5cff7825Smh27603 		 * Arrange to go to next lower speed by informing our idle
1102*5cff7825Smh27603 		 * status to the power management framework.
1103*5cff7825Smh27603 		 */
1104*5cff7825Smh27603 		CPUDRV_PM_MONITOR_PM_IDLE_COMP(dip, cpupm);
1105*5cff7825Smh27603 	} else {
1106*5cff7825Smh27603 		/*
1107*5cff7825Smh27603 		 * If we are between the idle water marks and have not
1108*5cff7825Smh27603 		 * been here enough consecutive times to be considered
1109*5cff7825Smh27603 		 * busy, just increment the count and return.
1110*5cff7825Smh27603 		 */
1111*5cff7825Smh27603 		if ((idle_cnt < cur_spd->idle_hwm) &&
1112*5cff7825Smh27603 		    (idle_cnt >= cur_spd->idle_lwm) &&
1113*5cff7825Smh27603 		    (cur_spd->idle_bhwm_cnt < cpudrv_pm_idle_bhwm_cnt_max)) {
1114*5cff7825Smh27603 			cur_spd->idle_blwm_cnt = 0;
1115*5cff7825Smh27603 			cur_spd->idle_bhwm_cnt++;
1116*5cff7825Smh27603 			mutex_exit(&cpudsp->lock);
1117*5cff7825Smh27603 			goto do_return;
1118*5cff7825Smh27603 		}
1119*5cff7825Smh27603 		if (idle_cnt < cur_spd->idle_lwm) {
1120*5cff7825Smh27603 			cur_spd->idle_blwm_cnt++;
1121*5cff7825Smh27603 			cur_spd->idle_bhwm_cnt = 0;
1122*5cff7825Smh27603 		}
1123*5cff7825Smh27603 		/*
1124*5cff7825Smh27603 		 * Arranges to stay at the current speed.
1125*5cff7825Smh27603 		 */
1126*5cff7825Smh27603 		CPUDRV_PM_MONITOR_PM_BUSY_COMP(dip, cpupm);
1127*5cff7825Smh27603 	}
1128*5cff7825Smh27603 	mutex_exit(&cpudsp->lock);
1129*5cff7825Smh27603 do_return:
1130*5cff7825Smh27603 	mutex_enter(&cpupm->timeout_lock);
1131*5cff7825Smh27603 	ASSERT(cpupm->timeout_count > 0);
1132*5cff7825Smh27603 	cpupm->timeout_count--;
1133*5cff7825Smh27603 	cv_signal(&cpupm->timeout_cv);
1134*5cff7825Smh27603 	mutex_exit(&cpupm->timeout_lock);
1135*5cff7825Smh27603 }
1136