1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#pragma ident "%Z%%M% %I% %E% SMI" 27 28/* 29 * SFMMU primitives. These primitives should only be used by sfmmu 30 * routines. 31 */ 32 33#if defined(lint) 34#include <sys/types.h> 35#else /* lint */ 36#include "assym.h" 37#endif /* lint */ 38 39#include <sys/asm_linkage.h> 40#include <sys/machtrap.h> 41#include <sys/machasi.h> 42#include <sys/sun4asi.h> 43#include <sys/pte.h> 44#include <sys/mmu.h> 45#include <vm/hat_sfmmu.h> 46#include <vm/seg_spt.h> 47#include <sys/machparam.h> 48#include <sys/privregs.h> 49#include <sys/scb.h> 50#include <sys/intreg.h> 51#include <sys/machthread.h> 52#include <sys/clock.h> 53#include <sys/trapstat.h> 54 55/* 56 * sfmmu related subroutines 57 */ 58 59#if defined (lint) 60 61/* ARGSUSED */ 62void 63sfmmu_raise_tsb_exception(uint64_t sfmmup, uint64_t rctx) 64{} 65 66int 67sfmmu_getctx_pri() 68{ return(0); } 69 70int 71sfmmu_getctx_sec() 72{ return(0); } 73 74/* ARGSUSED */ 75void 76sfmmu_setctx_sec(int ctx) 77{} 78 79/* ARGSUSED */ 80void 81sfmmu_load_mmustate(sfmmu_t *sfmmup) 82{ 83} 84 85#else /* lint */ 86 87/* 88 * Invalidate either the context of a specific victim or any process 89 * currently running on this CPU. 90 * 91 * %g1 = sfmmup whose ctx is being stolen (victim) 92 * when called from sfmmu_wrap_around, %g1 == INVALID_CONTEXT. 93 * Note %g1 is the only input argument used by this xcall handler. 94 */ 95 96 ENTRY(sfmmu_raise_tsb_exception) 97 ! 98 ! if (victim == INVALID_CONTEXT) { 99 ! if (sec-ctx > INVALID_CONTEXT) 100 ! write INVALID_CONTEXT to sec-ctx 101 ! if (pri-ctx > INVALID_CONTEXT) 102 ! write INVALID_CONTEXT to pri-ctx 103 ! 104 ! } else if (current CPU tsbmiss->usfmmup != victim sfmmup) { 105 ! return 106 ! } else { 107 ! if (sec-ctx > INVALID_CONTEXT) 108 ! write INVALID_CONTEXT to sec-ctx 109 ! 110 ! if (pri-ctx > INVALID_CONTEXT) 111 ! write INVALID_CONTEXT to pri-ctx 112 ! } 113 ! 114 115 sethi %hi(ksfmmup), %g3 116 ldx [%g3 + %lo(ksfmmup)], %g3 117 cmp %g1, %g3 118 be,a,pn %xcc, ptl1_panic /* can't invalidate kernel ctx */ 119 mov PTL1_BAD_RAISE_TSBEXCP, %g1 120 121 set INVALID_CONTEXT, %g2 122 123 cmp %g1, INVALID_CONTEXT 124 bne,pt %xcc, 1f /* called from wrap_around? */ 125 mov MMU_SCONTEXT, %g3 126 127 ldxa [%g3]ASI_MMU_CTX, %g5 /* %g5 = sec-ctx */ 128 cmp %g5, INVALID_CONTEXT /* kernel or invalid ctx ? */ 129 ble,pn %xcc, 0f /* yes, no need to change */ 130 mov MMU_PCONTEXT, %g7 131 132 stxa %g2, [%g3]ASI_MMU_CTX /* set invalid ctx */ 133 membar #Sync 134 1350: 136 ldxa [%g7]ASI_MMU_CTX, %g5 /* %g5 = pri-ctx */ 137 cmp %g5, INVALID_CONTEXT /* kernel or invalid ctx? */ 138 ble,pn %xcc, 6f /* yes, no need to change */ 139 nop 140 141 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */ 142 membar #Sync 143 1446: /* flushall tlb */ 145 mov %o0, %g3 146 mov %o1, %g4 147 mov %o2, %g6 148 mov %o5, %g7 149 150 mov %g0, %o0 ! XXX no cpu list yet 151 mov %g0, %o1 ! XXX no cpu list yet 152 mov MAP_ITLB | MAP_DTLB, %o2 153 mov MMU_DEMAP_ALL, %o5 154 ta FAST_TRAP 155 brz,pt %o0, 5f 156 nop 157 ba panic_bad_hcall 158 mov MMU_DEMAP_ALL, %o1 1595: 160 mov %g3, %o0 161 mov %g4, %o1 162 mov %g6, %o2 163 mov %g7, %o5 164 165 ba 3f 166 nop 1671: 168 /* 169 * %g1 = sfmmup 170 * %g2 = INVALID_CONTEXT 171 * %g3 = MMU_SCONTEXT 172 */ 173 CPU_TSBMISS_AREA(%g5, %g6) /* load cpu tsbmiss area */ 174 ldx [%g5 + TSBMISS_UHATID], %g5 /* load usfmmup */ 175 176 cmp %g5, %g1 /* is it the victim? */ 177 bne,pt %xcc, 2f /* is our sec-ctx a victim? */ 178 nop 179 180 ldxa [%g3]ASI_MMU_CTX, %g5 /* %g5 = sec-ctx */ 181 cmp %g5, INVALID_CONTEXT /* kernel or invalid ctx ? */ 182 ble,pn %xcc, 0f /* yes, no need to change */ 183 mov MMU_PCONTEXT, %g7 184 185 stxa %g2, [%g3]ASI_MMU_CTX /* set sec-ctx to invalid */ 186 membar #Sync 187 1880: 189 ldxa [%g7]ASI_MMU_CTX, %g4 /* %g4 = pri-ctx */ 190 cmp %g4, INVALID_CONTEXT /* is pri-ctx the victim? */ 191 ble %icc, 3f /* no need to change pri-ctx */ 192 nop 193 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */ 194 membar #Sync 195 1963: 197 /* TSB program must be cleared - walkers do not check a context. */ 198 mov %o0, %g3 199 mov %o1, %g4 200 mov %o5, %g7 201 clr %o0 202 clr %o1 203 mov MMU_TSB_CTXNON0, %o5 204 ta FAST_TRAP 205 brnz,a,pn %o0, ptl1_panic 206 mov PTL1_BAD_HCALL, %g1 207 mov %g3, %o0 208 mov %g4, %o1 209 mov %g7, %o5 2102: 211 retry 212 SET_SIZE(sfmmu_raise_tsb_exception) 213 214 ENTRY_NP(sfmmu_getctx_pri) 215 set MMU_PCONTEXT, %o0 216 set CTXREG_CTX_MASK, %o1 217 ldxa [%o0]ASI_MMU_CTX, %o0 218 retl 219 and %o0, %o1, %o0 220 SET_SIZE(sfmmu_getctx_pri) 221 222 ENTRY_NP(sfmmu_getctx_sec) 223 set MMU_SCONTEXT, %o0 224 set CTXREG_CTX_MASK, %o1 225 ldxa [%o0]ASI_MMU_CTX, %o0 226 retl 227 and %o0, %o1, %o0 228 SET_SIZE(sfmmu_getctx_sec) 229 230 /* 231 * Set the secondary context register for this process. 232 * %o0 = context number 233 */ 234 ENTRY_NP(sfmmu_setctx_sec) 235 /* 236 * From resume we call sfmmu_setctx_sec with interrupts disabled. 237 * But we can also get called from C with interrupts enabled. So, 238 * we need to check first. 239 */ 240 241 /* If interrupts are not disabled, then disable them */ 242 rdpr %pstate, %g1 243 btst PSTATE_IE, %g1 244 bnz,a,pt %icc, 1f 245 wrpr %g1, PSTATE_IE, %pstate /* disable interrupts */ 2461: 247 mov MMU_SCONTEXT, %o1 248 sethi %hi(FLUSH_ADDR), %o4 249 stxa %o0, [%o1]ASI_MMU_CTX /* set 2nd context reg. */ 250 flush %o4 251 252 /* 253 * if the routine is entered with intr enabled, then enable intr now. 254 * otherwise, keep intr disabled, return without enabing intr. 255 * %g1 - old intr state 256 */ 257 btst PSTATE_IE, %g1 258 bnz,a,pt %icc, 2f 259 wrpr %g0, %g1, %pstate /* enable interrupts */ 2602: retl 261 nop 262 SET_SIZE(sfmmu_setctx_sec) 263 264 /* 265 * set ktsb_phys to 1 if the processor supports ASI_QUAD_LDD_PHYS. 266 * returns the detection value in %o0. 267 */ 268 ENTRY_NP(sfmmu_setup_4lp) 269 set ktsb_phys, %o2 270 mov 1, %o1 271 st %o1, [%o2] 272 retl 273 mov %o1, %o0 274 SET_SIZE(sfmmu_setup_4lp) 275 276 /* 277 * Called to load MMU registers and tsbmiss area 278 * for the active process. This function should 279 * only be called from TL=0. 280 * 281 * %o0 - hat pointer 282 */ 283 ENTRY_NP(sfmmu_load_mmustate) 284 285#ifdef DEBUG 286 PANIC_IF_INTR_ENABLED_PSTR(msfmmu_ei_l1, %g1) 287#endif /* DEBUG */ 288 289 sethi %hi(ksfmmup), %o3 290 ldx [%o3 + %lo(ksfmmup)], %o3 291 cmp %o3, %o0 292 be,pn %xcc, 3f ! if kernel as, do nothing 293 nop 294 295 /* 296 * We need to set up the TSB base register, tsbmiss 297 * area, and pass the TSB information into the hypervisor 298 */ 299 ldx [%o0 + SFMMU_TSB], %o1 ! %o1 = first tsbinfo 300 ldx [%o1 + TSBINFO_NEXTPTR], %g2 ! %g2 = second tsbinfo 301 302 /* create/set first UTSBREG */ 303 MAKE_UTSBREG(%o1, %o2, %o3) ! %o2 = user tsbreg 304 SET_UTSBREG(SCRATCHPAD_UTSBREG1, %o2, %o3) 305 306 brz,pt %g2, 2f 307 mov -1, %o2 ! use -1 if no second TSB 308 309 /* make 2nd UTSBREG */ 310 MAKE_UTSBREG(%g2, %o2, %o3) ! %o2 = user tsbreg 3112: 312 SET_UTSBREG(SCRATCHPAD_UTSBREG2, %o2, %o3) 313 314#ifdef DEBUG 315 /* check if hypervisor/hardware should handle user TSB */ 316 sethi %hi(hv_use_non0_tsb), %o2 317 ld [%o2 + %lo(hv_use_non0_tsb)], %o2 318 brz,pn %o2, 5f 319 nop 320#endif /* DEBUG */ 321 CPU_ADDR(%o2, %o4) ! load CPU struct addr to %o2 using %o4 322 ldub [%o2 + CPU_TSTAT_FLAGS], %o1 ! load cpu_tstat_flag to %o1 323 324 /* 325 * %o0 = sfmmup 326 * %o2 = returned sfmmu cnum on this CPU 327 * %o4 = scratch 328 */ 329 SFMMU_CPU_CNUM(%o0, %o2, %o4) 330 331 mov %o5, %o4 ! preserve %o5 for resume 332 mov %o0, %o3 ! preserve %o0 333 btst TSTAT_TLB_STATS, %o1 334 bnz,a,pn %icc, 4f ! ntsb = 0 if TLB stats enabled 335 clr %o0 336 cmp %o2, INVALID_CONTEXT 337 be,a,pn %icc, 4f 338 clr %o0 ! ntsb = 0 for invalid ctx 339 ldx [%o3 + SFMMU_HVBLOCK + HV_TSB_INFO_CNT], %o0 3404: 341 ldx [%o3 + SFMMU_HVBLOCK + HV_TSB_INFO_PA], %o1 342 mov MMU_TSB_CTXNON0, %o5 343 ta FAST_TRAP ! set TSB info for user process 344 brnz,a,pn %o0, panic_bad_hcall 345 mov MMU_TSB_CTXNON0, %o1 346 mov %o3, %o0 ! restore %o0 347 mov %o4, %o5 ! restore %o5 3485: 349 ldx [%o0 + SFMMU_ISMBLKPA], %o1 ! copy members of sfmmu 350 CPU_TSBMISS_AREA(%o2, %o3) ! we need to access from 351 stx %o1, [%o2 + TSBMISS_ISMBLKPA] ! sfmmu_tsb_miss into the 352 lduh [%o0 + SFMMU_FLAGS], %o3 ! per-CPU tsbmiss area. 353 stx %o0, [%o2 + TSBMISS_UHATID] 354 stuh %o3, [%o2 + TSBMISS_HATFLAGS] 355 3563: retl 357 nop 358 SET_SIZE(sfmmu_load_mmustate) 359 360#endif /* lint */ 361 362#if defined(lint) 363 364/* Prefetch "struct tsbe" while walking TSBs */ 365/*ARGSUSED*/ 366void 367prefetch_tsbe_read(struct tsbe *tsbep) 368{} 369 370/* Prefetch the tsbe that we are about to write */ 371/*ARGSUSED*/ 372void 373prefetch_tsbe_write(struct tsbe *tsbep) 374{} 375 376#else /* lint */ 377 378 ENTRY(prefetch_tsbe_read) 379 retl 380 nop 381 SET_SIZE(prefetch_tsbe_read) 382 383 ENTRY(prefetch_tsbe_write) 384 retl 385 nop 386 SET_SIZE(prefetch_tsbe_write) 387#endif /* lint */ 388