1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NIAGARA2REGS_H 27 #define _SYS_NIAGARA2REGS_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define MB(n) ((n) * 1024 * 1024) 36 37 #define L2CACHE_SIZE MB(4) 38 #define L2CACHE_LINESIZE 64 39 #define L2CACHE_ASSOCIATIVITY 16 40 41 #define NIAGARA2_HSVC_MAJOR 1 42 #define NIAGARA2_HSVC_MINOR 0 43 44 #define VFALLS_HSVC_MAJOR 1 45 #define VFALLS_HSVC_MINOR 0 46 47 #define NIAGARA2_PREALLOC_BASE MB(196) 48 49 /* PIC overflow range is -16 to -1 */ 50 #define PIC_IN_OV_RANGE(x) (((uint32_t)x >= 0xfffffff0) ? 1 : 0) 51 52 /* 53 * Niagara2 SPARC Performance Instrumentation Counter 54 */ 55 #define PIC0_MASK (((uint64_t)1 << 32) - 1) /* pic0 in bits 31:0 */ 56 #define PIC1_SHIFT 32 /* pic1 in bits 64:32 */ 57 58 /* 59 * Niagara2 SPARC Performance Control Register 60 */ 61 #define CPC_NIAGARA2_PCR_PRIV_SHIFT 0 62 #define CPC_NIAGARA2_PCR_ST_SHIFT 1 63 #define CPC_NIAGARA2_PCR_UT_SHIFT 2 64 65 #define CPC_NIAGARA2_PCR_HT_SHIFT 3 66 #define CPC_NIAGARA2_PCR_HT (1ull << CPC_NIAGARA2_PCR_HT_SHIFT) 67 68 #define CPC_NIAGARA2_PCR_TOE0_SHIFT 4 69 #define CPC_NIAGARA2_PCR_TOE1_SHIFT 5 70 #define CPC_NIAGARA2_PCR_TOE0 (1ull << CPC_NIAGARA2_PCR_TOE0_SHIFT) 71 #define CPC_NIAGARA2_PCR_TOE1 (1ull << CPC_NIAGARA2_PCR_TOE1_SHIFT) 72 73 #define CPC_NIAGARA2_PCR_PIC0_SHIFT 6 74 #define CPC_NIAGARA2_PCR_PIC1_SHIFT 19 75 #define CPC_NIAGARA2_PCR_PIC0_MASK UINT64_C(0xfff) 76 #define CPC_NIAGARA2_PCR_PIC1_MASK UINT64_C(0xfff) 77 78 #define CPC_NIAGARA2_PCR_OV0_SHIFT 18 79 #define CPC_NIAGARA2_PCR_OV1_SHIFT 30 80 #define CPC_NIAGARA2_PCR_OV0_MASK UINT64_C(0x40000) 81 #define CPC_NIAGARA2_PCR_OV1_MASK UINT64_C(0x80000000) 82 83 #define CPC_NIAGARA2_PCR_HOLDOV0_SHIFT 62 84 #define CPC_NIAGARA2_PCR_HOLDOV1_SHIFT 63 85 #define CPC_NIAGARA2_PCR_HOLDOV0 (1ull << CPC_NIAGARA2_PCR_HOLDOV0_SHIFT) 86 #define CPC_NIAGARA2_PCR_HOLDOV1 (1ull << CPC_NIAGARA2_PCR_HOLDOV1_SHIFT) 87 88 /* 89 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 90 * performance counters for Niagara2 91 */ 92 #define HV_NIAGARA2_GETPERF 0x104 93 #define HV_NIAGARA2_SETPERF 0x105 94 95 /* 96 * Hypervisor FAST_TRAP API function numbers to get/set DRAM 97 * performance counters for Victoria Falls 98 */ 99 #define HV_VFALLS_GETPERF 0x106 100 #define HV_VFALLS_SETPERF 0x107 101 102 /* 103 * Niagara2 DRAM performance counters 104 */ 105 #define NIAGARA_DRAM_PIC0_SEL_SHIFT 0x4 106 #define NIAGARA_DRAM_PIC1_SEL_SHIFT 0x0 107 108 #define NIAGARA_DRAM_PIC0_SHIFT 0x20 109 #define NIAGARA_DRAM_PIC0_MASK 0x7fffffff 110 #define NIAGARA_DRAM_PIC1_SHIFT 0x0 111 #define NIAGARA_DRAM_PIC1_MASK 0x7fffffff 112 113 #if defined(NIAGARA2_IMPL) 114 /* 115 * SPARC/DRAM performance counter register numbers for HV_NIAGARA2_GETPERF 116 * and HV_NIAGARA2_SETPERF for Niagara2 117 */ 118 #define NIAGARA_DRAM_BANKS 0x4 119 120 #define HV_NIAGARA_SPARC_CTL 0x0 121 #define HV_NIAGARA_DRAM_CTL0 0x1 122 #define HV_NIAGARA_DRAM_COUNT0 0x2 123 #define HV_NIAGARA_DRAM_CTL1 0x3 124 #define HV_NIAGARA_DRAM_COUNT1 0x4 125 #define HV_NIAGARA_DRAM_CTL2 0x5 126 #define HV_NIAGARA_DRAM_COUNT2 0x6 127 #define HV_NIAGARA_DRAM_CTL3 0x7 128 #define HV_NIAGARA_DRAM_COUNT3 0x8 129 130 #elif defined(VFALLS_IMPL) 131 /* 132 * SPARC/DRAM performance counter register numbers for HV_VFALLS_GETPERF 133 * and HV_VFALLS_SETPERF for Victoria Falls 134 * Support for 4-node configuration 135 */ 136 #define NIAGARA_DRAM_BANKS 0x8 137 138 #define HV_NIAGARA_SPARC_CTL 0x0 139 #define HV_NIAGARA_L2_CTL 0x1 140 #define HV_NIAGARA_DRAM_CTL0 0x2 141 #define HV_NIAGARA_DRAM_COUNT0 0x3 142 #define HV_NIAGARA_DRAM_CTL1 0x4 143 #define HV_NIAGARA_DRAM_COUNT1 0x5 144 #define HV_NIAGARA_DRAM_CTL2 0x6 145 #define HV_NIAGARA_DRAM_COUNT2 0x7 146 #define HV_NIAGARA_DRAM_CTL3 0x8 147 #define HV_NIAGARA_DRAM_COUNT3 0x9 148 #define HV_NIAGARA_DRAM_CTL4 0xa 149 #define HV_NIAGARA_DRAM_COUNT4 0xb 150 #define HV_NIAGARA_DRAM_CTL5 0xc 151 #define HV_NIAGARA_DRAM_COUNT5 0xd 152 #define HV_NIAGARA_DRAM_CTL6 0xe 153 #define HV_NIAGARA_DRAM_COUNT6 0xf 154 #define HV_NIAGARA_DRAM_CTL7 0x10 155 #define HV_NIAGARA_DRAM_COUNT7 0x11 156 157 #define ZAMBEZI_PIC0_SEL_SHIFT 0x0 158 #define ZAMBEZI_PIC1_SEL_SHIFT 0x8 159 160 #define ZAMBEZI_LPU_COUNTERS 0x10 161 #define ZAMBEZI_GPD_COUNTERS 0x4 162 #define ZAMBEZI_ASU_COUNTERS 0x4 163 164 #define HV_ZAM0_LPU_A_PCR 0x12 165 #define HV_ZAM0_LPU_A_PIC0 0x13 166 #define HV_ZAM0_LPU_A_PIC1 0x14 167 #define HV_ZAM0_LPU_B_PCR 0x15 168 #define HV_ZAM0_LPU_B_PIC0 0x16 169 #define HV_ZAM0_LPU_B_PIC1 0x17 170 #define HV_ZAM0_LPU_C_PCR 0x18 171 #define HV_ZAM0_LPU_C_PIC0 0x19 172 #define HV_ZAM0_LPU_C_PIC1 0x1a 173 #define HV_ZAM0_LPU_D_PCR 0x1b 174 #define HV_ZAM0_LPU_D_PIC0 0x1c 175 #define HV_ZAM0_LPU_D_PIC1 0x1d 176 #define HV_ZAM0_GPD_PCR 0x1e 177 #define HV_ZAM0_GPD_PIC0 0x1f 178 #define HV_ZAM0_GPD_PIC1 0x20 179 #define HV_ZAM0_ASU_PCR 0x21 180 #define HV_ZAM0_ASU_PIC0 0x22 181 #define HV_ZAM0_ASU_PIC1 0x23 182 183 #define HV_ZAM1_LPU_A_PCR 0x24 184 #define HV_ZAM1_LPU_A_PIC0 0x25 185 #define HV_ZAM1_LPU_A_PIC1 0x26 186 #define HV_ZAM1_LPU_B_PCR 0x27 187 #define HV_ZAM1_LPU_B_PIC0 0x28 188 #define HV_ZAM1_LPU_B_PIC1 0x29 189 #define HV_ZAM1_LPU_C_PCR 0x2a 190 #define HV_ZAM1_LPU_C_PIC0 0x2b 191 #define HV_ZAM1_LPU_C_PIC1 0x2c 192 #define HV_ZAM1_LPU_D_PCR 0x2d 193 #define HV_ZAM1_LPU_D_PIC0 0x2e 194 #define HV_ZAM1_LPU_D_PIC1 0x2f 195 #define HV_ZAM1_GPD_PCR 0x30 196 #define HV_ZAM1_GPD_PIC0 0x31 197 #define HV_ZAM1_GPD_PIC1 0x32 198 #define HV_ZAM1_ASU_PCR 0x33 199 #define HV_ZAM1_ASU_PIC0 0x34 200 #define HV_ZAM1_ASU_PIC1 0x35 201 202 #define HV_ZAM2_LPU_A_PCR 0x36 203 #define HV_ZAM2_LPU_A_PIC0 0x37 204 #define HV_ZAM2_LPU_A_PIC1 0x38 205 #define HV_ZAM2_LPU_B_PCR 0x39 206 #define HV_ZAM2_LPU_B_PIC0 0x3a 207 #define HV_ZAM2_LPU_B_PIC1 0x3b 208 #define HV_ZAM2_LPU_C_PCR 0x3c 209 #define HV_ZAM2_LPU_C_PIC0 0x3d 210 #define HV_ZAM2_LPU_C_PIC1 0x3e 211 #define HV_ZAM2_LPU_D_PCR 0x3f 212 #define HV_ZAM2_LPU_D_PIC0 0x40 213 #define HV_ZAM2_LPU_D_PIC1 0x41 214 #define HV_ZAM2_GPD_PCR 0x42 215 #define HV_ZAM2_GPD_PIC0 0x43 216 #define HV_ZAM2_GPD_PIC1 0x44 217 #define HV_ZAM2_ASU_PCR 0x45 218 #define HV_ZAM2_ASU_PIC0 0x46 219 #define HV_ZAM2_ASU_PIC1 0x47 220 221 #define HV_ZAM3_LPU_A_PCR 0x48 222 #define HV_ZAM3_LPU_A_PIC0 0x49 223 #define HV_ZAM3_LPU_A_PIC1 0x4a 224 #define HV_ZAM3_LPU_B_PCR 0x4b 225 #define HV_ZAM3_LPU_B_PIC0 0x4c 226 #define HV_ZAM3_LPU_B_PIC1 0x4d 227 #define HV_ZAM3_LPU_C_PCR 0x4e 228 #define HV_ZAM3_LPU_C_PIC0 0x4f 229 #define HV_ZAM3_LPU_C_PIC1 0x50 230 #define HV_ZAM3_LPU_D_PCR 0x51 231 #define HV_ZAM3_LPU_D_PIC0 0x52 232 #define HV_ZAM3_LPU_D_PIC1 0x53 233 #define HV_ZAM3_GPD_PCR 0x54 234 #define HV_ZAM3_GPD_PIC0 0x55 235 #define HV_ZAM3_GPD_PIC1 0x56 236 #define HV_ZAM3_ASU_PCR 0x57 237 #define HV_ZAM3_ASU_PIC0 0x58 238 #define HV_ZAM3_ASU_PIC1 0x59 239 240 #define VFALLS_L2_CTL_MASK 0x3 241 #define VFALLS_SL3_MASK 0x300 242 243 #endif 244 245 #ifndef _ASM 246 /* 247 * prototypes for hypervisor interface to get/set SPARC and DRAM 248 * performance counters 249 */ 250 extern uint64_t hv_niagara_setperf(uint64_t regnum, uint64_t val); 251 extern uint64_t hv_niagara_getperf(uint64_t regnum, uint64_t *val); 252 #endif 253 254 #ifdef __cplusplus 255 } 256 #endif 257 258 #endif /* _SYS_NIAGARA2REGS_H */ 259