1 /* 2 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 #ifndef _SYS_MMU_H 7 #define _SYS_MMU_H 8 9 #pragma ident "%Z%%M% %I% %E% SMI" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 #ifndef _ASM 16 #include <sys/types.h> 17 #endif 18 #include <sys/hypervisor_api.h> 19 20 /* 21 * Definitions for the SOFT MMU 22 */ 23 24 #define FAST_IMMU_MISS_TT 0x64 25 #define FAST_DMMU_MISS_TT 0x68 26 #define FAST_PROT_TT 0x6c 27 28 /* 29 * Constants defining alternate spaces 30 * and register layouts within them, 31 * and a few other interesting assembly constants. 32 */ 33 34 /* 35 * vaddr offsets of various registers 36 */ 37 #define MMU_PCONTEXT 0x08 /* primary context number */ 38 #define MMU_SCONTEXT 0x10 /* secondary context number */ 39 40 /* 41 * Pseudo Synchronous Fault Status Register Layout 42 * 43 * IMMU and DMMU maintain their own pseudo SFSR Register 44 * 45 * +------------------------------------------------+ 46 * | Reserved | Context | FT | 47 * +----------------------|-------------------------+ 48 * 63 32 31 16 15 0 49 * 50 */ 51 #define SFSR_FT 0x0000FFFF /* fault type mask */ 52 #define SFSR_CTX 0xFFFF0000 /* fault context mask */ 53 54 /* 55 * Definition of FT (Fault Type) bit field of sfsr. 56 */ 57 #define FT_NONE 0x00 58 #define FT_PRIV MMFSA_F_PRIV /* privilege violation */ 59 #define FT_SPEC_LD MMFSA_F_SOPG /* speculative ld to e page */ 60 #define FT_ATOMIC_NC MMFSA_F_NCATM /* atomic to nc page */ 61 #define FT_ILL_ALT MMFSA_F_INVASI /* illegal lda/sta */ 62 #define FT_NFO MMFSA_F_NFO /* normal access to nfo page */ 63 #define FT_RANGE MMFSA_F_INVVA /* dmmu or immu address out of range */ 64 #define FT_NEW_FMISS MMFSA_F_FMISS /* fast miss */ 65 #define FT_NEW_FPROT MMFSA_F_FPROT /* fast protection */ 66 #define FT_NEW_MISS MMFSA_F_MISS /* mmu miss */ 67 #define FT_NEW_INVRA MMFSA_F_INVRA /* invalid RA */ 68 #define FT_NEW_PROT MMFSA_F_PROT /* protection violation */ 69 #define FT_NEW_PRVACT MMFSA_F_PRVACT /* privileged action */ 70 #define FT_NEW_WPT MMFSA_F_WPT /* watchpoint hit */ 71 #define FT_NEW_UNALIGN MMFSA_F_UNALIGN /* unaligned access */ 72 #define FT_NEW_INVPGSZ MMFSA_F_INVPGSZ /* invalid page size */ 73 74 #define SFSR_FT_SHIFT 0 /* amt. to shift right to get flt type */ 75 #define SFSR_CTX_SHIFT 16 /* to shift right to get context */ 76 #define X_FAULT_TYPE(x) (((x) & SFSR_FT) >> SFSR_FT_SHIFT) 77 #define X_FAULT_CTX(x) (((x) & SFSR_CTX) >> SFSR_CTX_SHIFT) 78 79 /* 80 * MMU TAG TARGET register Layout 81 * 82 * +-----+---------+------+-------------------------+ 83 * | 000 | context | -- | virtual address [63:22] | 84 * +-----+---------+------+-------------------------+ 85 * 63 61 60 48 47 42 41 0 86 */ 87 #define TTARGET_CTX_SHIFT 48 88 #define TTARGET_VA_SHIFT 22 89 90 /* 91 * MMU TAG ACCESS register Layout 92 * 93 * +-------------------------+------------------+ 94 * | virtual address [63:13] | context [12:0] | 95 * +-------------------------+------------------+ 96 * 63 13 12 0 97 */ 98 #define TAGACC_CTX_MASK 0x1FFF 99 #define TAGACC_SHIFT 13 100 #define TAGACC_VADDR_MASK (~TAGACC_CTX_MASK) 101 #define TAGACC_CTX_LSHIFT (64 - TAGACC_SHIFT) 102 103 /* 104 * MMU PRIMARY/SECONDARY CONTEXT register 105 */ 106 #define CTXREG_CTX_MASK 0x1FFF 107 108 /* 109 * The kernel always runs in KCONTEXT, and no user mappings 110 * are ever valid in it (so any user access pagefaults). 111 */ 112 #define KCONTEXT 0 113 114 /* 115 * FLUSH_ADDR is used in the flush instruction to guarantee stores to mmu 116 * registers complete. It is selected so it won't miss in the tlb. 117 */ 118 #define FLUSH_ADDR (KERNELBASE + 2 * MMU_PAGESIZE4M) 119 120 #define MAX_NCTXS_BITS 16 /* sun4v max. contexts bits */ 121 #define MIN_NCTXS_BITS 2 122 #define MAX_NCTXS (1ull << MAX_NCTXS_BITS) 123 124 #ifdef __cplusplus 125 } 126 #endif 127 128 #endif /* _SYS_MMU_H */ 129