xref: /titanic_52/usr/src/uts/sun4v/os/mach_startup.c (revision f808c858fa61e7769218966759510a8b1190dfcf)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 #include <sys/machsystm.h>
30 #include <sys/archsystm.h>
31 #include <sys/prom_plat.h>
32 #include <sys/promif.h>
33 #include <sys/vm.h>
34 #include <sys/cpu.h>
35 #include <sys/atomic.h>
36 #include <sys/cpupart.h>
37 #include <sys/disp.h>
38 #include <sys/hypervisor_api.h>
39 #include <sys/traptrace.h>
40 #include <sys/modctl.h>
41 #include <sys/ldoms.h>
42 
43 #ifdef TRAPTRACE
44 int mach_htraptrace_enable = 1;
45 #else
46 int mach_htraptrace_enable = 0;
47 #endif
48 int htrap_tr0_inuse = 0;
49 extern char htrap_tr0[];	/* prealloc buf for boot cpu */
50 
51 caddr_t	mmu_fault_status_area;
52 
53 extern void sfmmu_set_tsbs(void);
54 /*
55  * CPU IDLE optimization variables/routines
56  */
57 static int enable_halt_idle_cpus = 1;
58 
59 void
60 setup_trap_table(void)
61 {
62 	caddr_t mmfsa_va;
63 	extern	 caddr_t mmu_fault_status_area;
64 	mmfsa_va =
65 	    mmu_fault_status_area + (MMFSA_SIZE * CPU->cpu_id);
66 
67 	intr_init(CPU);		/* init interrupt request free list */
68 	setwstate(WSTATE_KERN);
69 	set_mmfsa_scratchpad(mmfsa_va);
70 	prom_set_mmfsa_traptable(&trap_table, va_to_pa(mmfsa_va));
71 	sfmmu_set_tsbs();
72 }
73 
74 void
75 phys_install_has_changed(void)
76 {
77 
78 }
79 
80 /*
81  * Halt the present CPU until awoken via an interrupt
82  */
83 static void
84 cpu_halt(void)
85 {
86 	cpu_t *cpup = CPU;
87 	processorid_t cpun = cpup->cpu_id;
88 	cpupart_t *cp = cpup->cpu_part;
89 	int hset_update = 1;
90 	uint_t s;
91 
92 	/*
93 	 * If this CPU is online, and there's multiple CPUs
94 	 * in the system, then we should notate our halting
95 	 * by adding ourselves to the partition's halted CPU
96 	 * bitmap. This allows other CPUs to find/awaken us when
97 	 * work becomes available.
98 	 */
99 	if (CPU->cpu_flags & CPU_OFFLINE || ncpus == 1)
100 		hset_update = 0;
101 
102 	/*
103 	 * Add ourselves to the partition's halted CPUs bitmask
104 	 * and set our HALTED flag, if necessary.
105 	 *
106 	 * When a thread becomes runnable, it is placed on the queue
107 	 * and then the halted cpuset is checked to determine who
108 	 * (if anyone) should be awoken. We therefore need to first
109 	 * add ourselves to the halted cpuset, and then check if there
110 	 * is any work available.
111 	 */
112 	if (hset_update) {
113 		cpup->cpu_disp_flags |= CPU_DISP_HALTED;
114 		membar_producer();
115 		CPUSET_ATOMIC_ADD(cp->cp_haltset, cpun);
116 	}
117 
118 	/*
119 	 * Check to make sure there's really nothing to do.
120 	 * Work destined for this CPU may become available after
121 	 * this check. We'll be notified through the clearing of our
122 	 * bit in the halted CPU bitmask, and a poke.
123 	 */
124 	if (disp_anywork()) {
125 		if (hset_update) {
126 			cpup->cpu_disp_flags &= ~CPU_DISP_HALTED;
127 			CPUSET_ATOMIC_DEL(cp->cp_haltset, cpun);
128 		}
129 		return;
130 	}
131 
132 	/*
133 	 * We're on our way to being halted.
134 	 *
135 	 * Disable interrupts now, so that we'll awaken immediately
136 	 * after halting if someone tries to poke us between now and
137 	 * the time we actually halt.
138 	 *
139 	 * We check for the presence of our bit after disabling interrupts.
140 	 * If it's cleared, we'll return. If the bit is cleared after
141 	 * we check then the poke will pop us out of the halted state.
142 	 *
143 	 * The ordering of the poke and the clearing of the bit by cpu_wakeup
144 	 * is important.
145 	 * cpu_wakeup() must clear, then poke.
146 	 * cpu_halt() must disable interrupts, then check for the bit.
147 	 */
148 	s = disable_vec_intr();
149 
150 	if (hset_update && !CPU_IN_SET(cp->cp_haltset, cpun)) {
151 		cpup->cpu_disp_flags &= ~CPU_DISP_HALTED;
152 		enable_vec_intr(s);
153 		return;
154 	}
155 
156 	/*
157 	 * The check for anything locally runnable is here for performance
158 	 * and isn't needed for correctness. disp_nrunnable ought to be
159 	 * in our cache still, so it's inexpensive to check, and if there
160 	 * is anything runnable we won't have to wait for the poke.
161 	 */
162 	if (cpup->cpu_disp->disp_nrunnable != 0) {
163 		if (hset_update) {
164 			cpup->cpu_disp_flags &= ~CPU_DISP_HALTED;
165 			CPUSET_ATOMIC_DEL(cp->cp_haltset, cpun);
166 		}
167 		enable_vec_intr(s);
168 		return;
169 	}
170 
171 	/*
172 	 * Halt the strand
173 	 */
174 	(void) hv_cpu_yield();
175 
176 	/*
177 	 * We're no longer halted
178 	 */
179 	enable_vec_intr(s);
180 	if (hset_update) {
181 		cpup->cpu_disp_flags &= ~CPU_DISP_HALTED;
182 		CPUSET_ATOMIC_DEL(cp->cp_haltset, cpun);
183 	}
184 }
185 
186 /*
187  * If "cpu" is halted, then wake it up clearing its halted bit in advance.
188  * Otherwise, see if other CPUs in the cpu partition are halted and need to
189  * be woken up so that they can steal the thread we placed on this CPU.
190  * This function is only used on MP systems.
191  */
192 static void
193 cpu_wakeup(cpu_t *cpu, int bound)
194 {
195 	uint_t		cpu_found;
196 	int		result;
197 	cpupart_t	*cp;
198 
199 	cp = cpu->cpu_part;
200 	if (CPU_IN_SET(cp->cp_haltset, cpu->cpu_id)) {
201 		/*
202 		 * Clear the halted bit for that CPU since it will be
203 		 * poked in a moment.
204 		 */
205 		CPUSET_ATOMIC_DEL(cp->cp_haltset, cpu->cpu_id);
206 		/*
207 		 * We may find the current CPU present in the halted cpuset
208 		 * if we're in the context of an interrupt that occurred
209 		 * before we had a chance to clear our bit in cpu_halt().
210 		 * Poking ourself is obviously unnecessary, since if
211 		 * we're here, we're not halted.
212 		 */
213 		if (cpu != CPU)
214 			poke_cpu(cpu->cpu_id);
215 		return;
216 	} else {
217 		/*
218 		 * This cpu isn't halted, but it's idle or undergoing a
219 		 * context switch. No need to awaken anyone else.
220 		 */
221 		if (cpu->cpu_thread == cpu->cpu_idle_thread ||
222 		    cpu->cpu_disp_flags & CPU_DISP_DONTSTEAL)
223 			return;
224 	}
225 
226 	/*
227 	 * No need to wake up other CPUs if the thread we just enqueued
228 	 * is bound.
229 	 */
230 	if (bound)
231 		return;
232 
233 	/*
234 	 * See if there's any other halted CPUs. If there are, then
235 	 * select one, and awaken it.
236 	 * It's possible that after we find a CPU, somebody else
237 	 * will awaken it before we get the chance.
238 	 * In that case, look again.
239 	 */
240 	do {
241 		CPUSET_FIND(cp->cp_haltset, cpu_found);
242 		if (cpu_found == CPUSET_NOTINSET)
243 			return;
244 
245 		ASSERT(cpu_found >= 0 && cpu_found < NCPU);
246 		CPUSET_ATOMIC_XDEL(cp->cp_haltset, cpu_found, result);
247 	} while (result < 0);
248 
249 	if (cpu_found != CPU->cpu_id)
250 		poke_cpu(cpu_found);
251 }
252 
253 void
254 mach_cpu_halt_idle()
255 {
256 	if (enable_halt_idle_cpus) {
257 		idle_cpu = cpu_halt;
258 		disp_enq_thread = cpu_wakeup;
259 	}
260 }
261 
262 int
263 ndata_alloc_mmfsa(struct memlist *ndata)
264 {
265 	size_t	size;
266 
267 	size = MMFSA_SIZE * max_ncpus;
268 	mmu_fault_status_area = ndata_alloc(ndata, size, ecache_alignsize);
269 	if (mmu_fault_status_area == NULL)
270 		return (-1);
271 	return (0);
272 }
273 
274 void
275 mach_memscrub(void)
276 {
277 	/* no memscrub support for sun4v for now */
278 }
279 
280 void
281 mach_fpras()
282 {
283 	/* no fpras support for sun4v for now */
284 }
285 
286 void
287 mach_hw_copy_limit(void)
288 {
289 	/* HW copy limits set by individual CPU module */
290 }
291 
292 /*
293  * We need to enable soft ring functionality on Niagara platform since
294  * one strand can't handle interrupts for a 1Gb NIC. Set the tunable
295  * ip_squeue_soft_ring by default on this platform. We can also set
296  * ip_threads_per_cpu to track number of threads per core. The variables
297  * themselves are defined in space.c and used by IP module
298  */
299 extern uint_t ip_threads_per_cpu;
300 extern boolean_t ip_squeue_soft_ring;
301 void
302 startup_platform(void)
303 {
304 	ip_squeue_soft_ring = B_TRUE;
305 }
306 
307 /*
308  * This function sets up hypervisor traptrace buffer
309  * This routine is called by the boot cpu only
310  */
311 void
312 mach_htraptrace_setup(int cpuid)
313 {
314 	TRAP_TRACE_CTL	*ctlp;
315 	int bootcpuid = getprocessorid(); /* invoked on boot cpu only */
316 
317 	if (mach_htraptrace_enable && ((cpuid != bootcpuid) ||
318 	    !htrap_tr0_inuse)) {
319 		ctlp = &trap_trace_ctl[cpuid];
320 		ctlp->d.hvaddr_base = (cpuid == bootcpuid) ? htrap_tr0 :
321 		    contig_mem_alloc_align(HTRAP_TSIZE, HTRAP_TSIZE);
322 		if (ctlp->d.hvaddr_base == NULL) {
323 			ctlp->d.hlimit = 0;
324 			ctlp->d.hpaddr_base = NULL;
325 			cmn_err(CE_WARN, "!cpu%d: failed to allocate HV "
326 			    "traptrace buffer", cpuid);
327 		} else {
328 			ctlp->d.hlimit = HTRAP_TSIZE;
329 			ctlp->d.hpaddr_base = va_to_pa(ctlp->d.hvaddr_base);
330 		}
331 	}
332 }
333 
334 /*
335  * This function enables or disables the hypervisor traptracing
336  */
337 void
338 mach_htraptrace_configure(int cpuid)
339 {
340 	uint64_t ret;
341 	uint64_t prev_buf, prev_bufsize;
342 	uint64_t prev_enable;
343 	uint64_t size;
344 	TRAP_TRACE_CTL	*ctlp;
345 
346 	ctlp = &trap_trace_ctl[cpuid];
347 	if (mach_htraptrace_enable) {
348 		if ((ctlp->d.hvaddr_base != NULL) &&
349 		    ((ctlp->d.hvaddr_base != htrap_tr0) ||
350 		    (!htrap_tr0_inuse))) {
351 			ret = hv_ttrace_buf_info(&prev_buf, &prev_bufsize);
352 			if ((ret == H_EOK) && (prev_bufsize != 0)) {
353 				cmn_err(CE_CONT,
354 				    "!cpu%d: previous HV traptrace buffer of "
355 				    "size 0x%lx at address 0x%lx", cpuid,
356 				    prev_bufsize, prev_buf);
357 			}
358 
359 			ret = hv_ttrace_buf_conf(ctlp->d.hpaddr_base,
360 			    ctlp->d.hlimit /
361 			    (sizeof (struct htrap_trace_record)), &size);
362 			if (ret == H_EOK) {
363 				ret = hv_ttrace_enable(\
364 				    (uint64_t)TRAP_TENABLE_ALL, &prev_enable);
365 				if (ret != H_EOK) {
366 					cmn_err(CE_WARN,
367 					    "!cpu%d: HV traptracing not "
368 					    "enabled, ta: 0x%x returned error: "
369 					    "%ld", cpuid, TTRACE_ENABLE, ret);
370 				} else {
371 					if (ctlp->d.hvaddr_base == htrap_tr0)
372 						htrap_tr0_inuse = 1;
373 				}
374 			} else {
375 				cmn_err(CE_WARN,
376 				    "!cpu%d: HV traptrace buffer not "
377 				    "configured, ta: 0x%x returned error: %ld",
378 				    cpuid, TTRACE_BUF_CONF, ret);
379 			}
380 			/*
381 			 * set hvaddr_base to NULL when traptrace buffer
382 			 * registration fails
383 			 */
384 			if (ret != H_EOK) {
385 				ctlp->d.hvaddr_base = NULL;
386 				ctlp->d.hlimit = 0;
387 				ctlp->d.hpaddr_base = NULL;
388 			}
389 		}
390 	} else {
391 		ret = hv_ttrace_buf_info(&prev_buf, &prev_bufsize);
392 		if ((ret == H_EOK) && (prev_bufsize != 0)) {
393 			ret = hv_ttrace_enable((uint64_t)TRAP_TDISABLE_ALL,
394 			    &prev_enable);
395 			if (ret == H_EOK) {
396 				if (ctlp->d.hvaddr_base == htrap_tr0)
397 					htrap_tr0_inuse = 0;
398 				ctlp->d.hvaddr_base = NULL;
399 				ctlp->d.hlimit = 0;
400 				ctlp->d.hpaddr_base = NULL;
401 			} else
402 				cmn_err(CE_WARN,
403 				    "!cpu%d: HV traptracing is not disabled, "
404 				    "ta: 0x%x returned error: %ld",
405 				    cpuid, TTRACE_ENABLE, ret);
406 		}
407 	}
408 }
409 
410 /*
411  * This function cleans up the hypervisor traptrace buffer
412  */
413 void
414 mach_htraptrace_cleanup(int cpuid)
415 {
416 	if (mach_htraptrace_enable) {
417 		TRAP_TRACE_CTL *ctlp;
418 		caddr_t httrace_buf_va;
419 
420 		ASSERT(cpuid < max_ncpus);
421 		ctlp = &trap_trace_ctl[cpuid];
422 		httrace_buf_va = ctlp->d.hvaddr_base;
423 		if (httrace_buf_va == htrap_tr0) {
424 			bzero(httrace_buf_va, HTRAP_TSIZE);
425 		} else if (httrace_buf_va != NULL) {
426 			contig_mem_free(httrace_buf_va, HTRAP_TSIZE);
427 		}
428 		ctlp->d.hvaddr_base = NULL;
429 		ctlp->d.hlimit = 0;
430 		ctlp->d.hpaddr_base = NULL;
431 	}
432 }
433 
434 /*
435  * Load any required machine class (sun4v) specific drivers.
436  */
437 void
438 load_mach_drivers(void)
439 {
440 	/*
441 	 * We don't want to load these LDOMs-specific
442 	 * modules if domaining has been disabled.  Also,
443 	 * we must be able to run on non-LDOMs firmware.
444 	 */
445 	if (!domaining_enabled)
446 		return;
447 
448 	/*
449 	 * Load the core domain services module
450 	 */
451 	if (modload("misc", "ds") == -1)
452 		cmn_err(CE_NOTE, "!'ds' module failed to load");
453 
454 	/*
455 	 * Load the rest of the domain services
456 	 */
457 	if (modload("misc", "fault_iso") == -1)
458 		cmn_err(CE_NOTE, "!'fault_iso' module failed to load");
459 
460 	if (modload("misc", "platsvc") == -1)
461 		cmn_err(CE_NOTE, "!'platsvc' module failed to load");
462 
463 	if (modload("misc", "dr_cpu") == -1)
464 		cmn_err(CE_NOTE, "!'dr_cpu' module failed to load");
465 
466 	/*
467 	 * Attempt to attach any virtual device servers. These
468 	 * drivers must be loaded at start of day so that they
469 	 * can respond to any updates to the machine description.
470 	 *
471 	 * Since it is quite likely that a domain will not support
472 	 * one or more of these servers, failures are ignored.
473 	 */
474 
475 	/* virtual disk server */
476 	(void) i_ddi_attach_hw_nodes("vds");
477 
478 	/* virtual network switch */
479 	(void) i_ddi_attach_hw_nodes("vsw");
480 
481 	/* virtual console concentrator */
482 	(void) i_ddi_attach_hw_nodes("vcc");
483 }
484